Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'v6.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

New boards: 9Tripod X3568, 100ASK DShanPi A1, LinkEase EasePi R1,
FriendlyElec NanoPi R76S

Interesting archeological addition: RK3368 (2015) gets display
output afterall.

New peripherals: vicap on px30 and rk356x, PCIe Gen2x1 on RK3528,
use actual clock-ids for SCMI clocks - not hardcoded numbers,
CQE support for the eMMC on RK3588.

As well as a number of enablements for individual boards.
For example enablement for the now usable NPU.

* tag 'v6.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (43 commits)
arm64: dts: rockchip: add vicap node to rk356x
arm64: dts: rockchip: add the vip node to px30
arm64: dts: rockchip: fixes audio for 100ASK DshanPi A1
arm64: dts: rockchip: fixes vcc3v3_s0 supply for 100ASK DshanPi A1
arm64: dts: rockchip: fixes ethernet for 100ASK DshanPi A1
arm64: dts: rockchip: fixes regulator for 100ASK DshanPi A1
arm64: dts: rockchip: correct assigned-clock-rates spelling on 2 boards
arm64: dts: rockchip: clean up devicetree for 9Tripod X3568 v4
arm64: dts: rockchip: Enable USB-C DP Alt for Indiedroid Nova
arm64: dts: rockchip: add eMMC CQE support for rk3588
arm64: dts: rockchip: enable HDMI audio on Rock 5 ITX
arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 3C
arm64: dts: rockchip: Add eeprom vcc-supply for Radxa ROCK 5A
arm64: dts: rockchip: Move the EEPROM to correct I2C bus on Radxa ROCK 5A
arm64: dts: rockchip: use SCMI clock id for gpu clock on rk356x
arm64: dts: rockchip: Remove sdmmc max-frequency on RK3588S EVB1 board
arm64: dts: rockchip: Remove sdmmc max-frequency for Radxa ROCK 5 ITX/5B/5B+/5T
arm64: dts: rockchip: Switch microSD card detect to gpio on Radxa ROCK 5 ITX/5C
arm64: dts: rockchip: Add devicetree for the 9Tripod X3568 v4
dt-bindings: arm: rockchip: Add 9Tripod X3568 series
...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

+3603 -36
+21
Documentation/devicetree/bindings/arm/rockchip.yaml
··· 15 15 compatible: 16 16 oneOf: 17 17 18 + - description: 100ASK DshanPi A1 board 19 + items: 20 + - const: 100ask,dshanpi-a1 21 + - const: rockchip,rk3576 22 + 18 23 - description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition) 19 24 items: 20 25 - const: vamrs,ficus ··· 29 24 items: 30 25 - const: vamrs,rock960 31 26 - const: rockchip,rk3399 27 + 28 + - description: 9Tripod X3568 series board 29 + items: 30 + - enum: 31 + - 9tripod,x3568-v4 32 + - const: rockchip,rk3568 32 33 33 34 - description: Amarula Vyasa RK3288 34 35 items: ··· 340 329 - friendlyarm,nanopi-r6c 341 330 - friendlyarm,nanopi-r6s 342 331 - const: rockchip,rk3588s 332 + 333 + - description: FriendlyElec NanoPi R76S 334 + items: 335 + - const: friendlyarm,nanopi-r76s 336 + - const: rockchip,rk3576 343 337 344 338 - description: FriendlyElec NanoPi Zero2 345 339 items: ··· 763 747 items: 764 748 - const: lckfb,tspi-rk3566 765 749 - const: rockchip,rk3566 750 + 751 + - description: LinkEase EasePi R1 752 + items: 753 + - const: linkease,easepi-r1 754 + - const: rockchip,rk3568 766 755 767 756 - description: Luckfox Core3576 Module based boards 768 757 items:
+4
Documentation/devicetree/bindings/vendor-prefixes.yaml
··· 30 30 description: 70mai Co., Ltd. 31 31 "^8dev,.*": 32 32 description: 8devices, UAB 33 + "^9tripod,.*": 34 + description: Shenzhen 9Tripod Innovation and Development CO., LTD. 33 35 "^abb,.*": 34 36 description: ABB 35 37 "^abilis,.*": ··· 909 907 description: Lincoln Technology Solutions 910 908 "^lineartechnology,.*": 911 909 description: Linear Technology 910 + "^linkease,.*": 911 + description: Shenzhen LinkEase Network Technology Co., Ltd. 912 912 "^linksprite,.*": 913 913 description: LinkSprite Technologies, Inc. 914 914 "^linksys,.*":
+4
arch/arm64/boot/dts/rockchip/Makefile
··· 130 130 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb 131 131 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-cb2-manta.dtb 132 132 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2.dtb 133 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-9tripod-x3568-v4.dtb 133 134 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb 135 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb 134 136 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb 135 137 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb 136 138 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb ··· 152 150 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb 153 151 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo 154 152 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo 153 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-100ask-dshanpi-a1.dtb 155 154 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb 156 155 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo 157 156 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb 158 157 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb 159 158 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb 159 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb 160 160 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-roc-pc.dtb 161 161 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb 162 162 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
+12
arch/arm64/boot/dts/rockchip/px30.dtsi
··· 1241 1241 status = "disabled"; 1242 1242 }; 1243 1243 1244 + cif: video-capture@ff490000 { 1245 + compatible = "rockchip,px30-vip"; 1246 + reg = <0x0 0xff490000 0x0 0x200>; 1247 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1248 + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; 1249 + clock-names = "aclk", "hclk", "pclk"; 1250 + power-domains = <&power PX30_PD_VI>; 1251 + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1252 + reset-names = "axi", "ahb", "pclkin"; 1253 + status = "disabled"; 1254 + }; 1255 + 1244 1256 isp: isp@ff4a0000 { 1245 1257 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/ 1246 1258 reg = <0x0 0xff4a0000 0x0 0x8000>;
+1 -1
arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
··· 184 184 185 185 &gmac2phy { 186 186 assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; 187 - assigned-clock-rate = <50000000>; 187 + assigned-clock-rates = <50000000>; 188 188 assigned-clocks = <&cru SCLK_MAC2PHY>; 189 189 status = "okay"; 190 190 };
+1 -1
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
··· 101 101 &gmac2phy { 102 102 phy-supply = <&vcc_phy>; 103 103 clock_in_out = "output"; 104 - assigned-clock-rate = <50000000>; 104 + assigned-clock-rates = <50000000>; 105 105 assigned-clocks = <&cru SCLK_MAC2PHY>; 106 106 assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; 107 107 status = "okay";
+73
arch/arm64/boot/dts/rockchip/rk3368.dtsi
··· 140 140 }; 141 141 }; 142 142 143 + display_subsystem: display-subsystem { 144 + compatible = "rockchip,display-subsystem"; 145 + ports = <&vop_out>; 146 + status = "disabled"; 147 + }; 148 + 143 149 arm-pmu { 144 150 compatible = "arm,cortex-a53-pmu"; 145 151 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, ··· 853 847 status = "disabled"; 854 848 }; 855 849 850 + vop: vop@ff930000 { 851 + compatible = "rockchip,rk3368-vop"; 852 + reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>; 853 + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 854 + assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 855 + assigned-clock-rates = <400000000>, <200000000>; 856 + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 857 + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 858 + iommus = <&vop_mmu>; 859 + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 860 + reset-names = "axi", "ahb", "dclk"; 861 + status = "disabled"; 862 + 863 + vop_out: port { 864 + #address-cells = <1>; 865 + #size-cells = <0>; 866 + 867 + vop_out_dsi: endpoint@0 { 868 + reg = <0>; 869 + remote-endpoint = <&dsi_in_vop>; 870 + }; 871 + }; 872 + }; 873 + 856 874 vop_mmu: iommu@ff930300 { 857 875 compatible = "rockchip,iommu"; 858 876 reg = <0x0 0xff930300 0x0 0x100>; ··· 885 855 clock-names = "aclk", "iface"; 886 856 power-domains = <&power RK3368_PD_VIO>; 887 857 #iommu-cells = <0>; 858 + status = "disabled"; 859 + }; 860 + 861 + mipi_dsi: dsi@ff960000 { 862 + compatible = "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi"; 863 + reg = <0x0 0xff960000 0x0 0x4000>; 864 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 865 + clocks = <&cru PCLK_MIPI_DSI0>; 866 + clock-names = "pclk"; 867 + phys = <&dphy>; 868 + phy-names = "dphy"; 869 + resets = <&cru SRST_MIPIDSI0>; 870 + reset-names = "apb"; 871 + rockchip,grf = <&grf>; 872 + status = "disabled"; 873 + 874 + ports { 875 + #address-cells = <1>; 876 + #size-cells = <0>; 877 + 878 + mipi_in: port@0 { 879 + reg = <0>; 880 + 881 + dsi_in_vop: endpoint { 882 + remote-endpoint = <&vop_out_dsi>; 883 + }; 884 + }; 885 + 886 + mipi_out: port@1 { 887 + reg = <1>; 888 + }; 889 + 890 + }; 891 + }; 892 + 893 + dphy: phy@ff968000 { 894 + compatible = "rockchip,rk3368-dsi-dphy"; 895 + reg = <0x0 0xff968000 0x0 0x4000>; 896 + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>; 897 + clock-names = "ref", "pclk"; 898 + #phy-cells = <0>; 899 + resets = <&cru SRST_MIPIDPHYTX>; 900 + reset-names = "apb"; 888 901 status = "disabled"; 889 902 }; 890 903
+12
arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
··· 171 171 }; 172 172 }; 173 173 174 + &combphy { 175 + status = "okay"; 176 + }; 177 + 174 178 &cpu0 { 175 179 cpu-supply = <&vdd_arm>; 176 180 }; ··· 231 227 reset-deassert-us = <100000>; 232 228 reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; 233 229 }; 230 + }; 231 + 232 + &pcie { 233 + pinctrl-names = "default"; 234 + pinctrl-0 = <&pciem1_pins>; 235 + reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; 236 + vpcie3v3-supply = <&vcc_3v3>; 237 + status = "okay"; 234 238 }; 235 239 236 240 &pinctrl {
+55 -1
arch/arm64/boot/dts/rockchip/rk3528.dtsi
··· 7 7 #include <dt-bindings/gpio/gpio.h> 8 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 9 #include <dt-bindings/interrupt-controller/irq.h> 10 + #include <dt-bindings/phy/phy.h> 10 11 #include <dt-bindings/pinctrl/rockchip.h> 11 12 #include <dt-bindings/clock/rockchip,rk3528-cru.h> 12 13 #include <dt-bindings/power/rockchip,rk3528-power.h> ··· 279 278 280 279 soc { 281 280 compatible = "simple-bus"; 282 - ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; 281 + ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>; 283 282 #address-cells = <2>; 284 283 #size-cells = <2>; 284 + 285 + pcie: pcie@fe000000 { 286 + compatible = "rockchip,rk3528-pcie", 287 + "rockchip,rk3568-pcie"; 288 + reg = <0x0 0xfe000000 0x0 0x400000>, 289 + <0x0 0xfe4f0000 0x0 0x010000>, 290 + <0x0 0xfc000000 0x0 0x100000>; 291 + reg-names = "dbi", "apb", "config"; 292 + bus-range = <0x0 0xff>; 293 + clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, 294 + <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>, 295 + <&cru CLK_PCIE_AUX>; 296 + clock-names = "aclk_mst", "aclk_slv", 297 + "aclk_dbi", "pclk", 298 + "aux"; 299 + device_type = "pci"; 300 + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 301 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 302 + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 303 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 304 + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 305 + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 306 + interrupt-names = "sys", "pmc", "msg", "legacy", "err", 307 + "msi"; 308 + #interrupt-cells = <1>; 309 + interrupt-map-mask = <0 0 0 7>; 310 + interrupt-map = <0 0 0 1 &pcie_intc 0>, 311 + <0 0 0 2 &pcie_intc 1>, 312 + <0 0 0 3 &pcie_intc 2>, 313 + <0 0 0 4 &pcie_intc 3>; 314 + linux,pci-domain = <0>; 315 + max-link-speed = <2>; 316 + num-lanes = <1>; 317 + phys = <&combphy PHY_TYPE_PCIE>; 318 + phy-names = "pcie-phy"; 319 + power-domains = <&power RK3528_PD_VPU>; 320 + ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>, 321 + <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>, 322 + <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; 323 + resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>; 324 + reset-names = "pwr", "pipe"; 325 + #address-cells = <3>; 326 + #size-cells = <2>; 327 + status = "disabled"; 328 + 329 + pcie_intc: legacy-interrupt-controller { 330 + interrupt-controller; 331 + interrupt-parent = <&gic>; 332 + interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>; 333 + #address-cells = <0>; 334 + #interrupt-cells = <1>; 335 + }; 336 + }; 285 337 286 338 gic: interrupt-controller@fed01000 { 287 339 compatible = "arm,gic-400";
+1
arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
··· 466 466 compatible = "belling,bl24c16a", "atmel,24c16"; 467 467 reg = <0x50>; 468 468 pagesize = <16>; 469 + vcc-supply = <&vcca1v8_pmu>; 469 470 }; 470 471 }; 471 472
+880
arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + 3 + /dts-v1/; 4 + #include <dt-bindings/gpio/gpio.h> 5 + #include <dt-bindings/input/input.h> 6 + #include <dt-bindings/leds/common.h> 7 + #include <dt-bindings/pinctrl/rockchip.h> 8 + #include <dt-bindings/soc/rockchip,vop2.h> 9 + #include "rk3568.dtsi" 10 + 11 + / { 12 + model = "9Tripod X3568 v4"; 13 + compatible = "9tripod,x3568-v4", "rockchip,rk3568"; 14 + 15 + aliases { 16 + ethernet0 = &gmac0; 17 + ethernet1 = &gmac1; 18 + mmc0 = &sdhci; 19 + mmc1 = &sdmmc0; 20 + mmc2 = &sdmmc2; 21 + rtc0 = &rtc0; 22 + }; 23 + 24 + chosen { 25 + stdout-path = "serial2:1500000n8"; 26 + }; 27 + 28 + adc-keys { 29 + compatible = "adc-keys"; 30 + io-channels = <&saradc 0>; 31 + io-channel-names = "buttons"; 32 + keyup-threshold-microvolt = <1800000>; 33 + poll-interval = <100>; 34 + 35 + button-vol-up { 36 + label = "volume up"; 37 + linux,code = <KEY_VOLUMEUP>; 38 + press-threshold-microvolt = <50000>; 39 + }; 40 + 41 + button-vol-down { 42 + label = "volume down"; 43 + linux,code = <KEY_VOLUMEDOWN>; 44 + press-threshold-microvolt = <500000>; 45 + }; 46 + }; 47 + 48 + hdmi-con { 49 + compatible = "hdmi-connector"; 50 + type = "a"; 51 + 52 + port { 53 + hdmi_con_in: endpoint { 54 + remote-endpoint = <&hdmi_out_con>; 55 + }; 56 + }; 57 + }; 58 + 59 + leds { 60 + compatible = "gpio-leds"; 61 + 62 + led_work: led-0 { 63 + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 64 + function = LED_FUNCTION_HEARTBEAT; 65 + color = <LED_COLOR_ID_BLUE>; 66 + linux,default-trigger = "heartbeat"; 67 + pinctrl-names = "default"; 68 + pinctrl-0 = <&led_work_en>; 69 + }; 70 + }; 71 + 72 + rk809-sound { 73 + compatible = "simple-audio-card"; 74 + simple-audio-card,format = "i2s"; 75 + simple-audio-card,name = "Analog RK809"; 76 + simple-audio-card,mclk-fs = <256>; 77 + 78 + simple-audio-card,cpu { 79 + sound-dai = <&i2s1_8ch>; 80 + }; 81 + simple-audio-card,codec { 82 + sound-dai = <&rk809>; 83 + }; 84 + }; 85 + 86 + pdm_codec: pdm-codec { 87 + compatible = "dmic-codec"; 88 + num-channels = <2>; 89 + #sound-dai-cells = <0>; 90 + }; 91 + 92 + pdm_sound: pdm-sound { 93 + compatible = "simple-audio-card"; 94 + simple-audio-card,name = "microphone"; 95 + 96 + simple-audio-card,cpu { 97 + sound-dai = <&pdm>; 98 + }; 99 + 100 + simple-audio-card,codec { 101 + sound-dai = <&pdm_codec>; 102 + }; 103 + }; 104 + 105 + spdif_dit: spdif-dit { 106 + compatible = "linux,spdif-dit"; 107 + #sound-dai-cells = <0>; 108 + }; 109 + 110 + spdif_sound: spdif-sound { 111 + compatible = "simple-audio-card"; 112 + simple-audio-card,name = "SPDIF"; 113 + 114 + simple-audio-card,cpu { 115 + sound-dai = <&spdif>; 116 + }; 117 + simple-audio-card,codec { 118 + sound-dai = <&spdif_dit>; 119 + }; 120 + }; 121 + 122 + sdio_pwrseq: sdio-pwrseq { 123 + compatible = "mmc-pwrseq-simple"; 124 + clocks = <&rk809 1>; 125 + clock-names = "ext_clock"; 126 + pinctrl-names = "default"; 127 + pinctrl-0 = <&wifi_enable>; 128 + post-power-on-delay-ms = <100>; 129 + power-off-delay-us = <300>; 130 + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; 131 + }; 132 + 133 + dc_12v: regulator-dc-12v { 134 + compatible = "regulator-fixed"; 135 + regulator-name = "dc_12v"; 136 + regulator-always-on; 137 + regulator-boot-on; 138 + regulator-min-microvolt = <12000000>; 139 + regulator-max-microvolt = <12000000>; 140 + }; 141 + 142 + pcie30_avdd0v9: regulator-pcie30-avdd0v9 { 143 + compatible = "regulator-fixed"; 144 + regulator-name = "pcie30_avdd0v9"; 145 + regulator-always-on; 146 + regulator-boot-on; 147 + regulator-min-microvolt = <900000>; 148 + regulator-max-microvolt = <900000>; 149 + vin-supply = <&vcc3v3_sys>; 150 + }; 151 + 152 + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { 153 + compatible = "regulator-fixed"; 154 + regulator-name = "pcie30_avdd1v8"; 155 + regulator-always-on; 156 + regulator-boot-on; 157 + regulator-min-microvolt = <1800000>; 158 + regulator-max-microvolt = <1800000>; 159 + vin-supply = <&vcc3v3_sys>; 160 + }; 161 + 162 + vcc3v3_sys: regulator-vcc3v3-sys { 163 + compatible = "regulator-fixed"; 164 + regulator-name = "vcc3v3_sys"; 165 + regulator-always-on; 166 + regulator-boot-on; 167 + regulator-min-microvolt = <3300000>; 168 + regulator-max-microvolt = <3300000>; 169 + vin-supply = <&dc_12v>; 170 + }; 171 + 172 + vcc3v3_pcie: regulator-vcc3v3-pcie { 173 + compatible = "regulator-gpio"; 174 + regulator-name = "vcc3v3_pcie"; 175 + regulator-min-microvolt = <100000>; 176 + regulator-max-microvolt = <3300000>; 177 + pinctrl-names = "default"; 178 + pinctrl-0 = <&vcc3v3_pcie_en_pin>; 179 + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; 180 + gpios-states = <1>; 181 + states = <100000 0>, <3300000 1>; 182 + startup-delay-us = <5000>; 183 + }; 184 + 185 + vcc5v0_sys: regulator-vcc5v0-sys { 186 + compatible = "regulator-fixed"; 187 + regulator-name = "vcc5v0_sys"; 188 + regulator-always-on; 189 + regulator-boot-on; 190 + regulator-min-microvolt = <5000000>; 191 + regulator-max-microvolt = <5000000>; 192 + vin-supply = <&dc_12v>; 193 + }; 194 + 195 + vcc5v0_usb: regulator-vcc5v0-usb { 196 + compatible = "regulator-fixed"; 197 + regulator-name = "vcc5v0_usb"; 198 + regulator-always-on; 199 + regulator-boot-on; 200 + regulator-min-microvolt = <5000000>; 201 + regulator-max-microvolt = <5000000>; 202 + vin-supply = <&dc_12v>; 203 + }; 204 + 205 + vcc5v0_usb_host: regulator-vcc5v0-usb-host { 206 + compatible = "regulator-fixed"; 207 + enable-active-high; 208 + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; 209 + pinctrl-names = "default"; 210 + pinctrl-0 = <&vcc5v0_usb_host_en>; 211 + regulator-name = "vcc5v0_usb_host"; 212 + regulator-min-microvolt = <5000000>; 213 + regulator-max-microvolt = <5000000>; 214 + vin-supply = <&vcc5v0_usb>; 215 + }; 216 + 217 + vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { 218 + compatible = "regulator-fixed"; 219 + enable-active-high; 220 + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 221 + pinctrl-names = "default"; 222 + pinctrl-0 = <&vcc5v0_usb_otg_en>; 223 + regulator-name = "vcc5v0_usb_otg"; 224 + regulator-min-microvolt = <5000000>; 225 + regulator-max-microvolt = <5000000>; 226 + vin-supply = <&vcc5v0_usb>; 227 + }; 228 + }; 229 + 230 + &can1 { 231 + assigned-clocks = <&cru CLK_CAN1>; 232 + assigned-clock-rates = <150000000>; 233 + pinctrl-names = "default"; 234 + pinctrl-0 = <&can1m1_pins>; 235 + status = "okay"; 236 + }; 237 + 238 + /* used for usb_host0_xhci */ 239 + &combphy0 { 240 + status = "okay"; 241 + }; 242 + 243 + /* used for usb_host1_xhci */ 244 + &combphy1 { 245 + status = "okay"; 246 + }; 247 + 248 + /* connected to sata2 */ 249 + &combphy2 { 250 + status = "okay"; 251 + }; 252 + 253 + &cpu0 { 254 + cpu-supply = <&vdd_cpu>; 255 + }; 256 + 257 + &cpu1 { 258 + cpu-supply = <&vdd_cpu>; 259 + }; 260 + 261 + &cpu2 { 262 + cpu-supply = <&vdd_cpu>; 263 + }; 264 + 265 + &cpu3 { 266 + cpu-supply = <&vdd_cpu>; 267 + }; 268 + 269 + &gmac0 { 270 + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 271 + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 272 + assigned-clock-rates = <0>, <125000000>; 273 + clock_in_out = "output"; 274 + pinctrl-names = "default"; 275 + pinctrl-0 = <&gmac0_miim 276 + &gmac0_tx_bus2 277 + &gmac0_rx_bus2 278 + &gmac0_rgmii_clk 279 + &gmac0_rgmii_bus>; 280 + phy-handle = <&rgmii_phy0>; 281 + phy-mode = "rgmii-id"; 282 + status = "okay"; 283 + }; 284 + 285 + &gmac1 { 286 + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 287 + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 288 + assigned-clock-rates = <0>, <125000000>; 289 + clock_in_out = "output"; 290 + pinctrl-names = "default"; 291 + pinctrl-0 = <&gmac1m1_miim 292 + &gmac1m1_tx_bus2 293 + &gmac1m1_rx_bus2 294 + &gmac1m1_rgmii_clk 295 + &gmac1m1_rgmii_bus>; 296 + phy-handle = <&rgmii_phy1>; 297 + phy-mode = "rgmii-id"; 298 + status = "okay"; 299 + }; 300 + 301 + &gpu { 302 + mali-supply = <&vdd_gpu>; 303 + status = "okay"; 304 + }; 305 + 306 + &hdmi { 307 + avdd-0v9-supply = <&vdda0v9_image>; 308 + avdd-1v8-supply = <&vcca1v8_image>; 309 + status = "okay"; 310 + }; 311 + 312 + &hdmi_in { 313 + hdmi_in_vp0: endpoint { 314 + remote-endpoint = <&vp0_out_hdmi>; 315 + }; 316 + }; 317 + 318 + &hdmi_out { 319 + hdmi_out_con: endpoint { 320 + remote-endpoint = <&hdmi_con_in>; 321 + }; 322 + }; 323 + 324 + &hdmi_sound { 325 + status = "okay"; 326 + }; 327 + 328 + &i2c0 { 329 + status = "okay"; 330 + 331 + vdd_cpu: regulator@1c { 332 + compatible = "tcs,tcs4525"; 333 + reg = <0x1c>; 334 + fcs,suspend-voltage-selector = <1>; 335 + regulator-name = "vdd_cpu"; 336 + regulator-always-on; 337 + regulator-boot-on; 338 + regulator-min-microvolt = <800000>; 339 + regulator-max-microvolt = <1150000>; 340 + regulator-ramp-delay = <2300>; 341 + vin-supply = <&vcc5v0_sys>; 342 + 343 + regulator-state-mem { 344 + regulator-off-in-suspend; 345 + }; 346 + }; 347 + 348 + rk809: pmic@20 { 349 + compatible = "rockchip,rk809"; 350 + reg = <0x20>; 351 + interrupt-parent = <&gpio0>; 352 + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 353 + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; 354 + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; 355 + #clock-cells = <1>; 356 + clock-names = "mclk"; 357 + clocks = <&cru I2S1_MCLKOUT_TX>; 358 + pinctrl-names = "default"; 359 + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; 360 + system-power-controller; 361 + #sound-dai-cells = <0>; 362 + vcc1-supply = <&vcc3v3_sys>; 363 + vcc2-supply = <&vcc3v3_sys>; 364 + vcc3-supply = <&vcc3v3_sys>; 365 + vcc4-supply = <&vcc3v3_sys>; 366 + vcc5-supply = <&vcc3v3_sys>; 367 + vcc6-supply = <&vcc3v3_sys>; 368 + vcc7-supply = <&vcc3v3_sys>; 369 + vcc8-supply = <&vcc3v3_sys>; 370 + vcc9-supply = <&vcc3v3_sys>; 371 + wakeup-source; 372 + 373 + regulators { 374 + vdd_logic: DCDC_REG1 { 375 + regulator-name = "vdd_logic"; 376 + regulator-always-on; 377 + regulator-boot-on; 378 + regulator-initial-mode = <0x2>; 379 + regulator-min-microvolt = <500000>; 380 + regulator-max-microvolt = <1350000>; 381 + regulator-ramp-delay = <6001>; 382 + 383 + regulator-state-mem { 384 + regulator-off-in-suspend; 385 + }; 386 + }; 387 + 388 + vdd_gpu: DCDC_REG2 { 389 + regulator-name = "vdd_gpu"; 390 + regulator-always-on; 391 + regulator-initial-mode = <0x2>; 392 + regulator-min-microvolt = <500000>; 393 + regulator-max-microvolt = <1350000>; 394 + regulator-ramp-delay = <6001>; 395 + 396 + regulator-state-mem { 397 + regulator-off-in-suspend; 398 + }; 399 + }; 400 + 401 + vcc_ddr: DCDC_REG3 { 402 + regulator-name = "vcc_ddr"; 403 + regulator-always-on; 404 + regulator-boot-on; 405 + regulator-initial-mode = <0x2>; 406 + 407 + regulator-state-mem { 408 + regulator-on-in-suspend; 409 + }; 410 + }; 411 + 412 + vdd_npu: DCDC_REG4 { 413 + regulator-name = "vdd_npu"; 414 + regulator-initial-mode = <0x2>; 415 + regulator-min-microvolt = <500000>; 416 + regulator-max-microvolt = <1350000>; 417 + regulator-ramp-delay = <6001>; 418 + 419 + regulator-state-mem { 420 + regulator-off-in-suspend; 421 + }; 422 + }; 423 + 424 + vcc_1v8: DCDC_REG5 { 425 + regulator-name = "vcc_1v8"; 426 + regulator-always-on; 427 + regulator-boot-on; 428 + regulator-min-microvolt = <1800000>; 429 + regulator-max-microvolt = <1800000>; 430 + 431 + regulator-state-mem { 432 + regulator-off-in-suspend; 433 + }; 434 + }; 435 + 436 + vdda0v9_image: LDO_REG1 { 437 + regulator-name = "vdda0v9_image"; 438 + regulator-min-microvolt = <900000>; 439 + regulator-max-microvolt = <900000>; 440 + 441 + regulator-state-mem { 442 + regulator-off-in-suspend; 443 + }; 444 + }; 445 + 446 + vdda_0v9: LDO_REG2 { 447 + regulator-name = "vdda_0v9"; 448 + regulator-always-on; 449 + regulator-boot-on; 450 + regulator-min-microvolt = <900000>; 451 + regulator-max-microvolt = <900000>; 452 + 453 + regulator-state-mem { 454 + regulator-off-in-suspend; 455 + }; 456 + }; 457 + 458 + vdda0v9_pmu: LDO_REG3 { 459 + regulator-name = "vdda0v9_pmu"; 460 + regulator-always-on; 461 + regulator-boot-on; 462 + regulator-min-microvolt = <900000>; 463 + regulator-max-microvolt = <900000>; 464 + 465 + regulator-state-mem { 466 + regulator-on-in-suspend; 467 + regulator-suspend-microvolt = <900000>; 468 + }; 469 + }; 470 + 471 + vccio_acodec: LDO_REG4 { 472 + regulator-name = "vccio_acodec"; 473 + regulator-always-on; 474 + regulator-min-microvolt = <3300000>; 475 + regulator-max-microvolt = <3300000>; 476 + 477 + regulator-state-mem { 478 + regulator-off-in-suspend; 479 + }; 480 + }; 481 + 482 + vccio_sd: LDO_REG5 { 483 + regulator-name = "vccio_sd"; 484 + regulator-min-microvolt = <1800000>; 485 + regulator-max-microvolt = <3300000>; 486 + 487 + regulator-state-mem { 488 + regulator-off-in-suspend; 489 + }; 490 + }; 491 + 492 + vcc3v3_pmu: LDO_REG6 { 493 + regulator-name = "vcc3v3_pmu"; 494 + regulator-always-on; 495 + regulator-boot-on; 496 + regulator-min-microvolt = <3300000>; 497 + regulator-max-microvolt = <3300000>; 498 + 499 + regulator-state-mem { 500 + regulator-on-in-suspend; 501 + regulator-suspend-microvolt = <3300000>; 502 + }; 503 + }; 504 + 505 + vcca_1v8: LDO_REG7 { 506 + regulator-name = "vcca_1v8"; 507 + regulator-always-on; 508 + regulator-boot-on; 509 + regulator-min-microvolt = <1800000>; 510 + regulator-max-microvolt = <1800000>; 511 + 512 + regulator-state-mem { 513 + regulator-off-in-suspend; 514 + }; 515 + }; 516 + 517 + vcca1v8_pmu: LDO_REG8 { 518 + regulator-name = "vcca1v8_pmu"; 519 + regulator-always-on; 520 + regulator-boot-on; 521 + regulator-min-microvolt = <1800000>; 522 + regulator-max-microvolt = <1800000>; 523 + 524 + regulator-state-mem { 525 + regulator-on-in-suspend; 526 + regulator-suspend-microvolt = <1800000>; 527 + }; 528 + }; 529 + 530 + vcca1v8_image: LDO_REG9 { 531 + regulator-name = "vcca1v8_image"; 532 + regulator-min-microvolt = <1800000>; 533 + regulator-max-microvolt = <1800000>; 534 + 535 + regulator-state-mem { 536 + regulator-off-in-suspend; 537 + }; 538 + }; 539 + 540 + vcc_3v3: SWITCH_REG1 { 541 + regulator-name = "vcc_3v3"; 542 + regulator-always-on; 543 + regulator-boot-on; 544 + 545 + regulator-state-mem { 546 + regulator-off-in-suspend; 547 + }; 548 + }; 549 + 550 + vcc3v3_sd: SWITCH_REG2 { 551 + regulator-name = "vcc3v3_sd"; 552 + 553 + regulator-state-mem { 554 + regulator-off-in-suspend; 555 + }; 556 + }; 557 + }; 558 + 559 + codec { 560 + rockchip,mic-in-differential; 561 + }; 562 + }; 563 + }; 564 + 565 + &i2c5 { 566 + status = "okay"; 567 + 568 + rtc0: rtc@51 { 569 + compatible = "nxp,pcf8563"; 570 + reg = <0x51>; 571 + #clock-cells = <0>; 572 + }; 573 + }; 574 + 575 + &i2s0_8ch { 576 + status = "okay"; 577 + }; 578 + 579 + &i2s1_8ch { 580 + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; 581 + rockchip,trcm-sync-tx-only; 582 + status = "okay"; 583 + }; 584 + 585 + /* used for AP6275S Bluetooth Sound */ 586 + &i2s3_2ch { 587 + status = "okay"; 588 + }; 589 + 590 + &mdio0 { 591 + rgmii_phy0: ethernet-phy@3 { 592 + compatible = "ethernet-phy-ieee802.3-c22"; 593 + reg = <3>; 594 + reset-assert-us = <20000>; 595 + reset-deassert-us = <100000>; 596 + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 597 + 598 + leds { 599 + #address-cells = <1>; 600 + #size-cells = <0>; 601 + 602 + led@1 { 603 + reg = <1>; 604 + color = <LED_COLOR_ID_GREEN>; 605 + function = LED_FUNCTION_LAN; 606 + default-state = "keep"; 607 + }; 608 + 609 + /* Note: The LED polarity is inverted */ 610 + led@2 { 611 + reg = <2>; 612 + color = <LED_COLOR_ID_AMBER>; 613 + function = LED_FUNCTION_LAN; 614 + default-state = "keep"; 615 + }; 616 + }; 617 + }; 618 + }; 619 + 620 + &mdio1 { 621 + rgmii_phy1: ethernet-phy@2 { 622 + compatible = "ethernet-phy-ieee802.3-c22"; 623 + reg = <2>; 624 + reset-assert-us = <20000>; 625 + reset-deassert-us = <100000>; 626 + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 627 + 628 + leds { 629 + #address-cells = <1>; 630 + #size-cells = <0>; 631 + 632 + led@1 { 633 + reg = <1>; 634 + color = <LED_COLOR_ID_GREEN>; 635 + function = LED_FUNCTION_LAN; 636 + default-state = "keep"; 637 + }; 638 + 639 + /* Note: The LED polarity is inverted */ 640 + led@2 { 641 + reg = <2>; 642 + color = <LED_COLOR_ID_AMBER>; 643 + function = LED_FUNCTION_LAN; 644 + default-state = "keep"; 645 + }; 646 + }; 647 + }; 648 + }; 649 + 650 + &pcie30phy { 651 + status = "okay"; 652 + }; 653 + 654 + &pcie3x2 { 655 + pinctrl-names = "default"; 656 + pinctrl-0 = <&pcie_reset_pin>; 657 + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 658 + vpcie3v3-supply = <&vcc3v3_pcie>; 659 + status = "okay"; 660 + }; 661 + 662 + &pdm { 663 + status = "okay"; 664 + }; 665 + 666 + &pinctrl { 667 + leds { 668 + led_work_en: led_work_en { 669 + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 670 + }; 671 + }; 672 + 673 + pmic { 674 + pmic_int: pmic_int { 675 + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 676 + }; 677 + }; 678 + 679 + sdio-pwrseq { 680 + wifi_enable: wifi-enable { 681 + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 682 + }; 683 + }; 684 + 685 + usb { 686 + vcc5v0_usb_host_en: vcc5v0_usb_host_en { 687 + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 688 + }; 689 + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { 690 + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 691 + }; 692 + }; 693 + 694 + pcie { 695 + pcie_reset_pin: pcie-reset-pin { 696 + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; 697 + }; 698 + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { 699 + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 700 + }; 701 + }; 702 + }; 703 + 704 + &pmu_io_domains { 705 + pmuio1-supply = <&vcc3v3_pmu>; 706 + pmuio2-supply = <&vcc3v3_pmu>; 707 + vccio1-supply = <&vccio_acodec>; 708 + vccio2-supply = <&vcc_1v8>; 709 + vccio3-supply = <&vccio_sd>; 710 + vccio4-supply = <&vcc_1v8>; 711 + vccio5-supply = <&vcc_3v3>; 712 + vccio6-supply = <&vcc_1v8>; 713 + vccio7-supply = <&vcc_3v3>; 714 + status = "okay"; 715 + }; 716 + 717 + &pwm4 { 718 + status = "okay"; 719 + }; 720 + 721 + /* Required remotectl for IR receiver */ 722 + &pwm7 { 723 + status = "disabled"; 724 + }; 725 + 726 + &saradc { 727 + vref-supply = <&vcca_1v8>; 728 + status = "okay"; 729 + }; 730 + 731 + &sata2 { 732 + status = "okay"; 733 + }; 734 + 735 + /* used for eMMC */ 736 + &sdhci { 737 + bus-width = <8>; 738 + max-frequency = <200000000>; 739 + mmc-hs200-1_8v; 740 + non-removable; 741 + pinctrl-names = "default"; 742 + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; 743 + status = "okay"; 744 + }; 745 + 746 + /* used for microSD (TF) Slot */ 747 + &sdmmc0 { 748 + bus-width = <4>; 749 + cap-sd-highspeed; 750 + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 751 + disable-wp; 752 + pinctrl-names = "default"; 753 + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 754 + sd-uhs-sdr104; 755 + vmmc-supply = <&vcc3v3_sd>; 756 + vqmmc-supply = <&vccio_sd>; 757 + status = "okay"; 758 + }; 759 + 760 + /* used for AP6275S WiFi */ 761 + &sdmmc2 { 762 + bus-width = <4>; 763 + cap-sd-highspeed; 764 + cap-sdio-irq; 765 + keep-power-in-suspend; 766 + mmc-pwrseq = <&sdio_pwrseq>; 767 + non-removable; 768 + pinctrl-names = "default"; 769 + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 770 + sd-uhs-sdr104; 771 + vmmc-supply = <&vcc3v3_sys>; 772 + vqmmc-supply = <&vcc_1v8>; 773 + status = "okay"; 774 + }; 775 + 776 + &spdif { 777 + status = "okay"; 778 + }; 779 + 780 + &tsadc { 781 + rockchip,hw-tshut-mode = <1>; 782 + rockchip,hw-tshut-polarity = <0>; 783 + status = "okay"; 784 + }; 785 + 786 + /* used for Debug */ 787 + &uart2 { 788 + status = "okay"; 789 + }; 790 + 791 + &uart3 { 792 + pinctrl-0 = <&uart3m1_xfer>; 793 + status = "okay"; 794 + }; 795 + 796 + &uart4 { 797 + pinctrl-0 = <&uart4m1_xfer>; 798 + status = "okay"; 799 + }; 800 + 801 + /* used for WiFi/BT AP6275S */ 802 + &uart8 { 803 + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; 804 + status = "okay"; 805 + }; 806 + 807 + &uart9 { 808 + pinctrl-0 = <&uart9m1_xfer>; 809 + status = "okay"; 810 + }; 811 + 812 + &usb_host0_ehci { 813 + status = "okay"; 814 + }; 815 + 816 + &usb_host0_ohci { 817 + status = "okay"; 818 + }; 819 + 820 + &usb_host0_xhci { 821 + extcon = <&usb2phy0>; 822 + status = "okay"; 823 + }; 824 + 825 + &usb_host1_ehci { 826 + status = "okay"; 827 + }; 828 + 829 + &usb_host1_ohci { 830 + status = "okay"; 831 + }; 832 + 833 + &usb_host1_xhci { 834 + status = "okay"; 835 + }; 836 + 837 + &usb2phy0 { 838 + status = "okay"; 839 + }; 840 + 841 + &usb2phy0_host { 842 + phy-supply = <&vcc5v0_usb_host>; 843 + status = "okay"; 844 + }; 845 + 846 + &usb2phy0_otg { 847 + phy-supply = <&vcc5v0_usb_otg>; 848 + status = "okay"; 849 + }; 850 + 851 + &usb2phy1 { 852 + status = "okay"; 853 + }; 854 + 855 + &usb2phy1_host { 856 + phy-supply = <&vcc5v0_usb_host>; 857 + status = "okay"; 858 + }; 859 + 860 + &usb2phy1_otg { 861 + phy-supply = <&vcc5v0_usb_host>; 862 + status = "okay"; 863 + }; 864 + 865 + &vop { 866 + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 867 + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 868 + status = "okay"; 869 + }; 870 + 871 + &vop_mmu { 872 + status = "okay"; 873 + }; 874 + 875 + &vp0 { 876 + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 877 + reg = <ROCKCHIP_VOP2_EP_HDMI0>; 878 + remote-endpoint = <&hdmi_in_vp0>; 879 + }; 880 + };
+623
arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + 3 + /dts-v1/; 4 + 5 + #include <dt-bindings/gpio/gpio.h> 6 + #include <dt-bindings/input/input.h> 7 + #include <dt-bindings/leds/common.h> 8 + #include <dt-bindings/pinctrl/rockchip.h> 9 + #include <dt-bindings/soc/rockchip,vop2.h> 10 + #include "rk3568.dtsi" 11 + 12 + / { 13 + model = "LinkEase EasePi R1"; 14 + compatible = "linkease,easepi-r1", "rockchip,rk3568"; 15 + 16 + aliases { 17 + ethernet0 = &gmac0; 18 + ethernet1 = &gmac1; 19 + mmc0 = &sdhci; 20 + }; 21 + 22 + chosen: chosen { 23 + stdout-path = "serial2:1500000n8"; 24 + }; 25 + 26 + adc-keys { 27 + compatible = "adc-keys"; 28 + io-channels = <&saradc 0>; 29 + io-channel-names = "buttons"; 30 + keyup-threshold-microvolt = <1800000>; 31 + 32 + button-recovery { 33 + label = "Recovery"; 34 + linux,code = <KEY_VENDOR>; 35 + press-threshold-microvolt = <1750>; 36 + }; 37 + }; 38 + 39 + gpio-leds { 40 + compatible = "gpio-leds"; 41 + pinctrl-names = "default"; 42 + pinctrl-0 = <&status_led_pin>; 43 + 44 + status_led: led-status { 45 + color = <LED_COLOR_ID_GREEN>; 46 + function = LED_FUNCTION_STATUS; 47 + gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; 48 + linux,default-trigger = "heartbeat"; 49 + }; 50 + }; 51 + 52 + hdmi-con { 53 + compatible = "hdmi-connector"; 54 + type = "a"; 55 + 56 + port { 57 + hdmi_con_in: endpoint { 58 + remote-endpoint = <&hdmi_out_con>; 59 + }; 60 + }; 61 + }; 62 + 63 + dc_12v: regulator-dc-12v { 64 + compatible = "regulator-fixed"; 65 + regulator-name = "dc_12v"; 66 + regulator-always-on; 67 + regulator-boot-on; 68 + regulator-min-microvolt = <12000000>; 69 + regulator-max-microvolt = <12000000>; 70 + }; 71 + 72 + vcc5v0_sys: regulator-vcc5v0-sys { 73 + compatible = "regulator-fixed"; 74 + regulator-name = "vcc5v0_sys"; 75 + regulator-always-on; 76 + regulator-boot-on; 77 + regulator-min-microvolt = <5000000>; 78 + regulator-max-microvolt = <5000000>; 79 + vin-supply = <&dc_12v>; 80 + }; 81 + 82 + vcc3v3_sys: regulator-vcc3v3-sys { 83 + compatible = "regulator-fixed"; 84 + regulator-name = "vcc3v3_sys"; 85 + regulator-always-on; 86 + regulator-boot-on; 87 + regulator-min-microvolt = <3300000>; 88 + regulator-max-microvolt = <3300000>; 89 + vin-supply = <&dc_12v>; 90 + }; 91 + 92 + pcie30_avdd0v9: regulator-pcie30-avdd0v9 { 93 + compatible = "regulator-fixed"; 94 + regulator-name = "pcie30_avdd0v9"; 95 + regulator-always-on; 96 + regulator-boot-on; 97 + regulator-min-microvolt = <900000>; 98 + regulator-max-microvolt = <900000>; 99 + vin-supply = <&vcc3v3_sys>; 100 + }; 101 + 102 + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { 103 + compatible = "regulator-fixed"; 104 + regulator-name = "pcie30_avdd1v8"; 105 + regulator-always-on; 106 + regulator-boot-on; 107 + regulator-min-microvolt = <1800000>; 108 + regulator-max-microvolt = <1800000>; 109 + vin-supply = <&vcc3v3_sys>; 110 + }; 111 + 112 + regulator-vdd0v95-25glan { 113 + compatible = "regulator-fixed"; 114 + enable-active-high; 115 + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 116 + pinctrl-names = "default"; 117 + pinctrl-0 = <&vdd0v95_25glan_en>; 118 + regulator-name = "vdd0v95_25glan"; 119 + regulator-always-on; 120 + regulator-boot-on; 121 + regulator-min-microvolt = <950000>; 122 + regulator-max-microvolt = <950000>; 123 + vin-supply = <&vcc3v3_sys>; 124 + }; 125 + 126 + vcc3v3_nvme: regulator-vcc3v3-nvme { 127 + compatible = "regulator-fixed"; 128 + enable-active-high; 129 + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 130 + pinctrl-names = "default"; 131 + pinctrl-0 = <&vcc3v3_nvme_en>; 132 + regulator-name = "vcc3v3_nvme"; 133 + regulator-min-microvolt = <3300000>; 134 + regulator-max-microvolt = <3300000>; 135 + vin-supply = <&dc_12v>; 136 + }; 137 + 138 + }; 139 + 140 + &combphy1 { 141 + status = "okay"; 142 + }; 143 + 144 + &combphy2 { 145 + status = "okay"; 146 + }; 147 + 148 + &cpu0 { 149 + cpu-supply = <&vdd_cpu>; 150 + }; 151 + 152 + &cpu1 { 153 + cpu-supply = <&vdd_cpu>; 154 + }; 155 + 156 + &cpu2 { 157 + cpu-supply = <&vdd_cpu>; 158 + }; 159 + 160 + &cpu3 { 161 + cpu-supply = <&vdd_cpu>; 162 + }; 163 + 164 + &gmac0 { 165 + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 166 + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 167 + assigned-clock-rates = <0>, <125000000>; 168 + phy-handle = <&rgmii_phy0>; 169 + phy-mode = "rgmii-id"; 170 + pinctrl-names = "default"; 171 + pinctrl-0 = <&gmac0_miim 172 + &gmac0_tx_bus2 173 + &gmac0_rx_bus2 174 + &gmac0_rgmii_clk 175 + &gmac0_rgmii_bus>; 176 + status = "okay"; 177 + }; 178 + 179 + &gmac1 { 180 + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 181 + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 182 + assigned-clock-rates = <0>, <125000000>; 183 + phy-handle = <&rgmii_phy1>; 184 + phy-mode = "rgmii-id"; 185 + pinctrl-names = "default"; 186 + pinctrl-0 = <&gmac1m1_miim 187 + &gmac1m1_tx_bus2 188 + &gmac1m1_rx_bus2 189 + &gmac1m1_rgmii_clk 190 + &gmac1m1_rgmii_bus>; 191 + status = "okay"; 192 + }; 193 + 194 + &gpu { 195 + mali-supply = <&vdd_gpu>; 196 + status = "okay"; 197 + }; 198 + 199 + &hdmi { 200 + avdd-0v9-supply = <&vdda0v9_image>; 201 + avdd-1v8-supply = <&vcca1v8_image>; 202 + status = "okay"; 203 + }; 204 + 205 + &hdmi_in { 206 + hdmi_in_vp0: endpoint { 207 + remote-endpoint = <&vp0_out_hdmi>; 208 + }; 209 + }; 210 + 211 + &hdmi_out { 212 + hdmi_out_con: endpoint { 213 + remote-endpoint = <&hdmi_con_in>; 214 + }; 215 + }; 216 + 217 + &hdmi_sound { 218 + status = "okay"; 219 + }; 220 + 221 + &i2c0 { 222 + status = "okay"; 223 + 224 + vdd_cpu: regulator@1c { 225 + compatible = "tcs,tcs4525"; 226 + reg = <0x1c>; 227 + fcs,suspend-voltage-selector = <1>; 228 + regulator-name = "vdd_cpu"; 229 + regulator-always-on; 230 + regulator-boot-on; 231 + regulator-min-microvolt = <800000>; 232 + regulator-max-microvolt = <1150000>; 233 + regulator-ramp-delay = <2300>; 234 + vin-supply = <&vcc5v0_sys>; 235 + 236 + regulator-state-mem { 237 + regulator-off-in-suspend; 238 + }; 239 + }; 240 + 241 + rk809: pmic@20 { 242 + compatible = "rockchip,rk809"; 243 + reg = <0x20>; 244 + interrupt-parent = <&gpio0>; 245 + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 246 + #clock-cells = <1>; 247 + pinctrl-names = "default"; 248 + pinctrl-0 = <&pmic_int>; 249 + system-power-controller; 250 + vcc1-supply = <&vcc3v3_sys>; 251 + vcc2-supply = <&vcc3v3_sys>; 252 + vcc3-supply = <&vcc3v3_sys>; 253 + vcc4-supply = <&vcc3v3_sys>; 254 + vcc5-supply = <&vcc3v3_sys>; 255 + vcc6-supply = <&vcc3v3_sys>; 256 + vcc7-supply = <&vcc3v3_sys>; 257 + vcc8-supply = <&vcc3v3_sys>; 258 + vcc9-supply = <&vcc3v3_sys>; 259 + wakeup-source; 260 + 261 + regulators { 262 + vdd_logic: DCDC_REG1 { 263 + regulator-name = "vdd_logic"; 264 + regulator-always-on; 265 + regulator-boot-on; 266 + regulator-initial-mode = <0x2>; 267 + regulator-min-microvolt = <500000>; 268 + regulator-max-microvolt = <1350000>; 269 + regulator-ramp-delay = <6001>; 270 + 271 + regulator-state-mem { 272 + regulator-off-in-suspend; 273 + }; 274 + }; 275 + 276 + vdd_gpu: DCDC_REG2 { 277 + regulator-name = "vdd_gpu"; 278 + regulator-always-on; 279 + regulator-initial-mode = <0x2>; 280 + regulator-min-microvolt = <500000>; 281 + regulator-max-microvolt = <1350000>; 282 + regulator-ramp-delay = <6001>; 283 + 284 + regulator-state-mem { 285 + regulator-off-in-suspend; 286 + }; 287 + }; 288 + 289 + vcc_ddr: DCDC_REG3 { 290 + regulator-name = "vcc_ddr"; 291 + regulator-always-on; 292 + regulator-boot-on; 293 + regulator-initial-mode = <0x2>; 294 + 295 + regulator-state-mem { 296 + regulator-on-in-suspend; 297 + }; 298 + }; 299 + 300 + vdd_npu: DCDC_REG4 { 301 + regulator-name = "vdd_npu"; 302 + regulator-initial-mode = <0x2>; 303 + regulator-min-microvolt = <500000>; 304 + regulator-max-microvolt = <1350000>; 305 + regulator-ramp-delay = <6001>; 306 + 307 + regulator-state-mem { 308 + regulator-off-in-suspend; 309 + }; 310 + }; 311 + 312 + vcc_1v8: DCDC_REG5 { 313 + regulator-name = "vcc_1v8"; 314 + regulator-always-on; 315 + regulator-boot-on; 316 + regulator-min-microvolt = <1800000>; 317 + regulator-max-microvolt = <1800000>; 318 + 319 + regulator-state-mem { 320 + regulator-off-in-suspend; 321 + }; 322 + }; 323 + 324 + vdda0v9_image: LDO_REG1 { 325 + regulator-name = "vdda0v9_image"; 326 + regulator-min-microvolt = <950000>; 327 + regulator-max-microvolt = <950000>; 328 + 329 + regulator-state-mem { 330 + regulator-off-in-suspend; 331 + }; 332 + }; 333 + 334 + vdda_0v9: LDO_REG2 { 335 + regulator-name = "vdda_0v9"; 336 + regulator-always-on; 337 + regulator-boot-on; 338 + regulator-min-microvolt = <900000>; 339 + regulator-max-microvolt = <900000>; 340 + 341 + regulator-state-mem { 342 + regulator-off-in-suspend; 343 + }; 344 + }; 345 + 346 + vdda0v9_pmu: LDO_REG3 { 347 + regulator-name = "vdda0v9_pmu"; 348 + regulator-always-on; 349 + regulator-boot-on; 350 + regulator-min-microvolt = <900000>; 351 + regulator-max-microvolt = <900000>; 352 + 353 + regulator-state-mem { 354 + regulator-on-in-suspend; 355 + regulator-suspend-microvolt = <900000>; 356 + }; 357 + }; 358 + 359 + vccio_acodec: LDO_REG4 { 360 + regulator-name = "vccio_acodec"; 361 + regulator-min-microvolt = <3300000>; 362 + regulator-max-microvolt = <3300000>; 363 + 364 + regulator-state-mem { 365 + regulator-off-in-suspend; 366 + }; 367 + }; 368 + 369 + vccio_sd: LDO_REG5 { 370 + regulator-name = "vccio_sd"; 371 + regulator-min-microvolt = <1800000>; 372 + regulator-max-microvolt = <3300000>; 373 + 374 + regulator-state-mem { 375 + regulator-off-in-suspend; 376 + }; 377 + }; 378 + 379 + vcc3v3_pmu: LDO_REG6 { 380 + regulator-name = "vcc3v3_pmu"; 381 + regulator-always-on; 382 + regulator-boot-on; 383 + regulator-min-microvolt = <3300000>; 384 + regulator-max-microvolt = <3300000>; 385 + 386 + regulator-state-mem { 387 + regulator-on-in-suspend; 388 + regulator-suspend-microvolt = <3300000>; 389 + }; 390 + }; 391 + 392 + vcca_1v8: LDO_REG7 { 393 + regulator-name = "vcca_1v8"; 394 + regulator-always-on; 395 + regulator-boot-on; 396 + regulator-min-microvolt = <1800000>; 397 + regulator-max-microvolt = <1800000>; 398 + 399 + regulator-state-mem { 400 + regulator-off-in-suspend; 401 + }; 402 + }; 403 + 404 + vcca1v8_pmu: LDO_REG8 { 405 + regulator-name = "vcca1v8_pmu"; 406 + regulator-always-on; 407 + regulator-boot-on; 408 + regulator-min-microvolt = <1800000>; 409 + regulator-max-microvolt = <1800000>; 410 + 411 + regulator-state-mem { 412 + regulator-on-in-suspend; 413 + regulator-suspend-microvolt = <1800000>; 414 + }; 415 + }; 416 + 417 + vcca1v8_image: LDO_REG9 { 418 + regulator-name = "vcca1v8_image"; 419 + regulator-min-microvolt = <1800000>; 420 + regulator-max-microvolt = <1800000>; 421 + 422 + regulator-state-mem { 423 + regulator-off-in-suspend; 424 + }; 425 + }; 426 + 427 + vcc_3v3: SWITCH_REG1 { 428 + regulator-name = "vcc_3v3"; 429 + regulator-always-on; 430 + regulator-boot-on; 431 + 432 + regulator-state-mem { 433 + regulator-off-in-suspend; 434 + }; 435 + }; 436 + 437 + vcc3v3_sd: SWITCH_REG2 { 438 + regulator-name = "vcc3v3_sd"; 439 + regulator-always-on; 440 + regulator-boot-on; 441 + 442 + regulator-state-mem { 443 + regulator-off-in-suspend; 444 + }; 445 + }; 446 + }; 447 + }; 448 + }; 449 + 450 + &i2s0_8ch { 451 + status = "okay"; 452 + }; 453 + 454 + &mdio0 { 455 + rgmii_phy0: ethernet-phy@1 { 456 + compatible = "ethernet-phy-ieee802.3-c22"; 457 + reg = <0x1>; 458 + pinctrl-0 = <&eth_phy0_reset_pin>; 459 + pinctrl-names = "default"; 460 + reset-assert-us = <20000>; 461 + reset-deassert-us = <100000>; 462 + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 463 + }; 464 + }; 465 + 466 + &mdio1 { 467 + rgmii_phy1: ethernet-phy@1 { 468 + compatible = "ethernet-phy-ieee802.3-c22"; 469 + reg = <0x1>; 470 + pinctrl-0 = <&eth_phy1_reset_pin>; 471 + pinctrl-names = "default"; 472 + reset-assert-us = <20000>; 473 + reset-deassert-us = <100000>; 474 + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 475 + }; 476 + }; 477 + 478 + /* ETH3 */ 479 + &pcie2x1 { 480 + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; 481 + vpcie3v3-supply = <&vcc3v3_sys>; 482 + status = "okay"; 483 + }; 484 + 485 + &pcie30phy { 486 + data-lanes = <1 2>; 487 + status = "okay"; 488 + }; 489 + 490 + /* ETH2 */ 491 + &pcie3x1 { 492 + num-lanes = <1>; 493 + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; 494 + vpcie3v3-supply = <&vcc3v3_sys>; 495 + status = "okay"; 496 + }; 497 + 498 + /* M.2 Key for 2280 NVMe */ 499 + &pcie3x2 { 500 + num-lanes = <1>; 501 + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 502 + vpcie3v3-supply = <&vcc3v3_nvme>; 503 + status = "okay"; 504 + }; 505 + 506 + &pinctrl { 507 + gmac0 { 508 + eth_phy0_reset_pin: eth-phy0-reset-pin { 509 + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 510 + }; 511 + }; 512 + 513 + gmac1 { 514 + eth_phy1_reset_pin: eth-phy1-reset-pin { 515 + rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; 516 + }; 517 + }; 518 + 519 + gpio-leds { 520 + status_led_pin: status-led-pin { 521 + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; 522 + }; 523 + }; 524 + 525 + nvme { 526 + vcc3v3_nvme_en: vcc3v3-nvme-en { 527 + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 528 + }; 529 + }; 530 + 531 + pcie-nic { 532 + vdd0v95_25glan_en: vdd0v95-25glan-en { 533 + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 534 + }; 535 + }; 536 + 537 + pmic { 538 + pmic_int: pmic-int { 539 + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 540 + }; 541 + }; 542 + 543 + }; 544 + 545 + &pmu_io_domains { 546 + pmuio1-supply = <&vcc3v3_pmu>; 547 + pmuio2-supply = <&vcc3v3_pmu>; 548 + vccio1-supply = <&vccio_acodec>; 549 + vccio3-supply = <&vccio_sd>; 550 + vccio4-supply = <&vcc_1v8>; 551 + vccio5-supply = <&vcc_3v3>; 552 + vccio6-supply = <&vcc_1v8>; 553 + vccio7-supply = <&vcc_3v3>; 554 + status = "okay"; 555 + }; 556 + 557 + &saradc { 558 + vref-supply = <&vcca_1v8>; 559 + status = "okay"; 560 + }; 561 + 562 + &sdhci { 563 + bus-width = <8>; 564 + max-frequency = <200000000>; 565 + non-removable; 566 + pinctrl-names = "default"; 567 + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; 568 + status = "okay"; 569 + }; 570 + 571 + &tsadc { 572 + rockchip,hw-tshut-mode = <1>; 573 + rockchip,hw-tshut-polarity = <0>; 574 + status = "okay"; 575 + }; 576 + 577 + &uart2 { 578 + status = "okay"; 579 + }; 580 + 581 + /* OTG Only USB2.0, Only device mode */ 582 + &usb_host0_xhci { 583 + dr_mode = "peripheral"; 584 + extcon = <&usb2phy0>; 585 + maximum-speed = "high-speed"; 586 + phys = <&usb2phy0_otg>; 587 + phy-names = "usb2-phy"; 588 + status = "okay"; 589 + }; 590 + 591 + &usb_host1_xhci { 592 + status = "okay"; 593 + }; 594 + 595 + &usb2phy0 { 596 + status = "okay"; 597 + }; 598 + 599 + &usb2phy0_host { 600 + phy-supply = <&vcc5v0_sys>; 601 + status = "okay"; 602 + }; 603 + 604 + &usb2phy0_otg { 605 + status = "okay"; 606 + }; 607 + 608 + &vop { 609 + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 610 + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 611 + status = "okay"; 612 + }; 613 + 614 + &vop_mmu { 615 + status = "okay"; 616 + }; 617 + 618 + &vp0 { 619 + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 620 + reg = <ROCKCHIP_VOP2_EP_HDMI0>; 621 + remote-endpoint = <&hdmi_in_vp0>; 622 + }; 623 + };
+49 -2
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
··· 53 53 device_type = "cpu"; 54 54 compatible = "arm,cortex-a55"; 55 55 reg = <0x0 0x0>; 56 - clocks = <&scmi_clk 0>; 56 + clocks = <&scmi_clk SCMI_CLK_CPU>; 57 57 #cooling-cells = <2>; 58 58 enable-method = "psci"; 59 59 i-cache-size = <0x8000>; ··· 69 69 device_type = "cpu"; 70 70 compatible = "arm,cortex-a55"; 71 71 reg = <0x0 0x100>; 72 + clocks = <&scmi_clk SCMI_CLK_CPU>; 72 73 #cooling-cells = <2>; 73 74 enable-method = "psci"; 74 75 i-cache-size = <0x8000>; ··· 85 84 device_type = "cpu"; 86 85 compatible = "arm,cortex-a55"; 87 86 reg = <0x0 0x200>; 87 + clocks = <&scmi_clk SCMI_CLK_CPU>; 88 88 #cooling-cells = <2>; 89 89 enable-method = "psci"; 90 90 i-cache-size = <0x8000>; ··· 101 99 device_type = "cpu"; 102 100 compatible = "arm,cortex-a55"; 103 101 reg = <0x0 0x300>; 102 + clocks = <&scmi_clk SCMI_CLK_CPU>; 104 103 #cooling-cells = <2>; 105 104 enable-method = "psci"; 106 105 i-cache-size = <0x8000>; ··· 560 557 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 561 558 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 562 559 interrupt-names = "job", "mmu", "gpu"; 563 - clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 560 + clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU>; 564 561 clock-names = "gpu", "bus"; 565 562 #cooling-cells = <2>; 566 563 power-domains = <&power RK3568_PD_GPU>; ··· 617 614 clock-names = "aclk", "iface"; 618 615 power-domains = <&power RK3568_PD_RGA>; 619 616 #iommu-cells = <0>; 617 + }; 618 + 619 + vicap: video-capture@fdfe0000 { 620 + compatible = "rockchip,rk3568-vicap"; 621 + reg = <0x0 0xfdfe0000 0x0 0x200>; 622 + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 623 + assigned-clocks = <&cru DCLK_VICAP>; 624 + assigned-clock-rates = <300000000>; 625 + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 626 + <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; 627 + clock-names = "aclk", "hclk", "dclk", "iclk"; 628 + iommus = <&vicap_mmu>; 629 + power-domains = <&power RK3568_PD_VI>; 630 + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, 631 + <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, 632 + <&cru SRST_I_VICAP>; 633 + reset-names = "arst", "hrst", "drst", "prst", "irst"; 634 + rockchip,grf = <&grf>; 635 + status = "disabled"; 636 + 637 + ports { 638 + #address-cells = <1>; 639 + #size-cells = <0>; 640 + 641 + vicap_dvp: port@0 { 642 + reg = <0>; 643 + }; 644 + 645 + vicap_mipi: port@1 { 646 + reg = <1>; 647 + }; 648 + }; 649 + }; 650 + 651 + vicap_mmu: iommu@fdfe0800 { 652 + compatible = "rockchip,rk3568-iommu"; 653 + reg = <0x0 0xfdfe0800 0x0 0x100>; 654 + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 655 + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 656 + clock-names = "aclk", "iface"; 657 + #iommu-cells = <0>; 658 + power-domains = <&power RK3568_PD_VI>; 659 + rockchip,disable-mmu-reset; 660 + status = "disabled"; 620 661 }; 621 662 622 663 sdmmc2: mmc@fe000000 {
+749
arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. 4 + * 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/leds/common.h> 11 + #include <dt-bindings/pinctrl/rockchip.h> 12 + #include <dt-bindings/soc/rockchip,vop2.h> 13 + #include "rk3576.dtsi" 14 + 15 + / { 16 + model = "100ASK DshanPi A1 board"; 17 + compatible = "100ask,dshanpi-a1", "rockchip,rk3576"; 18 + 19 + aliases { 20 + ethernet0 = &gmac0; 21 + ethernet1 = &gmac1; 22 + }; 23 + 24 + chosen { 25 + stdout-path = "serial0:1500000n8"; 26 + }; 27 + 28 + es8388_sound: es8388-sound { 29 + compatible = "simple-audio-card"; 30 + simple-audio-card,format = "i2s"; 31 + simple-audio-card,mclk-fs = <256>; 32 + simple-audio-card,name = "On-board Analog ES8388"; 33 + simple-audio-card,widgets = "Microphone", "Headphone Mic", 34 + "Microphone", "Mic Pads", 35 + "Headphone", "Headphone", 36 + "Line Out", "Line Out"; 37 + simple-audio-card,routing = "Headphone", "LOUT1", 38 + "Headphone", "ROUT1", 39 + "Line Out", "LOUT2", 40 + "Line Out", "ROUT2", 41 + "RINPUT1", "Headphone Mic", 42 + "LINPUT2", "Mic Pads", 43 + "RINPUT2", "Mic Pads"; 44 + simple-audio-card,pin-switches = "Headphone", "Line Out"; 45 + 46 + simple-audio-card,cpu { 47 + sound-dai = <&sai2>; 48 + }; 49 + 50 + simple-audio-card,codec { 51 + sound-dai = <&es8388>; 52 + system-clock-frequency = <12288000>; 53 + }; 54 + }; 55 + 56 + hdmi-con { 57 + compatible = "hdmi-connector"; 58 + type = "a"; 59 + 60 + port { 61 + hdmi_con_in: endpoint { 62 + remote-endpoint = <&hdmi_out_con>; 63 + }; 64 + }; 65 + }; 66 + 67 + vcc_in: regulator-vcc-12v0-dcin { 68 + compatible = "regulator-fixed"; 69 + regulator-name = "vcc_in"; 70 + regulator-always-on; 71 + regulator-boot-on; 72 + regulator-min-microvolt = <12000000>; 73 + regulator-max-microvolt = <12000000>; 74 + }; 75 + 76 + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { 77 + compatible = "regulator-fixed"; 78 + regulator-name = "vcc_1v1_nldo_s3"; 79 + regulator-always-on; 80 + regulator-boot-on; 81 + regulator-min-microvolt = <1100000>; 82 + regulator-max-microvolt = <1100000>; 83 + vin-supply = <&vcc_5v0_sys>; 84 + }; 85 + 86 + vcc_1v8_s0: regulator-vcc-1v8-s0 { 87 + compatible = "regulator-fixed"; 88 + regulator-name = "vcc_1v8_s0"; 89 + regulator-always-on; 90 + regulator-boot-on; 91 + regulator-min-microvolt = <1800000>; 92 + regulator-max-microvolt = <1800000>; 93 + vin-supply = <&vcc_1v8_s3>; 94 + }; 95 + 96 + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { 97 + compatible = "regulator-fixed"; 98 + regulator-name = "vcc_2v0_pldo_s3"; 99 + regulator-always-on; 100 + regulator-boot-on; 101 + regulator-min-microvolt = <2000000>; 102 + regulator-max-microvolt = <2000000>; 103 + vin-supply = <&vcc_5v0_sys>; 104 + }; 105 + 106 + vcc_3v3_m2: regulator-vcc-3v3-m2 { 107 + compatible = "regulator-fixed"; 108 + regulator-name = "vcc_3v3_m2"; 109 + regulator-always-on; 110 + regulator-boot-on; 111 + regulator-min-microvolt = <3300000>; 112 + regulator-max-microvolt = <3300000>; 113 + vin-supply = <&vcc_5v0_sys>; 114 + }; 115 + 116 + vcc_3v3_s0: regulator-vcc-3v3-s0 { 117 + compatible = "regulator-fixed"; 118 + regulator-name = "vcc_3v3_s0"; 119 + regulator-always-on; 120 + regulator-boot-on; 121 + regulator-min-microvolt = <3300000>; 122 + regulator-max-microvolt = <3300000>; 123 + vin-supply = <&vcc_3v3_s3>; 124 + }; 125 + 126 + vcc_5v0_sys: regulator-vcc-5v0-sys { 127 + compatible = "regulator-fixed"; 128 + regulator-name = "vcc_5v0_sys"; 129 + regulator-always-on; 130 + regulator-boot-on; 131 + regulator-min-microvolt = <5000000>; 132 + regulator-max-microvolt = <5000000>; 133 + vin-supply = <&vcc_in>; 134 + }; 135 + 136 + vbus5v0_typec: regulator-vbus5v0-typec { 137 + compatible = "regulator-fixed"; 138 + enable-active-high; 139 + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; 140 + pinctrl-names = "default"; 141 + pinctrl-0 = <&typec5v_pwren_h>; 142 + regulator-name = "vbus5v0_typec"; 143 + regulator-min-microvolt = <5000000>; 144 + regulator-max-microvolt = <5000000>; 145 + vin-supply = <&vcc_5v0_sys>; 146 + }; 147 + }; 148 + 149 + &combphy0_ps { 150 + status = "okay"; 151 + }; 152 + 153 + &combphy1_psu { 154 + status = "okay"; 155 + }; 156 + 157 + &cpu_b0 { 158 + cpu-supply = <&vdd_cpu_big_s0>; 159 + }; 160 + 161 + &cpu_b1 { 162 + cpu-supply = <&vdd_cpu_big_s0>; 163 + }; 164 + 165 + &cpu_b2 { 166 + cpu-supply = <&vdd_cpu_big_s0>; 167 + }; 168 + 169 + &cpu_b3 { 170 + cpu-supply = <&vdd_cpu_big_s0>; 171 + }; 172 + 173 + &cpu_l0 { 174 + cpu-supply = <&vdd_cpu_lit_s0>; 175 + }; 176 + 177 + &cpu_l1 { 178 + cpu-supply = <&vdd_cpu_lit_s0>; 179 + }; 180 + 181 + &cpu_l2 { 182 + cpu-supply = <&vdd_cpu_lit_s0>; 183 + }; 184 + 185 + &cpu_l3 { 186 + cpu-supply = <&vdd_cpu_lit_s0>; 187 + }; 188 + 189 + &gmac0 { 190 + clock_in_out = "output"; 191 + phy-mode = "rgmii-id"; 192 + phy-handle = <&rgmii_phy0>; 193 + phy-supply = <&vcc_3v3_s0>; 194 + pinctrl-names = "default"; 195 + pinctrl-0 = <&eth0m0_miim 196 + &eth0m0_tx_bus2 197 + &eth0m0_rx_bus2 198 + &eth0m0_rgmii_clk 199 + &eth0m0_rgmii_bus>; 200 + status = "okay"; 201 + }; 202 + 203 + &gmac1 { 204 + clock_in_out = "output"; 205 + phy-mode = "rgmii-id"; 206 + phy-handle = <&rgmii_phy1>; 207 + phy-supply = <&vcc_3v3_s0>; 208 + pinctrl-names = "default"; 209 + pinctrl-0 = <&eth1m0_miim 210 + &eth1m0_tx_bus2 211 + &eth1m0_rx_bus2 212 + &eth1m0_rgmii_clk 213 + &eth1m0_rgmii_bus>; 214 + status = "okay"; 215 + }; 216 + 217 + &gpu { 218 + mali-supply = <&vdd_gpu_s0>; 219 + status = "okay"; 220 + }; 221 + 222 + &hdmi { 223 + status = "okay"; 224 + }; 225 + 226 + &hdmi_in { 227 + hdmi_in_vp0: endpoint { 228 + remote-endpoint = <&vp0_out_hdmi>; 229 + }; 230 + }; 231 + 232 + &hdmi_out { 233 + hdmi_out_con: endpoint { 234 + remote-endpoint = <&hdmi_con_in>; 235 + }; 236 + }; 237 + 238 + &hdmi_sound { 239 + status = "okay"; 240 + }; 241 + 242 + &hdptxphy { 243 + status = "okay"; 244 + }; 245 + 246 + &i2c1 { 247 + status = "okay"; 248 + 249 + pmic@23 { 250 + compatible = "rockchip,rk806"; 251 + reg = <0x23>; 252 + gpio-controller; 253 + #gpio-cells = <2>; 254 + interrupt-parent = <&gpio0>; 255 + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; 256 + pinctrl-names = "default"; 257 + pinctrl-0 = <&pmic_pins 258 + &rk806_dvs1_null 259 + &rk806_dvs2_null 260 + &rk806_dvs3_null>; 261 + system-power-controller; 262 + vcc1-supply = <&vcc_5v0_sys>; 263 + vcc2-supply = <&vcc_5v0_sys>; 264 + vcc3-supply = <&vcc_5v0_sys>; 265 + vcc4-supply = <&vcc_5v0_sys>; 266 + vcc5-supply = <&vcc_5v0_sys>; 267 + vcc6-supply = <&vcc_5v0_sys>; 268 + vcc7-supply = <&vcc_5v0_sys>; 269 + vcc8-supply = <&vcc_5v0_sys>; 270 + vcc9-supply = <&vcc_5v0_sys>; 271 + vcc10-supply = <&vcc_5v0_sys>; 272 + vcc11-supply = <&vcc_2v0_pldo_s3>; 273 + vcc12-supply = <&vcc_5v0_sys>; 274 + vcc13-supply = <&vcc_1v1_nldo_s3>; 275 + vcc14-supply = <&vcc_1v1_nldo_s3>; 276 + vcca-supply = <&vcc_5v0_sys>; 277 + 278 + rk806_dvs1_null: dvs1-null-pins { 279 + pins = "gpio_pwrctrl1"; 280 + function = "pin_fun0"; 281 + }; 282 + 283 + rk806_dvs2_null: dvs2-null-pins { 284 + pins = "gpio_pwrctrl2"; 285 + function = "pin_fun0"; 286 + }; 287 + 288 + rk806_dvs3_null: dvs3-null-pins { 289 + pins = "gpio_pwrctrl3"; 290 + function = "pin_fun0"; 291 + }; 292 + 293 + rk806_dvs1_slp: dvs1-slp-pins { 294 + pins = "gpio_pwrctrl1"; 295 + function = "pin_fun1"; 296 + }; 297 + 298 + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { 299 + pins = "gpio_pwrctrl1"; 300 + function = "pin_fun2"; 301 + }; 302 + 303 + rk806_dvs1_rst: dvs1-rst-pins { 304 + pins = "gpio_pwrctrl1"; 305 + function = "pin_fun3"; 306 + }; 307 + 308 + rk806_dvs2_slp: dvs2-slp-pins { 309 + pins = "gpio_pwrctrl2"; 310 + function = "pin_fun1"; 311 + }; 312 + 313 + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { 314 + pins = "gpio_pwrctrl2"; 315 + function = "pin_fun2"; 316 + }; 317 + 318 + rk806_dvs2_rst: dvs2-rst-pins { 319 + pins = "gpio_pwrctrl2"; 320 + function = "pin_fun3"; 321 + }; 322 + 323 + rk806_dvs2_dvs: dvs2-dvs-pins { 324 + pins = "gpio_pwrctrl2"; 325 + function = "pin_fun4"; 326 + }; 327 + 328 + rk806_dvs2_gpio: dvs2-gpio-pins { 329 + pins = "gpio_pwrctrl2"; 330 + function = "pin_fun5"; 331 + }; 332 + 333 + rk806_dvs3_slp: dvs3-slp-pins { 334 + pins = "gpio_pwrctrl3"; 335 + function = "pin_fun1"; 336 + }; 337 + 338 + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { 339 + pins = "gpio_pwrctrl3"; 340 + function = "pin_fun2"; 341 + }; 342 + 343 + rk806_dvs3_rst: dvs3-rst-pins { 344 + pins = "gpio_pwrctrl3"; 345 + function = "pin_fun3"; 346 + }; 347 + 348 + rk806_dvs3_dvs: dvs3-dvs-pins { 349 + pins = "gpio_pwrctrl3"; 350 + function = "pin_fun4"; 351 + }; 352 + 353 + rk806_dvs3_gpio: dvs3-gpio-pins { 354 + pins = "gpio_pwrctrl3"; 355 + function = "pin_fun5"; 356 + }; 357 + 358 + regulators { 359 + vdd_cpu_big_s0: dcdc-reg1 { 360 + regulator-always-on; 361 + regulator-boot-on; 362 + regulator-min-microvolt = <550000>; 363 + regulator-max-microvolt = <950000>; 364 + regulator-ramp-delay = <12500>; 365 + regulator-name = "vdd_cpu_big_s0"; 366 + regulator-enable-ramp-delay = <400>; 367 + regulator-state-mem { 368 + regulator-off-in-suspend; 369 + }; 370 + }; 371 + 372 + vdd_npu_s0: dcdc-reg2 { 373 + regulator-boot-on; 374 + regulator-min-microvolt = <550000>; 375 + regulator-max-microvolt = <950000>; 376 + regulator-ramp-delay = <12500>; 377 + regulator-name = "vdd_npu_s0"; 378 + regulator-enable-ramp-delay = <400>; 379 + regulator-state-mem { 380 + regulator-off-in-suspend; 381 + }; 382 + }; 383 + 384 + vdd_cpu_lit_s0: dcdc-reg3 { 385 + regulator-always-on; 386 + regulator-boot-on; 387 + regulator-min-microvolt = <550000>; 388 + regulator-max-microvolt = <950000>; 389 + regulator-ramp-delay = <12500>; 390 + regulator-name = "vdd_cpu_lit_s0"; 391 + regulator-state-mem { 392 + regulator-off-in-suspend; 393 + regulator-suspend-microvolt = <750000>; 394 + }; 395 + }; 396 + 397 + vcc_3v3_s3: dcdc-reg4 { 398 + regulator-always-on; 399 + regulator-boot-on; 400 + regulator-min-microvolt = <3300000>; 401 + regulator-max-microvolt = <3300000>; 402 + regulator-name = "vcc_3v3_s3"; 403 + regulator-state-mem { 404 + regulator-on-in-suspend; 405 + regulator-suspend-microvolt = <3300000>; 406 + }; 407 + }; 408 + 409 + vdd_gpu_s0: dcdc-reg5 { 410 + regulator-boot-on; 411 + regulator-min-microvolt = <550000>; 412 + regulator-max-microvolt = <900000>; 413 + regulator-ramp-delay = <12500>; 414 + regulator-name = "vdd_gpu_s0"; 415 + regulator-enable-ramp-delay = <400>; 416 + regulator-state-mem { 417 + regulator-off-in-suspend; 418 + regulator-suspend-microvolt = <850000>; 419 + }; 420 + }; 421 + 422 + vddq_ddr_s0: dcdc-reg6 { 423 + regulator-always-on; 424 + regulator-boot-on; 425 + regulator-name = "vddq_ddr_s0"; 426 + regulator-state-mem { 427 + regulator-off-in-suspend; 428 + }; 429 + }; 430 + 431 + vdd_logic_s0: dcdc-reg7 { 432 + regulator-always-on; 433 + regulator-boot-on; 434 + regulator-min-microvolt = <550000>; 435 + regulator-max-microvolt = <800000>; 436 + regulator-name = "vdd_logic_s0"; 437 + regulator-state-mem { 438 + regulator-off-in-suspend; 439 + }; 440 + }; 441 + 442 + vcc_1v8_s3: dcdc-reg8 { 443 + regulator-always-on; 444 + regulator-boot-on; 445 + regulator-min-microvolt = <1800000>; 446 + regulator-max-microvolt = <1800000>; 447 + regulator-name = "vcc_1v8_s3"; 448 + regulator-state-mem { 449 + regulator-on-in-suspend; 450 + regulator-suspend-microvolt = <1800000>; 451 + }; 452 + }; 453 + 454 + vdd2_ddr_s3: dcdc-reg9 { 455 + regulator-always-on; 456 + regulator-boot-on; 457 + regulator-name = "vdd2_ddr_s3"; 458 + regulator-state-mem { 459 + regulator-on-in-suspend; 460 + }; 461 + }; 462 + 463 + vdd_ddr_s0: dcdc-reg10 { 464 + regulator-always-on; 465 + regulator-boot-on; 466 + regulator-min-microvolt = <550000>; 467 + regulator-max-microvolt = <1200000>; 468 + regulator-name = "vdd_ddr_s0"; 469 + regulator-state-mem { 470 + regulator-off-in-suspend; 471 + }; 472 + }; 473 + 474 + vcca_1v8_s0: pldo-reg1 { 475 + regulator-always-on; 476 + regulator-boot-on; 477 + regulator-min-microvolt = <1800000>; 478 + regulator-max-microvolt = <1800000>; 479 + regulator-name = "vcca_1v8_s0"; 480 + regulator-state-mem { 481 + regulator-off-in-suspend; 482 + }; 483 + }; 484 + 485 + vcca1v8_pldo2_s0: pldo-reg2 { 486 + regulator-always-on; 487 + regulator-boot-on; 488 + regulator-min-microvolt = <1800000>; 489 + regulator-max-microvolt = <1800000>; 490 + regulator-name = "vcca1v8_pldo2_s0"; 491 + regulator-state-mem { 492 + regulator-off-in-suspend; 493 + }; 494 + }; 495 + 496 + vdda_1v2_s0: pldo-reg3 { 497 + regulator-always-on; 498 + regulator-boot-on; 499 + regulator-min-microvolt = <1200000>; 500 + regulator-max-microvolt = <1200000>; 501 + regulator-name = "vdda_1v2_s0"; 502 + regulator-state-mem { 503 + regulator-off-in-suspend; 504 + }; 505 + }; 506 + 507 + vcca_3v3_s0: pldo-reg4 { 508 + regulator-always-on; 509 + regulator-boot-on; 510 + regulator-min-microvolt = <3300000>; 511 + regulator-max-microvolt = <3300000>; 512 + regulator-name = "vcca_3v3_s0"; 513 + regulator-state-mem { 514 + regulator-off-in-suspend; 515 + }; 516 + }; 517 + 518 + vccio_sd_s0: pldo-reg5 { 519 + regulator-always-on; 520 + regulator-boot-on; 521 + regulator-min-microvolt = <1800000>; 522 + regulator-max-microvolt = <3300000>; 523 + regulator-name = "vccio_sd_s0"; 524 + regulator-state-mem { 525 + regulator-off-in-suspend; 526 + }; 527 + }; 528 + 529 + vcca1v8_pldo6_s3: pldo-reg6 { 530 + regulator-always-on; 531 + regulator-boot-on; 532 + regulator-min-microvolt = <1800000>; 533 + regulator-max-microvolt = <1800000>; 534 + regulator-name = "vcca1v8_pldo6_s3"; 535 + regulator-state-mem { 536 + regulator-on-in-suspend; 537 + regulator-suspend-microvolt = <1800000>; 538 + }; 539 + }; 540 + 541 + vdd_0v75_s3: nldo-reg1 { 542 + regulator-always-on; 543 + regulator-boot-on; 544 + regulator-min-microvolt = <750000>; 545 + regulator-max-microvolt = <750000>; 546 + regulator-name = "vdd_0v75_s3"; 547 + regulator-state-mem { 548 + regulator-on-in-suspend; 549 + regulator-suspend-microvolt = <750000>; 550 + }; 551 + }; 552 + 553 + vdda_ddr_pll_s0: nldo-reg2 { 554 + regulator-always-on; 555 + regulator-boot-on; 556 + regulator-min-microvolt = <850000>; 557 + regulator-max-microvolt = <850000>; 558 + regulator-name = "vdda_ddr_pll_s0"; 559 + regulator-state-mem { 560 + regulator-off-in-suspend; 561 + }; 562 + }; 563 + 564 + vdda0v75_hdmi_s0: nldo-reg3 { 565 + regulator-always-on; 566 + regulator-boot-on; 567 + regulator-min-microvolt = <837500>; 568 + regulator-max-microvolt = <837500>; 569 + regulator-name = "vdda0v75_hdmi_s0"; 570 + regulator-state-mem { 571 + regulator-off-in-suspend; 572 + }; 573 + }; 574 + 575 + vdda_0v85_s0: nldo-reg4 { 576 + regulator-always-on; 577 + regulator-boot-on; 578 + regulator-min-microvolt = <850000>; 579 + regulator-max-microvolt = <850000>; 580 + regulator-name = "vdda_0v85_s0"; 581 + regulator-state-mem { 582 + regulator-off-in-suspend; 583 + }; 584 + }; 585 + 586 + vdda_0v75_s0: nldo-reg5 { 587 + regulator-always-on; 588 + regulator-boot-on; 589 + regulator-min-microvolt = <750000>; 590 + regulator-max-microvolt = <750000>; 591 + regulator-name = "vdda_0v75_s0"; 592 + regulator-state-mem { 593 + regulator-off-in-suspend; 594 + }; 595 + }; 596 + }; 597 + }; 598 + }; 599 + 600 + &i2c4 { 601 + status = "okay"; 602 + 603 + es8388: audio-codec@11 { 604 + compatible = "everest,es8388", "everest,es8328"; 605 + reg = <0x11>; 606 + clocks = <&cru CLK_SAI2_MCLKOUT_TO_IO>; 607 + assigned-clocks = <&cru CLK_SAI2_MCLKOUT_TO_IO>; 608 + assigned-clock-rates = <12288000>; 609 + AVDD-supply = <&vcc_3v3_s0>; 610 + DVDD-supply = <&vcc_3v3_s0>; 611 + HPVDD-supply = <&vcc_3v3_s0>; 612 + PVDD-supply = <&vcc_3v3_s0>; 613 + pinctrl-names = "default"; 614 + pinctrl-0 = <&sai2m0_mclk>; 615 + #sound-dai-cells = <0>; 616 + }; 617 + }; 618 + 619 + &mdio0 { 620 + rgmii_phy0: phy@0 { 621 + compatible = "ethernet-phy-ieee802.3-c22"; 622 + reg = <0>; 623 + pinctrl-names = "default"; 624 + pinctrl-0 = <&gmac0_rst>; 625 + reset-assert-us = <20000>; 626 + reset-deassert-us = <100000>; 627 + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; 628 + }; 629 + }; 630 + 631 + &mdio1 { 632 + rgmii_phy1: phy@0 { 633 + compatible = "ethernet-phy-ieee802.3-c22"; 634 + reg = <0>; 635 + pinctrl-names = "default"; 636 + pinctrl-0 = <&gmac1_rst>; 637 + reset-assert-us = <20000>; 638 + reset-deassert-us = <100000>; 639 + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; 640 + }; 641 + }; 642 + 643 + &pcie0 { 644 + pinctrl-names = "default"; 645 + pinctrl-0 = <&pcie_reset>; 646 + reset-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; 647 + vpcie3v3-supply = <&vcc_3v3_m2>; 648 + status = "okay"; 649 + }; 650 + 651 + &pinctrl { 652 + gmac { 653 + gmac0_rst: gmac0-rst { 654 + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; 655 + }; 656 + 657 + gmac1_rst: gmac1-rst { 658 + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 659 + }; 660 + }; 661 + 662 + headphone { 663 + hp_det: hp-det { 664 + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 665 + }; 666 + }; 667 + 668 + pcie { 669 + pcie_reset: pcie-reset { 670 + rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 671 + }; 672 + }; 673 + 674 + usb { 675 + typec5v_pwren_h: typec5v-pwren-h { 676 + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 677 + }; 678 + }; 679 + }; 680 + 681 + &sai2 { 682 + status = "okay"; 683 + }; 684 + 685 + &sai6 { 686 + status = "okay"; 687 + }; 688 + 689 + &sdhci { 690 + bus-width = <8>; 691 + full-pwr-cycle-in-suspend; 692 + max-frequency = <200000000>; 693 + mmc-hs400-1_8v; 694 + mmc-hs400-enhanced-strobe; 695 + no-sdio; 696 + no-sd; 697 + non-removable; 698 + status = "okay"; 699 + }; 700 + 701 + &sdmmc { 702 + bus-width = <4>; 703 + cap-mmc-highspeed; 704 + cap-sd-highspeed; 705 + disable-wp; 706 + max-frequency = <200000000>; 707 + sd-uhs-sdr104; 708 + vmmc-supply = <&vcc_3v3_s0>; 709 + vqmmc-supply = <&vccio_sd_s0>; 710 + status = "okay"; 711 + }; 712 + 713 + &u2phy0 { 714 + status = "okay"; 715 + }; 716 + 717 + &u2phy0_otg { 718 + phy-supply = <&vbus5v0_typec>; 719 + status = "okay"; 720 + }; 721 + 722 + &u2phy1 { 723 + status = "okay"; 724 + }; 725 + 726 + &u2phy1_otg { 727 + phy-supply = <&vcc_5v0_sys>; 728 + status = "okay"; 729 + }; 730 + 731 + &uart0 { 732 + pinctrl-0 = <&uart0m0_xfer>; 733 + status = "okay"; 734 + }; 735 + 736 + &vop { 737 + status = "okay"; 738 + }; 739 + 740 + &vop_mmu { 741 + status = "okay"; 742 + }; 743 + 744 + &vp0 { 745 + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 746 + reg = <ROCKCHIP_VOP2_EP_HDMI0>; 747 + remote-endpoint = <&hdmi_in_vp0>; 748 + }; 749 + };
+860
arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd. 4 + * (http://www.friendlyelec.com) 5 + * 6 + * Copyright (c) 2025 Tianling Shen <cnsztl@gmail.com> 7 + */ 8 + 9 + /dts-v1/; 10 + #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/input/input.h> 12 + #include <dt-bindings/leds/common.h> 13 + #include <dt-bindings/pinctrl/rockchip.h> 14 + #include <dt-bindings/soc/rockchip,vop2.h> 15 + 16 + #include "rk3576.dtsi" 17 + 18 + / { 19 + model = "FriendlyElec NanoPi R76S"; 20 + compatible = "friendlyarm,nanopi-r76s", "rockchip,rk3576"; 21 + 22 + aliases { 23 + mmc0 = &sdhci; 24 + mmc1 = &sdmmc; 25 + mmc2 = &sdio; 26 + }; 27 + 28 + chosen { 29 + stdout-path = "serial0:1500000n8"; 30 + }; 31 + 32 + gpio-keys { 33 + compatible = "gpio-keys"; 34 + pinctrl-names = "default"; 35 + pinctrl-0 = <&user_but_pin>; 36 + 37 + button-reset { 38 + label = "reset"; 39 + gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; 40 + debounce-interval = <50>; 41 + linux,code = <KEY_RESTART>; 42 + wakeup-source; 43 + }; 44 + }; 45 + 46 + gpio-leds { 47 + compatible = "gpio-leds"; 48 + pinctrl-names = "default"; 49 + pinctrl-0 = <&led1_h>, <&led_sys_h>, <&led2_h>; 50 + 51 + led-0 { 52 + color = <LED_COLOR_ID_GREEN>; 53 + function = LED_FUNCTION_LAN; 54 + gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; 55 + }; 56 + 57 + led-1 { 58 + color = <LED_COLOR_ID_RED>; 59 + function = LED_FUNCTION_POWER; 60 + gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; 61 + linux,default-trigger = "heartbeat"; 62 + }; 63 + 64 + led-2 { 65 + color = <LED_COLOR_ID_GREEN>; 66 + function = LED_FUNCTION_WAN; 67 + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; 68 + }; 69 + }; 70 + 71 + hdmi-con { 72 + compatible = "hdmi-connector"; 73 + hdmi-pwr-supply = <&vcc5v_hdmi_tx>; 74 + type = "a"; 75 + 76 + port { 77 + hdmi_con_in: endpoint { 78 + remote-endpoint = <&hdmi_out_con>; 79 + }; 80 + }; 81 + }; 82 + 83 + sdio_pwrseq: sdio-pwrseq { 84 + compatible = "mmc-pwrseq-simple"; 85 + clocks = <&hym8563>; 86 + clock-names = "ext_clock"; 87 + pinctrl-names = "default"; 88 + pinctrl-0 = <&wifi_reg_on_h>; 89 + post-power-on-delay-ms = <200>; 90 + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; 91 + }; 92 + 93 + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { 94 + compatible = "regulator-fixed"; 95 + regulator-always-on; 96 + regulator-boot-on; 97 + regulator-min-microvolt = <3300000>; 98 + regulator-max-microvolt = <3300000>; 99 + regulator-name = "vcc3v3_rtc_s5"; 100 + vin-supply = <&vcc5v0_sys_s5>; 101 + }; 102 + 103 + vcc5v_dcin: regulator-vcc5v-dcin { 104 + compatible = "regulator-fixed"; 105 + regulator-always-on; 106 + regulator-boot-on; 107 + regulator-min-microvolt = <5000000>; 108 + regulator-max-microvolt = <5000000>; 109 + regulator-name = "vcc5v_dcin"; 110 + }; 111 + 112 + vcc5v_hdmi_tx: regulator-vcc5v-hdmi-tx { 113 + compatible = "regulator-fixed"; 114 + enable-active-high; 115 + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; 116 + pinctrl-names = "default"; 117 + pinctrl-0 = <&hdmi_tx_on_h>; 118 + regulator-min-microvolt = <5000000>; 119 + regulator-max-microvolt = <5000000>; 120 + regulator-name = "vcc5v_hdmi_tx"; 121 + vin-supply = <&vcc5v0_sys_s5>; 122 + }; 123 + 124 + vcc5v0_device_s0: regulator-vcc5v0-device-s0 { 125 + compatible = "regulator-fixed"; 126 + regulator-always-on; 127 + regulator-boot-on; 128 + regulator-min-microvolt = <5000000>; 129 + regulator-max-microvolt = <5000000>; 130 + regulator-name = "vcc5v0_device_s0"; 131 + vin-supply = <&vcc5v_dcin>; 132 + }; 133 + 134 + vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 { 135 + compatible = "regulator-fixed"; 136 + regulator-always-on; 137 + regulator-boot-on; 138 + regulator-min-microvolt = <5000000>; 139 + regulator-max-microvolt = <5000000>; 140 + regulator-name = "vcc5v0_sys_s5"; 141 + vin-supply = <&vcc5v_dcin>; 142 + }; 143 + 144 + vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 { 145 + compatible = "regulator-fixed"; 146 + enable-active-high; 147 + gpios = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; 148 + pinctrl-names = "default"; 149 + pinctrl-0 = <&usb_otg0_pwren_h>; 150 + regulator-min-microvolt = <5000000>; 151 + regulator-max-microvolt = <5000000>; 152 + regulator-name = "vcc5v0_usb_otg0"; 153 + vin-supply = <&vcc5v0_sys_s5>; 154 + }; 155 + 156 + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { 157 + compatible = "regulator-fixed"; 158 + regulator-always-on; 159 + regulator-boot-on; 160 + regulator-min-microvolt = <1100000>; 161 + regulator-max-microvolt = <1100000>; 162 + regulator-name = "vcc_1v1_nldo_s3"; 163 + vin-supply = <&vcc5v0_sys_s5>; 164 + }; 165 + 166 + vcc_1v8_s0: regulator-vcc-1v8-s0 { 167 + compatible = "regulator-fixed"; 168 + regulator-always-on; 169 + regulator-boot-on; 170 + regulator-min-microvolt = <1800000>; 171 + regulator-max-microvolt = <1800000>; 172 + regulator-name = "vcc_1v8_s0"; 173 + vin-supply = <&vcc_1v8_s3>; 174 + }; 175 + 176 + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { 177 + compatible = "regulator-fixed"; 178 + regulator-always-on; 179 + regulator-boot-on; 180 + regulator-min-microvolt = <2000000>; 181 + regulator-max-microvolt = <2000000>; 182 + regulator-name = "vcc_2v0_pldo_s3"; 183 + vin-supply = <&vcc5v0_sys_s5>; 184 + }; 185 + 186 + vcc_3v3_s0: regulator-vcc-3v3-s0 { 187 + compatible = "regulator-fixed"; 188 + regulator-always-on; 189 + regulator-boot-on; 190 + regulator-min-microvolt = <3300000>; 191 + regulator-max-microvolt = <3300000>; 192 + regulator-name = "vcc_3v3_s0"; 193 + vin-supply = <&vcc_3v3_s3>; 194 + }; 195 + }; 196 + 197 + &combphy0_ps { 198 + status = "okay"; 199 + }; 200 + 201 + &combphy1_psu { 202 + status = "okay"; 203 + }; 204 + 205 + &cpu_b0 { 206 + cpu-supply = <&vdd_cpu_big_s0>; 207 + }; 208 + 209 + &cpu_b1 { 210 + cpu-supply = <&vdd_cpu_big_s0>; 211 + }; 212 + 213 + &cpu_b2 { 214 + cpu-supply = <&vdd_cpu_big_s0>; 215 + }; 216 + 217 + &cpu_b3 { 218 + cpu-supply = <&vdd_cpu_big_s0>; 219 + }; 220 + 221 + &cpu_l0 { 222 + cpu-supply = <&vdd_cpu_lit_s0>; 223 + }; 224 + 225 + &cpu_l1 { 226 + cpu-supply = <&vdd_cpu_lit_s0>; 227 + }; 228 + 229 + &cpu_l2 { 230 + cpu-supply = <&vdd_cpu_lit_s0>; 231 + }; 232 + 233 + &cpu_l3 { 234 + cpu-supply = <&vdd_cpu_lit_s0>; 235 + }; 236 + 237 + &gpu { 238 + mali-supply = <&vdd_gpu_s0>; 239 + status = "okay"; 240 + }; 241 + 242 + &hdmi { 243 + status = "okay"; 244 + }; 245 + 246 + &hdmi_in { 247 + hdmi_in_vp0: endpoint { 248 + remote-endpoint = <&vp0_out_hdmi>; 249 + }; 250 + }; 251 + 252 + &hdmi_out { 253 + hdmi_out_con: endpoint { 254 + remote-endpoint = <&hdmi_con_in>; 255 + }; 256 + }; 257 + 258 + &hdmi_sound { 259 + status = "okay"; 260 + }; 261 + 262 + &hdptxphy { 263 + status = "okay"; 264 + }; 265 + 266 + &i2c1 { 267 + status = "okay"; 268 + 269 + pmic@23 { 270 + compatible = "rockchip,rk806"; 271 + reg = <0x23>; 272 + #gpio-cells = <2>; 273 + gpio-controller; 274 + interrupt-parent = <&gpio0>; 275 + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; 276 + pinctrl-names = "default"; 277 + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 278 + <&rk806_dvs2_null>, <&rk806_dvs3_null>; 279 + system-power-controller; 280 + 281 + vcc1-supply = <&vcc5v0_sys_s5>; 282 + vcc2-supply = <&vcc5v0_sys_s5>; 283 + vcc3-supply = <&vcc5v0_sys_s5>; 284 + vcc4-supply = <&vcc5v0_sys_s5>; 285 + vcc5-supply = <&vcc5v0_sys_s5>; 286 + vcc6-supply = <&vcc5v0_sys_s5>; 287 + vcc7-supply = <&vcc5v0_sys_s5>; 288 + vcc8-supply = <&vcc5v0_sys_s5>; 289 + vcc9-supply = <&vcc5v0_sys_s5>; 290 + vcc10-supply = <&vcc5v0_sys_s5>; 291 + vcc11-supply = <&vcc_2v0_pldo_s3>; 292 + vcc12-supply = <&vcc5v0_sys_s5>; 293 + vcc13-supply = <&vcc_1v1_nldo_s3>; 294 + vcc14-supply = <&vcc_1v1_nldo_s3>; 295 + vcca-supply = <&vcc5v0_sys_s5>; 296 + 297 + rk806_dvs1_null: dvs1-null-pins { 298 + pins = "gpio_pwrctrl1"; 299 + function = "pin_fun0"; 300 + }; 301 + 302 + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { 303 + pins = "gpio_pwrctrl1"; 304 + function = "pin_fun2"; 305 + }; 306 + 307 + rk806_dvs1_rst: dvs1-rst-pins { 308 + pins = "gpio_pwrctrl1"; 309 + function = "pin_fun3"; 310 + }; 311 + 312 + rk806_dvs1_slp: dvs1-slp-pins { 313 + pins = "gpio_pwrctrl1"; 314 + function = "pin_fun1"; 315 + }; 316 + 317 + rk806_dvs2_dvs: dvs2-dvs-pins { 318 + pins = "gpio_pwrctrl2"; 319 + function = "pin_fun4"; 320 + }; 321 + 322 + rk806_dvs2_gpio: dvs2-gpio-pins { 323 + pins = "gpio_pwrctrl2"; 324 + function = "pin_fun5"; 325 + }; 326 + 327 + rk806_dvs2_null: dvs2-null-pins { 328 + pins = "gpio_pwrctrl2"; 329 + function = "pin_fun0"; 330 + }; 331 + 332 + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { 333 + pins = "gpio_pwrctrl2"; 334 + function = "pin_fun2"; 335 + }; 336 + 337 + rk806_dvs2_rst: dvs2-rst-pins { 338 + pins = "gpio_pwrctrl2"; 339 + function = "pin_fun3"; 340 + }; 341 + 342 + rk806_dvs2_slp: dvs2-slp-pins { 343 + pins = "gpio_pwrctrl2"; 344 + function = "pin_fun1"; 345 + }; 346 + 347 + rk806_dvs3_dvs: dvs3-dvs-pins { 348 + pins = "gpio_pwrctrl3"; 349 + function = "pin_fun4"; 350 + }; 351 + 352 + rk806_dvs3_gpio: dvs3-gpio-pins { 353 + pins = "gpio_pwrctrl3"; 354 + function = "pin_fun5"; 355 + }; 356 + 357 + rk806_dvs3_null: dvs3-null-pins { 358 + pins = "gpio_pwrctrl3"; 359 + function = "pin_fun0"; 360 + }; 361 + 362 + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { 363 + pins = "gpio_pwrctrl3"; 364 + function = "pin_fun2"; 365 + }; 366 + 367 + rk806_dvs3_rst: dvs3-rst-pins { 368 + pins = "gpio_pwrctrl3"; 369 + function = "pin_fun3"; 370 + }; 371 + 372 + rk806_dvs3_slp: dvs3-slp-pins { 373 + pins = "gpio_pwrctrl3"; 374 + function = "pin_fun1"; 375 + }; 376 + 377 + regulators { 378 + vdd_cpu_big_s0: dcdc-reg1 { 379 + regulator-always-on; 380 + regulator-boot-on; 381 + regulator-enable-ramp-delay = <400>; 382 + regulator-min-microvolt = <550000>; 383 + regulator-max-microvolt = <950000>; 384 + regulator-name = "vdd_cpu_big_s0"; 385 + regulator-ramp-delay = <12500>; 386 + 387 + regulator-state-mem { 388 + regulator-off-in-suspend; 389 + }; 390 + }; 391 + 392 + vdd_npu_s0: dcdc-reg2 { 393 + regulator-boot-on; 394 + regulator-enable-ramp-delay = <400>; 395 + regulator-min-microvolt = <550000>; 396 + regulator-max-microvolt = <950000>; 397 + regulator-name = "vdd_npu_s0"; 398 + regulator-ramp-delay = <12500>; 399 + 400 + regulator-state-mem { 401 + regulator-off-in-suspend; 402 + }; 403 + }; 404 + 405 + vdd_cpu_lit_s0: dcdc-reg3 { 406 + regulator-always-on; 407 + regulator-boot-on; 408 + regulator-min-microvolt = <550000>; 409 + regulator-max-microvolt = <950000>; 410 + regulator-name = "vdd_cpu_lit_s0"; 411 + regulator-ramp-delay = <12500>; 412 + 413 + regulator-state-mem { 414 + regulator-off-in-suspend; 415 + regulator-suspend-microvolt = <750000>; 416 + }; 417 + }; 418 + 419 + vcc_3v3_s3: dcdc-reg4 { 420 + regulator-always-on; 421 + regulator-boot-on; 422 + regulator-min-microvolt = <3300000>; 423 + regulator-max-microvolt = <3300000>; 424 + regulator-name = "vcc_3v3_s3"; 425 + 426 + regulator-state-mem { 427 + regulator-on-in-suspend; 428 + regulator-suspend-microvolt = <3300000>; 429 + }; 430 + }; 431 + 432 + vdd_gpu_s0: dcdc-reg5 { 433 + regulator-boot-on; 434 + regulator-enable-ramp-delay = <400>; 435 + regulator-min-microvolt = <550000>; 436 + regulator-max-microvolt = <900000>; 437 + regulator-name = "vdd_gpu_s0"; 438 + regulator-ramp-delay = <12500>; 439 + 440 + regulator-state-mem { 441 + regulator-off-in-suspend; 442 + regulator-suspend-microvolt = <850000>; 443 + }; 444 + }; 445 + 446 + vddq_ddr_s0: dcdc-reg6 { 447 + regulator-always-on; 448 + regulator-boot-on; 449 + regulator-name = "vddq_ddr_s0"; 450 + 451 + regulator-state-mem { 452 + regulator-off-in-suspend; 453 + }; 454 + }; 455 + 456 + vdd_logic_s0: dcdc-reg7 { 457 + regulator-always-on; 458 + regulator-boot-on; 459 + regulator-min-microvolt = <550000>; 460 + regulator-max-microvolt = <800000>; 461 + regulator-name = "vdd_logic_s0"; 462 + 463 + regulator-state-mem { 464 + regulator-off-in-suspend; 465 + }; 466 + }; 467 + 468 + vcc_1v8_s3: dcdc-reg8 { 469 + regulator-always-on; 470 + regulator-boot-on; 471 + regulator-min-microvolt = <1800000>; 472 + regulator-max-microvolt = <1800000>; 473 + regulator-name = "vcc_1v8_s3"; 474 + 475 + regulator-state-mem { 476 + regulator-on-in-suspend; 477 + regulator-suspend-microvolt = <1800000>; 478 + }; 479 + }; 480 + 481 + vdd2_ddr_s3: dcdc-reg9 { 482 + regulator-always-on; 483 + regulator-boot-on; 484 + regulator-name = "vdd2_ddr_s3"; 485 + 486 + regulator-state-mem { 487 + regulator-on-in-suspend; 488 + }; 489 + }; 490 + 491 + vdd_ddr_s0: dcdc-reg10 { 492 + regulator-always-on; 493 + regulator-boot-on; 494 + regulator-min-microvolt = <550000>; 495 + regulator-max-microvolt = <1200000>; 496 + regulator-name = "vdd_ddr_s0"; 497 + 498 + regulator-state-mem { 499 + regulator-off-in-suspend; 500 + }; 501 + }; 502 + 503 + vcca_1v8_s0: pldo-reg1 { 504 + regulator-always-on; 505 + regulator-boot-on; 506 + regulator-min-microvolt = <1800000>; 507 + regulator-max-microvolt = <1800000>; 508 + regulator-name = "vcca_1v8_s0"; 509 + 510 + regulator-state-mem { 511 + regulator-off-in-suspend; 512 + }; 513 + }; 514 + 515 + vcca1v8_pldo2_s0: pldo-reg2 { 516 + regulator-always-on; 517 + regulator-boot-on; 518 + regulator-min-microvolt = <1800000>; 519 + regulator-max-microvolt = <1800000>; 520 + regulator-name = "vcca1v8_pldo2_s0"; 521 + 522 + regulator-state-mem { 523 + regulator-off-in-suspend; 524 + }; 525 + }; 526 + 527 + vdda_1v2_s0: pldo-reg3 { 528 + regulator-always-on; 529 + regulator-boot-on; 530 + regulator-min-microvolt = <1200000>; 531 + regulator-max-microvolt = <1200000>; 532 + regulator-name = "vdda_1v2_s0"; 533 + 534 + regulator-state-mem { 535 + regulator-off-in-suspend; 536 + }; 537 + }; 538 + 539 + vcca_3v3_s0: pldo-reg4 { 540 + regulator-always-on; 541 + regulator-boot-on; 542 + regulator-min-microvolt = <3300000>; 543 + regulator-max-microvolt = <3300000>; 544 + regulator-name = "vcca_3v3_s0"; 545 + 546 + regulator-state-mem { 547 + regulator-off-in-suspend; 548 + }; 549 + }; 550 + 551 + vccio_sd_s0: pldo-reg5 { 552 + regulator-always-on; 553 + regulator-boot-on; 554 + regulator-min-microvolt = <1800000>; 555 + regulator-max-microvolt = <3300000>; 556 + regulator-name = "vccio_sd_s0"; 557 + 558 + regulator-state-mem { 559 + regulator-off-in-suspend; 560 + }; 561 + }; 562 + 563 + vcca1v8_pldo6_s3: pldo-reg6 { 564 + regulator-always-on; 565 + regulator-boot-on; 566 + regulator-min-microvolt = <1800000>; 567 + regulator-max-microvolt = <1800000>; 568 + regulator-name = "vcca1v8_pldo6_s3"; 569 + 570 + regulator-state-mem { 571 + regulator-on-in-suspend; 572 + regulator-suspend-microvolt = <1800000>; 573 + }; 574 + }; 575 + 576 + vdd_0v75_s3: nldo-reg1 { 577 + regulator-always-on; 578 + regulator-boot-on; 579 + regulator-min-microvolt = <750000>; 580 + regulator-max-microvolt = <750000>; 581 + regulator-name = "vdd_0v75_s3"; 582 + 583 + regulator-state-mem { 584 + regulator-on-in-suspend; 585 + regulator-suspend-microvolt = <750000>; 586 + }; 587 + }; 588 + 589 + vdda_ddr_pll_s0: nldo-reg2 { 590 + regulator-always-on; 591 + regulator-boot-on; 592 + regulator-min-microvolt = <850000>; 593 + regulator-max-microvolt = <850000>; 594 + regulator-name = "vdda_ddr_pll_s0"; 595 + 596 + regulator-state-mem { 597 + regulator-off-in-suspend; 598 + }; 599 + }; 600 + 601 + vdda0v75_hdmi_s0: nldo-reg3 { 602 + regulator-always-on; 603 + regulator-boot-on; 604 + regulator-min-microvolt = <837500>; 605 + regulator-max-microvolt = <837500>; 606 + regulator-name = "vdda0v75_hdmi_s0"; 607 + 608 + regulator-state-mem { 609 + regulator-off-in-suspend; 610 + }; 611 + }; 612 + 613 + vdda_0v85_s0: nldo-reg4 { 614 + regulator-always-on; 615 + regulator-boot-on; 616 + regulator-min-microvolt = <850000>; 617 + regulator-max-microvolt = <850000>; 618 + regulator-name = "vdda_0v85_s0"; 619 + 620 + regulator-state-mem { 621 + regulator-off-in-suspend; 622 + }; 623 + }; 624 + 625 + vdda_0v75_s0: nldo-reg5 { 626 + regulator-always-on; 627 + regulator-boot-on; 628 + regulator-min-microvolt = <750000>; 629 + regulator-max-microvolt = <750000>; 630 + regulator-name = "vdda_0v75_s0"; 631 + 632 + regulator-state-mem { 633 + regulator-off-in-suspend; 634 + }; 635 + }; 636 + }; 637 + }; 638 + }; 639 + 640 + &i2c2 { 641 + status = "okay"; 642 + 643 + hym8563: rtc@51 { 644 + compatible = "haoyu,hym8563"; 645 + reg = <0x51>; 646 + #clock-cells = <0>; 647 + clock-output-names = "hym8563"; 648 + interrupt-parent = <&gpio0>; 649 + interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>; 650 + pinctrl-names = "default"; 651 + pinctrl-0 = <&rtc_int_l>; 652 + wakeup-source; 653 + }; 654 + }; 655 + 656 + &pcie0 { 657 + pinctrl-names = "default"; 658 + pinctrl-0 = <&pcie0_perstn>; 659 + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; 660 + vpcie3v3-supply = <&vcc_3v3_s3>; 661 + status = "okay"; 662 + }; 663 + 664 + &pcie1 { 665 + pinctrl-names = "default"; 666 + pinctrl-0 = <&pcie1_perstn>; 667 + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 668 + vpcie3v3-supply = <&vcc_3v3_s3>; 669 + status = "okay"; 670 + }; 671 + 672 + &pinctrl { 673 + bt { 674 + bt_reg_on_h: bt-reg-on-h { 675 + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 676 + }; 677 + 678 + bt_wake_host_h: bt-wake-host-h { 679 + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; 680 + }; 681 + 682 + host_wake_bt_h: host-wake-bt-h { 683 + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; 684 + }; 685 + }; 686 + 687 + gpio-keys { 688 + user_but_pin: user-but-pin { 689 + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 690 + }; 691 + }; 692 + 693 + gpio-leds { 694 + led_sys_h: led-sys-h { 695 + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 696 + }; 697 + 698 + led1_h: led1-h { 699 + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 700 + }; 701 + 702 + led2_h: led2-h { 703 + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 704 + }; 705 + }; 706 + 707 + hdmi { 708 + hdmi_tx_on_h: hdmi-tx-on-h { 709 + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 710 + }; 711 + }; 712 + 713 + hym8563 { 714 + rtc_int_l: rtc-int-l { 715 + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 716 + }; 717 + }; 718 + 719 + pcie { 720 + pcie0_perstn: pcie0-perstn { 721 + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 722 + }; 723 + 724 + pcie1_perstn: pcie1-perstn { 725 + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 726 + }; 727 + }; 728 + 729 + usb { 730 + usb_otg0_pwren_h: usb-otg0-pwren-h { 731 + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 732 + }; 733 + }; 734 + 735 + wifi { 736 + wifi_wake_host_h: wifi-wake-host-h { 737 + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; 738 + }; 739 + 740 + wifi_reg_on_h: wifi-reg-on-h { 741 + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; 742 + }; 743 + }; 744 + }; 745 + 746 + &sai6 { 747 + status = "okay"; 748 + }; 749 + 750 + &sdmmc { 751 + bus-width = <4>; 752 + cap-mmc-highspeed; 753 + cap-sd-highspeed; 754 + disable-wp; 755 + no-mmc; 756 + no-sdio; 757 + sd-uhs-sdr104; 758 + vmmc-supply = <&vcc_3v3_s3>; 759 + vqmmc-supply = <&vccio_sd_s0>; 760 + status = "okay"; 761 + }; 762 + 763 + &sdio { 764 + #address-cells = <1>; 765 + #size-cells = <0>; 766 + bus-width = <4>; 767 + cap-sd-highspeed; 768 + cap-sdio-irq; 769 + disable-wp; 770 + keep-power-in-suspend; 771 + mmc-pwrseq = <&sdio_pwrseq>; 772 + no-mmc; 773 + no-sd; 774 + non-removable; 775 + sd-uhs-sdr104; 776 + vmmc-supply = <&vcc_3v3_s3>; 777 + vqmmc-supply = <&vcc_1v8_s3>; 778 + wakeup-source; 779 + status = "okay"; 780 + 781 + rtl8822cs: wifi@1 { 782 + reg = <1>; 783 + interrupt-parent = <&gpio0>; 784 + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_HIGH>; 785 + interrupt-names = "host-wake"; 786 + pinctrl-names = "default"; 787 + pinctrl-0 = <&wifi_wake_host_h>; 788 + }; 789 + }; 790 + 791 + &sdhci { 792 + bus-width = <8>; 793 + cap-mmc-highspeed; 794 + full-pwr-cycle-in-suspend; 795 + mmc-hs400-1_8v; 796 + mmc-hs400-enhanced-strobe; 797 + no-sdio; 798 + no-sd; 799 + non-removable; 800 + status = "okay"; 801 + }; 802 + 803 + &saradc { 804 + vref-supply = <&vcca_1v8_s0>; 805 + status = "okay"; 806 + }; 807 + 808 + &u2phy0 { 809 + status = "okay"; 810 + }; 811 + 812 + &u2phy0_otg { 813 + phy-supply = <&vcc5v0_usb_otg0>; 814 + status = "okay"; 815 + }; 816 + 817 + &uart0 { 818 + status = "okay"; 819 + }; 820 + 821 + &uart5 { 822 + pinctrl-names = "default"; 823 + pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; 824 + uart-has-rtscts; 825 + status = "okay"; 826 + 827 + bluetooth { 828 + compatible = "realtek,rtl8822cs-bt"; 829 + enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; 830 + device-wake-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; 831 + host-wake-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; 832 + pinctrl-names = "default"; 833 + pinctrl-0 = <&bt_wake_host_h &host_wake_bt_h &bt_reg_on_h>; 834 + }; 835 + }; 836 + 837 + &usbdp_phy { 838 + status = "okay"; 839 + }; 840 + 841 + &usb_drd0_dwc3 { 842 + dr_mode = "host"; 843 + extcon = <&u2phy0>; 844 + status = "okay"; 845 + }; 846 + 847 + &vop { 848 + status = "okay"; 849 + }; 850 + 851 + &vop_mmu { 852 + status = "okay"; 853 + }; 854 + 855 + &vp0 { 856 + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 857 + reg = <ROCKCHIP_VOP2_EP_HDMI0>; 858 + remote-endpoint = <&hdmi_in_vp0>; 859 + }; 860 + };
+1
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
··· 2181 2181 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 2182 2182 <&cru SRST_T_EMMC>; 2183 2183 reset-names = "core", "bus", "axi", "block", "timer"; 2184 + supports-cqe; 2184 2185 status = "disabled"; 2185 2186 }; 2186 2187
+48
arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
··· 25 25 stdout-path = "serial2:1500000n8"; 26 26 }; 27 27 28 + dp-con { 29 + compatible = "dp-connector"; 30 + label = "DP OUT"; 31 + type = "full-size"; 32 + 33 + port { 34 + dp_con_in: endpoint { 35 + remote-endpoint = <&dp0_out_con>; 36 + }; 37 + }; 38 + }; 39 + 28 40 hdmi-con { 29 41 compatible = "hdmi-connector"; 30 42 type = "a"; ··· 115 103 regulator-min-microvolt = <5000000>; 116 104 regulator-max-microvolt = <5000000>; 117 105 vin-supply = <&vcc12v_dcin>; 106 + }; 107 + }; 108 + 109 + &dp0 { 110 + pinctrl-0 = <&dp0m0_pins>; 111 + pinctrl-names = "default"; 112 + status = "okay"; 113 + }; 114 + 115 + &dp0_in { 116 + dp0_in_vp2: endpoint { 117 + remote-endpoint = <&vp2_out_dp0>; 118 + }; 119 + }; 120 + 121 + &dp0_out { 122 + dp0_out_con: endpoint { 123 + remote-endpoint = <&dp_con_in>; 118 124 }; 119 125 }; 120 126 ··· 946 916 }; 947 917 948 918 &vop { 919 + /* 920 + * If no dedicated PLL was specified, the GPLL would be automatically 921 + * assigned as the PLL source for dclk_vop2. As the frequency of GPLL 922 + * is 1188 MHz, we can only get typical clock frequencies such as 923 + * 74.25MHz, 148.5MHz, 297MHz, 594MHz. 924 + * 925 + * So here we set the parent clock of VP2 to V0PLL so that we can get 926 + * any frequency. 927 + */ 928 + assigned-clocks = <&cru DCLK_VOP2_SRC>; 929 + assigned-clock-parents = <&cru PLL_V0PLL>; 949 930 status = "okay"; 950 931 }; 951 932 ··· 968 927 vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 969 928 reg = <ROCKCHIP_VOP2_EP_HDMI0>; 970 929 remote-endpoint = <&hdmi0_in_vp0>; 930 + }; 931 + }; 932 + 933 + &vp2 { 934 + vp2_out_dp0: endpoint@a { 935 + reg = <ROCKCHIP_VOP2_EP_DP0>; 936 + remote-endpoint = <&dp0_in_vp2>; 971 937 }; 972 938 };
+17 -2
arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
··· 345 345 }; 346 346 }; 347 347 348 + &hdmi1_sound { 349 + status = "okay"; 350 + }; 351 + 348 352 &hdptxphy1 { 349 353 status = "okay"; 350 354 }; ··· 550 546 }; 551 547 }; 552 548 549 + /* HDMI1 ("HDMI TX1 8K") audio */ 550 + &i2s6_8ch { 551 + status = "okay"; 552 + }; 553 + 553 554 &package_thermal { 554 555 polling-delay = <1000>; 555 556 ··· 676 667 led_pins: led-pins { 677 668 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, 678 669 <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 670 + }; 671 + }; 672 + 673 + mmc { 674 + sdmmc_det_pin: sdmmc-det-pin { 675 + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 679 676 }; 680 677 }; 681 678 ··· 810 795 bus-width = <4>; 811 796 cap-mmc-highspeed; 812 797 cap-sd-highspeed; 798 + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 813 799 disable-wp; 814 - max-frequency = <200000000>; 815 800 no-sdio; 816 801 no-mmc; 817 802 pinctrl-names = "default"; 818 - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; 803 + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det_pin>; 819 804 sd-uhs-sdr104; 820 805 vmmc-supply = <&vcc_3v3_s3>; 821 806 vqmmc-supply = <&vccio_sd_s0>;
+10 -3
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
··· 331 331 data-role = "dual"; 332 332 /* fusb302 supports PD Rev 2.0 Ver 1.2 */ 333 333 pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>; 334 - power-role = "sink"; 335 - try-power-role = "sink"; 336 334 op-sink-microwatt = <1000000>; 337 335 sink-pdos = 338 336 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>, 339 337 <PDO_VAR(5000, 20000, 5000)>; 338 + source-pdos = 339 + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 340 340 341 341 altmodes { 342 342 displayport { ··· 509 509 }; 510 510 }; 511 511 512 + mmc { 513 + sdmmc_det_pin: sdmmc-det-pin { 514 + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 515 + }; 516 + }; 517 + 512 518 pcie2 { 513 519 pcie2_0_rst: pcie2-0-rst { 514 520 rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ··· 596 590 }; 597 591 598 592 &sdmmc { 599 - max-frequency = <200000000>; 600 593 no-sdio; 601 594 no-mmc; 602 595 bus-width = <4>; ··· 603 598 cap-sd-highspeed; 604 599 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 605 600 disable-wp; 601 + pinctrl-names = "default"; 602 + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det_pin>; 606 603 sd-uhs-sdr104; 607 604 vmmc-supply = <&vcc_3v3_s3>; 608 605 vqmmc-supply = <&vccio_sd_s0>;
+5
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
··· 110 110 }; 111 111 }; 112 112 113 + &usb_con { 114 + power-role = "dual"; 115 + try-power-role = "sink"; 116 + }; 117 + 113 118 &usbdp_phy0 { 114 119 pinctrl-names = "default"; 115 120 pinctrl-0 = <&usbc_sbu_dc>;
+4
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
··· 49 49 }; 50 50 }; 51 51 52 + &usb_con { 53 + power-role = "sink"; 54 + }; 55 + 52 56 &usbdp_phy0 { 53 57 pinctrl-names = "default"; 54 58 pinctrl-0 = <&usbc_sbu_dc>;
+4
arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
··· 130 130 }; 131 131 }; 132 132 133 + &usb_con { 134 + power-role = "source"; 135 + }; 136 + 133 137 &usbdp_phy0 { 134 138 pinctrl-names = "default"; 135 139 pinctrl-0 = <&usbc_sbu_dc>;
-1
arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
··· 465 465 cap-sd-highspeed; 466 466 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 467 467 disable-wp; 468 - max-frequency = <150000000>; 469 468 no-mmc; 470 469 no-sdio; 471 470 sd-uhs-sdr104;
+34
arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
··· 796 796 domain-supply = <&vdd_gpu_s0>; 797 797 }; 798 798 799 + &pd_npu { 800 + domain-supply = <&vdd_npu_s0>; 801 + }; 802 + 799 803 &pinctrl { 800 804 audio-amplifier { 801 805 headphone_amplifier_en: headphone-amplifier-en { ··· 980 976 981 977 &pwm13 { 982 978 pinctrl-0 = <&pwm13m1_pins>; 979 + status = "okay"; 980 + }; 981 + 982 + &rknn_core_0 { 983 + npu-supply = <&vdd_npu_s0>; 984 + sram-supply = <&vdd_npu_s0>; 985 + status = "okay"; 986 + }; 987 + 988 + &rknn_core_1 { 989 + npu-supply = <&vdd_npu_s0>; 990 + sram-supply = <&vdd_npu_s0>; 991 + status = "okay"; 992 + }; 993 + 994 + &rknn_core_2 { 995 + npu-supply = <&vdd_npu_s0>; 996 + sram-supply = <&vdd_npu_s0>; 997 + status = "okay"; 998 + }; 999 + 1000 + &rknn_mmu_0 { 1001 + status = "okay"; 1002 + }; 1003 + 1004 + &rknn_mmu_1 { 1005 + status = "okay"; 1006 + }; 1007 + 1008 + &rknn_mmu_2 { 983 1009 status = "okay"; 984 1010 }; 985 1011
+104 -18
arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
··· 11 11 12 12 / { 13 13 model = "Indiedroid Nova"; 14 + chassis-type = "embedded"; 14 15 compatible = "indiedroid,nova", "rockchip,rk3588s"; 15 16 16 17 adc-keys-0 { ··· 188 187 189 188 &cpu_b3 { 190 189 cpu-supply = <&vdd_cpu_big1_s0>; 190 + }; 191 + 192 + &dp0 { 193 + status = "okay"; 194 + }; 195 + 196 + &dp0_in { 197 + dp0_in_vp1: endpoint { 198 + remote-endpoint = <&vp1_out_dp0>; 199 + }; 200 + }; 201 + 202 + &dp0_out { 203 + dp0_out_con: endpoint { 204 + remote-endpoint = <&usbdp_phy0_dp_in>; 205 + }; 191 206 }; 192 207 193 208 /* ··· 387 370 sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 388 371 op-sink-microwatt = <1000000>; 389 372 373 + altmodes { 374 + displayport { 375 + svid = /bits/ 16 <0xff01>; 376 + vdo = <0xffffffff>; 377 + }; 378 + }; 379 + 380 + 390 381 ports { 391 382 #address-cells = <1>; 392 383 #size-cells = <0>; 393 384 394 385 port@0 { 395 386 reg = <0>; 396 - usbc0_orien_sw: endpoint { 397 - remote-endpoint = <&usbdp_phy0_orientation_switch>; 387 + usbc0_hs: endpoint { 388 + remote-endpoint = <&usb_host0_xhci_hs>; 398 389 }; 399 390 }; 400 391 401 392 port@1 { 402 393 reg = <1>; 403 - usbc0_role_sw: endpoint { 404 - remote-endpoint = <&dwc3_0_role_switch>; 394 + usbc0_ss: endpoint { 395 + remote-endpoint = <&usbdp_phy0_ss_out>; 405 396 }; 406 397 }; 407 398 408 399 port@2 { 409 400 reg = <2>; 410 - dp_altmode_mux: endpoint { 411 - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 401 + usbc0_sbu: endpoint { 402 + remote-endpoint = <&usbdp_phy0_dp_out>; 412 403 }; 413 404 }; 414 405 }; ··· 492 467 domain-supply = <&vdd_gpu_s0>; 493 468 }; 494 469 470 + &pd_npu { 471 + domain-supply = <&vdd_npu_s0>; 472 + }; 473 + 495 474 &pinctrl { 496 475 bluetooth-pins { 497 476 bt_reset: bt-reset { ··· 548 519 }; 549 520 }; 550 521 522 + &rknn_core_0 { 523 + npu-supply = <&vdd_npu_s0>; 524 + sram-supply = <&vdd_npu_s0>; 525 + status = "okay"; 526 + }; 527 + 528 + &rknn_core_1 { 529 + npu-supply = <&vdd_npu_s0>; 530 + sram-supply = <&vdd_npu_s0>; 531 + status = "okay"; 532 + }; 533 + 534 + &rknn_core_2 { 535 + npu-supply = <&vdd_npu_s0>; 536 + sram-supply = <&vdd_npu_s0>; 537 + status = "okay"; 538 + }; 539 + 540 + &rknn_mmu_0 { 541 + status = "okay"; 542 + }; 543 + 544 + &rknn_mmu_1 { 545 + status = "okay"; 546 + }; 547 + 548 + &rknn_mmu_2 { 549 + status = "okay"; 550 + }; 551 + 551 552 &saradc { 552 553 vref-supply = <&vcca_1v8_s0>; 553 554 status = "okay"; 554 555 }; 555 556 556 - /* HS400 modes seemed to cause io errors. */ 557 557 &sdhci { 558 558 bus-width = <8>; 559 - no-mmc-hs400; 559 + mmc-hs400-1_8v; 560 + mmc-hs400-enhanced-strobe; 560 561 no-sd; 561 562 no-sdio; 562 563 non-removable; ··· 955 896 status = "okay"; 956 897 }; 957 898 958 - /* DMA seems to interfere with bluetooth device normal operation. */ 959 899 &uart9 { 960 900 pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>; 961 901 pinctrl-names = "default"; 962 - /delete-property/ dma-names; 963 - /delete-property/ dmas; 964 902 uart-has-rtscts; 965 903 status = "okay"; 966 904 ··· 984 928 usb-role-switch; 985 929 status = "okay"; 986 930 987 - port { 988 - dwc3_0_role_switch: endpoint { 989 - remote-endpoint = <&usbc0_role_sw>; 931 + ports { 932 + #address-cells = <1>; 933 + #size-cells = <0>; 934 + 935 + port@0 { 936 + reg = <0>; 937 + usb_host0_xhci_hs: endpoint { 938 + remote-endpoint = <&usbc0_hs>; 939 + }; 940 + }; 941 + 942 + port@1 { 943 + reg = <1>; 944 + usb_host0_xhci_ss: endpoint { 945 + remote-endpoint = <&usbdp_phy0_ss_in>; 946 + }; 990 947 }; 991 948 }; 992 949 }; ··· 1028 959 #address-cells = <1>; 1029 960 #size-cells = <0>; 1030 961 1031 - usbdp_phy0_orientation_switch: endpoint@0 { 962 + usbdp_phy0_ss_out: endpoint@0 { 1032 963 reg = <0>; 1033 - remote-endpoint = <&usbc0_orien_sw>; 964 + remote-endpoint = <&usbc0_ss>; 1034 965 }; 1035 966 1036 - usbdp_phy0_dp_altmode_mux: endpoint@1 { 967 + usbdp_phy0_ss_in: endpoint@1 { 1037 968 reg = <1>; 1038 - remote-endpoint = <&dp_altmode_mux>; 969 + remote-endpoint = <&usb_host0_xhci_ss>; 970 + }; 971 + 972 + usbdp_phy0_dp_in: endpoint@2 { 973 + reg = <2>; 974 + remote-endpoint = <&dp0_out_con>; 975 + }; 976 + 977 + usbdp_phy0_dp_out: endpoint@3 { 978 + reg = <3>; 979 + remote-endpoint = <&usbc0_sbu>; 1039 980 }; 1040 981 }; 1041 982 }; ··· 1062 983 vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 1063 984 reg = <ROCKCHIP_VOP2_EP_HDMI0>; 1064 985 remote-endpoint = <&hdmi0_in_vp0>; 986 + }; 987 + }; 988 + 989 + &vp1 { 990 + vp1_out_dp0: endpoint@a { 991 + reg = <ROCKCHIP_VOP2_EP_DP0>; 992 + remote-endpoint = <&dp0_in_vp1>; 1065 993 }; 1066 994 };
+16 -7
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
··· 228 228 regulator-off-in-suspend; 229 229 }; 230 230 }; 231 + 232 + eeprom: eeprom@50 { 233 + compatible = "belling,bl24c16a", "atmel,24c16"; 234 + reg = <0x50>; 235 + pagesize = <16>; 236 + vcc-supply = <&vcc_3v3_pmu>; 237 + }; 231 238 }; 232 239 233 240 &i2c2 { ··· 255 248 regulator-state-mem { 256 249 regulator-off-in-suspend; 257 250 }; 258 - }; 259 - 260 - eeprom: eeprom@50 { 261 - compatible = "belling,bl24c16a", "atmel,24c16"; 262 - reg = <0x50>; 263 - pagesize = <16>; 264 251 }; 265 252 }; 266 253 ··· 378 377 }; 379 378 }; 380 379 380 + mmc { 381 + sdmmc_det_pin: sdmmc-det-pin { 382 + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 383 + }; 384 + }; 385 + 381 386 pcie { 382 387 pow_en: pow-en { 383 388 rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ··· 443 436 max-frequency = <150000000>; 444 437 no-sdio; 445 438 no-mmc; 439 + pinctrl-names = "default"; 440 + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det_pin>; 446 441 sd-uhs-sdr104; 447 442 vmmc-supply = <&vcc_3v3_s0>; 448 443 vqmmc-supply = <&vccio_sd_s0>; ··· 609 600 }; 610 601 }; 611 602 612 - vcc_3v3_s3: dcdc-reg8 { 603 + vcc_3v3_pmu: vcc_3v3_s3: dcdc-reg8 { 613 604 regulator-name = "vcc_3v3_s3"; 614 605 regulator-always-on; 615 606 regulator-boot-on;
+9
arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
··· 473 473 }; 474 474 }; 475 475 476 + mmc { 477 + sdmmc_det_pin: sdmmc-det-pin { 478 + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 479 + }; 480 + }; 481 + 476 482 pcie { 477 483 pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 { 478 484 rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ··· 539 533 bus-width = <4>; 540 534 cap-mmc-highspeed; 541 535 cap-sd-highspeed; 536 + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 542 537 disable-wp; 543 538 no-sdio; 544 539 no-mmc; 540 + pinctrl-names = "default"; 541 + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det_pin>; 545 542 sd-uhs-sdr104; 546 543 vmmc-supply = <&vcc_3v3_s3>; 547 544 vqmmc-supply = <&vccio_sd_s0>;
+6
include/dt-bindings/clock/rk3568-cru.h
··· 485 485 486 486 #define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) 487 487 488 + /* scmi-clocks indices */ 489 + 490 + #define SCMI_CLK_CPU 0 491 + #define SCMI_CLK_GPU 1 492 + #define SCMI_CLK_NPU 2 493 + 488 494 /* pmu soft-reset indices */ 489 495 /* pmucru_softrst_con0 */ 490 496 #define SRST_P_PDPMU_NIU 0