tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
[MIPS] Split up war.h
It was getting a little big, ugly and a primary source for merge conflicts.
Also the old method was a bit too forgiving in that the workaround did
default to off, so now there is an explicit #error forcing platform
maintainers to think if they should enable a workaround for a particular
platform.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+625
-97
+25
include/asm-mips/mach-au1x00/war.h
+25
include/asm-mips/mach-au1x00/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
9
+
#define __ASM_MIPS_MACH_AU1X00_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */
+25
include/asm-mips/mach-bcm47xx/war.h
+25
include/asm-mips/mach-bcm47xx/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H
9
+
#define __ASM_MIPS_MACH_BCM947XX_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */
+25
include/asm-mips/mach-cobalt/war.h
+25
include/asm-mips/mach-cobalt/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_COBALT_WAR_H
9
+
#define __ASM_MIPS_MACH_COBALT_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */
+25
include/asm-mips/mach-dec/war.h
+25
include/asm-mips/mach-dec/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_DEC_WAR_H
9
+
#define __ASM_MIPS_MACH_DEC_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_DEC_WAR_H */
+25
include/asm-mips/mach-emma2rh/war.h
+25
include/asm-mips/mach-emma2rh/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H
9
+
#define __ASM_MIPS_MACH_EMMA2RH_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */
+25
include/asm-mips/mach-excite/war.h
+25
include/asm-mips/mach-excite/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H
9
+
#define __ASM_MIPS_MACH_EXCITE_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 1
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 1
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */
+29
include/asm-mips/mach-ip22/war.h
+29
include/asm-mips/mach-ip22/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_IP22_WAR_H
9
+
#define __ASM_MIPS_MACH_IP22_WAR_H
10
+
11
+
/*
12
+
* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
13
+
*/
14
+
15
+
#define R4600_V1_INDEX_ICACHEOP_WAR 1
16
+
#define R4600_V1_HIT_CACHEOP_WAR 1
17
+
#define R4600_V2_HIT_CACHEOP_WAR 1
18
+
#define R5432_CP0_INTERRUPT_WAR 0
19
+
#define BCM1250_M3_WAR 0
20
+
#define SIBYTE_1956_WAR 0
21
+
#define MIPS4K_ICACHE_REFILL_WAR 0
22
+
#define MIPS_CACHE_SYNC_WAR 0
23
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
24
+
#define RM9000_CDEX_SMP_WAR 0
25
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
26
+
#define R10000_LLSC_WAR 0
27
+
#define MIPS34K_MISSED_ITLB_WAR 0
28
+
29
+
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
+25
include/asm-mips/mach-ip27/war.h
+25
include/asm-mips/mach-ip27/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
9
+
#define __ASM_MIPS_MACH_IP27_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 1
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
+25
include/asm-mips/mach-ip32/war.h
+25
include/asm-mips/mach-ip32/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
9
+
#define __ASM_MIPS_MACH_IP32_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 1
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
+25
include/asm-mips/mach-jazz/war.h
+25
include/asm-mips/mach-jazz/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H
9
+
#define __ASM_MIPS_MACH_JAZZ_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */
+25
include/asm-mips/mach-jmr3927/war.h
+25
include/asm-mips/mach-jmr3927/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H
9
+
#define __ASM_MIPS_MACH_JMR3927_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */
+25
include/asm-mips/mach-lasat/war.h
+25
include/asm-mips/mach-lasat/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_LASAT_WAR_H
9
+
#define __ASM_MIPS_MACH_LASAT_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */
+25
include/asm-mips/mach-lemote/war.h
+25
include/asm-mips/mach-lemote/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H
9
+
#define __ASM_MIPS_MACH_LEMOTE_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */
+25
include/asm-mips/mach-mips/war.h
+25
include/asm-mips/mach-mips/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
9
+
#define __ASM_MIPS_MACH_MIPS_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 1
18
+
#define MIPS_CACHE_SYNC_WAR 1
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 1
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
+25
include/asm-mips/mach-mipssim/war.h
+25
include/asm-mips/mach-mipssim/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
9
+
#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */
+25
include/asm-mips/mach-pnx8550/war.h
+25
include/asm-mips/mach-pnx8550/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
9
+
#define __ASM_MIPS_MACH_PNX8550_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
+25
include/asm-mips/mach-qemu/war.h
+25
include/asm-mips/mach-qemu/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_QEMU_WAR_H
9
+
#define __ASM_MIPS_MACH_QEMU_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */
+29
include/asm-mips/mach-rm/war.h
+29
include/asm-mips/mach-rm/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_RM_WAR_H
9
+
#define __ASM_MIPS_MACH_RM_WAR_H
10
+
11
+
/*
12
+
* The RM200C seems to have been shipped only with V2.0 R4600s
13
+
*/
14
+
15
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
16
+
#define R4600_V1_HIT_CACHEOP_WAR 0
17
+
#define R4600_V2_HIT_CACHEOP_WAR 1
18
+
#define R5432_CP0_INTERRUPT_WAR 0
19
+
#define BCM1250_M3_WAR 0
20
+
#define SIBYTE_1956_WAR 0
21
+
#define MIPS4K_ICACHE_REFILL_WAR 0
22
+
#define MIPS_CACHE_SYNC_WAR 0
23
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
24
+
#define RM9000_CDEX_SMP_WAR 0
25
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
26
+
#define R10000_LLSC_WAR 0
27
+
#define MIPS34K_MISSED_ITLB_WAR 0
28
+
29
+
#endif /* __ASM_MIPS_MACH_RM_WAR_H */
+37
include/asm-mips/mach-sibyte/war.h
+37
include/asm-mips/mach-sibyte/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
9
+
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
16
+
#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
17
+
defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
18
+
19
+
#define BCM1250_M3_WAR 1
20
+
#define SIBYTE_1956_WAR 1
21
+
22
+
#else
23
+
24
+
#define BCM1250_M3_WAR 0
25
+
#define SIBYTE_1956_WAR 0
26
+
27
+
#endif
28
+
29
+
#define MIPS4K_ICACHE_REFILL_WAR 0
30
+
#define MIPS_CACHE_SYNC_WAR 0
31
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
32
+
#define RM9000_CDEX_SMP_WAR 0
33
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
34
+
#define R10000_LLSC_WAR 0
35
+
#define MIPS34K_MISSED_ITLB_WAR 0
36
+
37
+
#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
+25
include/asm-mips/mach-tx49xx/war.h
+25
include/asm-mips/mach-tx49xx/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
9
+
#define __ASM_MIPS_MACH_TX49XX_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 1
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
+25
include/asm-mips/mach-vr41xx/war.h
+25
include/asm-mips/mach-vr41xx/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H
9
+
#define __ASM_MIPS_MACH_VR41XX_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 0
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */
+25
include/asm-mips/mach-wrppmc/war.h
+25
include/asm-mips/mach-wrppmc/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
9
+
#define __ASM_MIPS_MACH_WRPPMC_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 0
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 1
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
+25
include/asm-mips/mach-yosemite/war.h
+25
include/asm-mips/mach-yosemite/war.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7
+
*/
8
+
#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
9
+
#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
10
+
11
+
#define R4600_V1_INDEX_ICACHEOP_WAR 0
12
+
#define R4600_V1_HIT_CACHEOP_WAR 0
13
+
#define R4600_V2_HIT_CACHEOP_WAR 0
14
+
#define R5432_CP0_INTERRUPT_WAR 0
15
+
#define BCM1250_M3_WAR 0
16
+
#define SIBYTE_1956_WAR 0
17
+
#define MIPS4K_ICACHE_REFILL_WAR 0
18
+
#define MIPS_CACHE_SYNC_WAR 0
19
+
#define TX49XX_ICACHE_INDEX_INV_WAR 0
20
+
#define RM9000_CDEX_SMP_WAR 1
21
+
#define ICACHE_REFILLS_WORKAROUND_WAR 1
22
+
#define R10000_LLSC_WAR 0
23
+
#define MIPS34K_MISSED_ITLB_WAR 0
24
+
25
+
#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
+30
-97
include/asm-mips/war.h
+30
-97
include/asm-mips/war.h
···
3
3
* License. See the file "COPYING" in the main directory of this archive
4
4
* for more details.
5
5
*
6
-
* Copyright (C) 2002, 2004 by Ralf Baechle
6
+
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle
7
7
*/
8
8
#ifndef _ASM_WAR_H
9
9
#define _ASM_WAR_H
10
10
11
+
#include <war.h>
11
12
12
13
/*
13
14
* Another R4600 erratum. Due to the lack of errata information the exact
14
15
* technical details aren't known. I've experimentally found that disabling
15
16
* interrupts during indexed I-cache flushes seems to be sufficient to deal
16
17
* with the issue.
17
-
*
18
-
* #define R4600_V1_INDEX_ICACHEOP_WAR 1
19
18
*/
19
+
#ifndef R4600_V1_INDEX_ICACHEOP_WAR
20
+
#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
21
+
#endif
20
22
21
23
/*
22
24
* Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
···
45
43
* nop
46
44
* nop
47
45
* cache Hit_Writeback_Invalidate_D
48
-
*
49
-
* #define R4600_V1_HIT_CACHEOP_WAR 1
50
46
*/
47
+
#ifndef R4600_V1_HIT_CACHEOP_WAR
48
+
#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
49
+
#endif
51
50
52
51
53
52
/*
···
61
58
* by a load instruction to an uncached address to empty the response buffer."
62
59
* (Revision 2.0 device errata from IDT available on http://www.idt.com/
63
60
* in .pdf format.)
64
-
*
65
-
* #define R4600_V2_HIT_CACHEOP_WAR 1
66
61
*/
67
-
68
-
/*
69
-
* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
70
-
*/
71
-
#ifdef CONFIG_SGI_IP22
72
-
73
-
#define R4600_V1_INDEX_ICACHEOP_WAR 1
74
-
#define R4600_V1_HIT_CACHEOP_WAR 1
75
-
#define R4600_V2_HIT_CACHEOP_WAR 1
76
-
62
+
#ifndef R4600_V2_HIT_CACHEOP_WAR
63
+
#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
77
64
#endif
78
-
79
-
/*
80
-
* But the RM200C seems to have been shipped only with V2.0 R4600s
81
-
*/
82
-
#ifdef CONFIG_SNI_RM
83
-
84
-
#define R4600_V2_HIT_CACHEOP_WAR 1
85
-
86
-
#endif
87
-
88
-
#ifdef CONFIG_CPU_R5432
89
65
90
66
/*
91
67
* When an interrupt happens on a CP0 register read instruction, CPU may
···
75
93
* first thing in the exception handler, which breaks one of the
76
94
* pre-conditions for this problem.
77
95
*/
78
-
#define R5432_CP0_INTERRUPT_WAR 1
79
-
96
+
#ifndef R5432_CP0_INTERRUPT_WAR
97
+
#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
80
98
#endif
81
-
82
-
#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
83
-
defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
84
99
85
100
/*
86
101
* Workaround for the Sibyte M3 errata the text of which can be found at
···
89
110
* will just return and take the exception again if the information was
90
111
* found to be inconsistent.
91
112
*/
92
-
#define BCM1250_M3_WAR 1
113
+
#ifndef BCM1250_M3_WAR
114
+
#error Check setting of BCM1250_M3_WAR for your platform
115
+
#endif
93
116
94
117
/*
95
118
* This is a DUART workaround related to glitches around register accesses
96
119
*/
97
-
#define SIBYTE_1956_WAR 1
98
-
120
+
#ifndef SIBYTE_1956_WAR
121
+
#error Check setting of SIBYTE_1956_WAR for your platform
99
122
#endif
100
123
101
124
/*
···
112
131
* Affects:
113
132
* MIPS 4K RTL revision <3.0, PRID revision <4
114
133
*/
115
-
#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \
116
-
defined(CONFIG_MIPS_SEAD)
117
-
#define MIPS4K_ICACHE_REFILL_WAR 1
134
+
#ifndef MIPS4K_ICACHE_REFILL_WAR
135
+
#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
118
136
#endif
119
137
120
138
/*
···
131
151
* MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8
132
152
* MIPS 20Kc RTL revision <4.0, PRID revision <?
133
153
*/
134
-
#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \
135
-
defined(CONFIG_MIPS_SEAD)
136
-
#define MIPS_CACHE_SYNC_WAR 1
154
+
#ifndef MIPS_CACHE_SYNC_WAR
155
+
#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
137
156
#endif
138
157
139
158
/*
···
142
163
*
143
164
* Workaround: do two phase flushing for Index_Invalidate_I
144
165
*/
145
-
#ifdef CONFIG_CPU_TX49XX
146
-
#define TX49XX_ICACHE_INDEX_INV_WAR 1
166
+
#ifndef TX49XX_ICACHE_INDEX_INV_WAR
167
+
#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
147
168
#endif
148
169
149
170
/*
150
171
* On the RM9000 there is a problem which makes the CreateDirtyExclusive
151
172
* eache operation unusable on SMP systems.
152
173
*/
153
-
#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
154
-
#define RM9000_CDEX_SMP_WAR 1
174
+
#ifndef RM9000_CDEX_SMP_WAR
175
+
#error Check setting of RM9000_CDEX_SMP_WAR for your platform
155
176
#endif
156
177
157
178
/*
···
160
181
* I-cache line worth of instructions being fetched may case spurious
161
182
* exceptions.
162
183
*/
163
-
#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
164
-
defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \
165
-
defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
166
-
#define ICACHE_REFILLS_WORKAROUND_WAR 1
184
+
#ifndef ICACHE_REFILLS_WORKAROUND_WAR
185
+
#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
167
186
#endif
168
187
169
188
/*
170
189
* On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
171
190
* may cause ll / sc and lld / scd sequences to execute non-atomically.
172
191
*/
173
-
#ifdef CONFIG_SGI_IP27
174
-
#define R10000_LLSC_WAR 1
192
+
#ifndef R10000_LLSC_WAR
193
+
#error Check setting of R10000_LLSC_WAR for your platform
175
194
#endif
176
195
177
196
/*
178
197
* 34K core erratum: "Problems Executing the TLBR Instruction"
179
198
*/
180
-
#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
181
-
defined(CONFIG_PMC_MSP7120_FPGA)
182
-
#define MIPS34K_MISSED_ITLB_WAR 1
183
-
#endif
184
-
185
-
/*
186
-
* Workarounds default to off
187
-
*/
188
-
#ifndef ICACHE_REFILLS_WORKAROUND_WAR
189
-
#define ICACHE_REFILLS_WORKAROUND_WAR 0
190
-
#endif
191
-
#ifndef R4600_V1_INDEX_ICACHEOP_WAR
192
-
#define R4600_V1_INDEX_ICACHEOP_WAR 0
193
-
#endif
194
-
#ifndef R4600_V1_HIT_CACHEOP_WAR
195
-
#define R4600_V1_HIT_CACHEOP_WAR 0
196
-
#endif
197
-
#ifndef R4600_V2_HIT_CACHEOP_WAR
198
-
#define R4600_V2_HIT_CACHEOP_WAR 0
199
-
#endif
200
-
#ifndef R5432_CP0_INTERRUPT_WAR
201
-
#define R5432_CP0_INTERRUPT_WAR 0
202
-
#endif
203
-
#ifndef BCM1250_M3_WAR
204
-
#define BCM1250_M3_WAR 0
205
-
#endif
206
-
#ifndef SIBYTE_1956_WAR
207
-
#define SIBYTE_1956_WAR 0
208
-
#endif
209
-
#ifndef MIPS4K_ICACHE_REFILL_WAR
210
-
#define MIPS4K_ICACHE_REFILL_WAR 0
211
-
#endif
212
-
#ifndef MIPS_CACHE_SYNC_WAR
213
-
#define MIPS_CACHE_SYNC_WAR 0
214
-
#endif
215
-
#ifndef TX49XX_ICACHE_INDEX_INV_WAR
216
-
#define TX49XX_ICACHE_INDEX_INV_WAR 0
217
-
#endif
218
-
#ifndef RM9000_CDEX_SMP_WAR
219
-
#define RM9000_CDEX_SMP_WAR 0
220
-
#endif
221
-
#ifndef R10000_LLSC_WAR
222
-
#define R10000_LLSC_WAR 0
223
-
#endif
224
199
#ifndef MIPS34K_MISSED_ITLB_WAR
225
-
#define MIPS34K_MISSED_ITLB_WAR 0
200
+
#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
226
201
#endif
227
202
228
203
#endif /* _ASM_WAR_H */