Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm: const'ify ioctls table (v2)

Because, there is no reason for it not to be const.

v1: original
v2: fix compile break in vmwgfx, and couple related cleanups suggested
by Ville Syrjälä

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

authored by

Rob Clark and committed by
Dave Airlie
baa70943 31e5d7c6

+29 -30
+2 -2
drivers/gpu/drm/exynos/exynos_drm_drv.c
··· 213 213 .close = drm_gem_vm_close, 214 214 }; 215 215 216 - static struct drm_ioctl_desc exynos_ioctls[] = { 216 + static const struct drm_ioctl_desc exynos_ioctls[] = { 217 217 DRM_IOCTL_DEF_DRV(EXYNOS_GEM_CREATE, exynos_drm_gem_create_ioctl, 218 218 DRM_UNLOCKED | DRM_AUTH), 219 219 DRM_IOCTL_DEF_DRV(EXYNOS_GEM_MAP_OFFSET, ··· 277 277 .gem_prime_export = exynos_dmabuf_prime_export, 278 278 .gem_prime_import = exynos_dmabuf_prime_import, 279 279 .ioctls = exynos_ioctls, 280 + .num_ioctls = ARRAY_SIZE(exynos_ioctls), 280 281 .fops = &exynos_drm_driver_fops, 281 282 .name = DRIVER_NAME, 282 283 .desc = DRIVER_DESC, ··· 289 288 static int exynos_drm_platform_probe(struct platform_device *pdev) 290 289 { 291 290 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 292 - exynos_drm_driver.num_ioctls = DRM_ARRAY_SIZE(exynos_ioctls); 293 291 294 292 return drm_platform_init(&exynos_drm_driver, pdev); 295 293 }
+1 -1
drivers/gpu/drm/gma500/psb_drv.c
··· 131 131 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data, 132 132 struct drm_file *file_priv); 133 133 134 - static struct drm_ioctl_desc psb_ioctls[] = { 134 + static const struct drm_ioctl_desc psb_ioctls[] = { 135 135 DRM_IOCTL_DEF_DRV(GMA_ADB, psb_adb_ioctl, DRM_AUTH), 136 136 DRM_IOCTL_DEF_DRV(GMA_MODE_OPERATION, psb_mode_operation_ioctl, 137 137 DRM_AUTH),
+1 -1
drivers/gpu/drm/i810/i810_dma.c
··· 1241 1241 return 0; 1242 1242 } 1243 1243 1244 - struct drm_ioctl_desc i810_ioctls[] = { 1244 + const struct drm_ioctl_desc i810_ioctls[] = { 1245 1245 DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1246 1246 DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED), 1247 1247 DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
+1 -1
drivers/gpu/drm/i810/i810_drv.h
··· 125 125 extern int i810_driver_device_is_agp(struct drm_device *dev); 126 126 127 127 extern long i810_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 128 - extern struct drm_ioctl_desc i810_ioctls[]; 128 + extern const struct drm_ioctl_desc i810_ioctls[]; 129 129 extern int i810_max_ioctl; 130 130 131 131 #define I810_BASE(reg) ((unsigned long) \
+1 -1
drivers/gpu/drm/i915/i915_dma.c
··· 1834 1834 kfree(file_priv); 1835 1835 } 1836 1836 1837 - struct drm_ioctl_desc i915_ioctls[] = { 1837 + const struct drm_ioctl_desc i915_ioctls[] = { 1838 1838 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1839 1839 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 1840 1840 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
+1 -1
drivers/gpu/drm/i915/i915_drv.h
··· 1566 1566 #define INTEL_RC6p_ENABLE (1<<1) 1567 1567 #define INTEL_RC6pp_ENABLE (1<<2) 1568 1568 1569 - extern struct drm_ioctl_desc i915_ioctls[]; 1569 + extern const struct drm_ioctl_desc i915_ioctls[]; 1570 1570 extern int i915_max_ioctl; 1571 1571 extern unsigned int i915_fbpercrtc __always_unused; 1572 1572 extern int i915_panel_ignore_lid __read_mostly;
+1 -1
drivers/gpu/drm/mga/mga_drv.h
··· 149 149 unsigned int agp_size; 150 150 } drm_mga_private_t; 151 151 152 - extern struct drm_ioctl_desc mga_ioctls[]; 152 + extern const struct drm_ioctl_desc mga_ioctls[]; 153 153 extern int mga_max_ioctl; 154 154 155 155 /* mga_dma.c */
+1 -1
drivers/gpu/drm/mga/mga_state.c
··· 1083 1083 return 0; 1084 1084 } 1085 1085 1086 - struct drm_ioctl_desc mga_ioctls[] = { 1086 + const struct drm_ioctl_desc mga_ioctls[] = { 1087 1087 DRM_IOCTL_DEF_DRV(MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1088 1088 DRM_IOCTL_DEF_DRV(MGA_FLUSH, mga_dma_flush, DRM_AUTH), 1089 1089 DRM_IOCTL_DEF_DRV(MGA_RESET, mga_dma_reset, DRM_AUTH),
+2 -3
drivers/gpu/drm/nouveau/nouveau_drm.c
··· 640 640 nouveau_cli_destroy(cli); 641 641 } 642 642 643 - static struct drm_ioctl_desc 643 + static const struct drm_ioctl_desc 644 644 nouveau_ioctls[] = { 645 645 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH), 646 646 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), ··· 695 695 .disable_vblank = nouveau_drm_vblank_disable, 696 696 697 697 .ioctls = nouveau_ioctls, 698 + .num_ioctls = ARRAY_SIZE(nouveau_ioctls), 698 699 .fops = &nouveau_driver_fops, 699 700 700 701 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, ··· 766 765 static int __init 767 766 nouveau_drm_init(void) 768 767 { 769 - driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls); 770 - 771 768 if (nouveau_modeset == -1) { 772 769 #ifdef CONFIG_VGA_CONSOLE 773 770 if (vgacon_text_force())
+1 -1
drivers/gpu/drm/omapdrm/omap_drv.c
··· 419 419 return ret; 420 420 } 421 421 422 - static struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { 422 + static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { 423 423 DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_UNLOCKED|DRM_AUTH), 424 424 DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 425 425 DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH),
+1 -1
drivers/gpu/drm/qxl/qxl_drv.h
··· 319 319 /* forward declaration for QXL_INFO_IO */ 320 320 void qxl_io_log(struct qxl_device *qdev, const char *fmt, ...); 321 321 322 - extern struct drm_ioctl_desc qxl_ioctls[]; 322 + extern const struct drm_ioctl_desc qxl_ioctls[]; 323 323 extern int qxl_max_ioctl; 324 324 325 325 int qxl_driver_load(struct drm_device *dev, unsigned long flags);
+1 -1
drivers/gpu/drm/qxl/qxl_ioctl.c
··· 402 402 return ret; 403 403 } 404 404 405 - struct drm_ioctl_desc qxl_ioctls[] = { 405 + const struct drm_ioctl_desc qxl_ioctls[] = { 406 406 DRM_IOCTL_DEF_DRV(QXL_ALLOC, qxl_alloc_ioctl, DRM_AUTH|DRM_UNLOCKED), 407 407 408 408 DRM_IOCTL_DEF_DRV(QXL_MAP, qxl_map_ioctl, DRM_AUTH|DRM_UNLOCKED),
+1 -1
drivers/gpu/drm/r128/r128_drv.h
··· 131 131 drm_r128_freelist_t *list_entry; 132 132 } drm_r128_buf_priv_t; 133 133 134 - extern struct drm_ioctl_desc r128_ioctls[]; 134 + extern const struct drm_ioctl_desc r128_ioctls[]; 135 135 extern int r128_max_ioctl; 136 136 137 137 /* r128_cce.c */
+1 -1
drivers/gpu/drm/r128/r128_state.c
··· 1643 1643 r128_do_cleanup_cce(dev); 1644 1644 } 1645 1645 1646 - struct drm_ioctl_desc r128_ioctls[] = { 1646 + const struct drm_ioctl_desc r128_ioctls[] = { 1647 1647 DRM_IOCTL_DEF_DRV(R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1648 1648 DRM_IOCTL_DEF_DRV(R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1649 1649 DRM_IOCTL_DEF_DRV(R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+1 -1
drivers/gpu/drm/radeon/radeon_drv.c
··· 109 109 struct drm_file *file_priv); 110 110 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 111 111 int *vpos, int *hpos); 112 - extern struct drm_ioctl_desc radeon_ioctls_kms[]; 112 + extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 113 113 extern int radeon_max_kms_ioctl; 114 114 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 115 115 int radeon_mode_dumb_mmap(struct drm_file *filp,
+1 -1
drivers/gpu/drm/radeon/radeon_kms.c
··· 722 722 KMS_INVALID_IOCTL(radeon_surface_free_kms) 723 723 724 724 725 - struct drm_ioctl_desc radeon_ioctls_kms[] = { 725 + const struct drm_ioctl_desc radeon_ioctls_kms[] = { 726 726 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 727 727 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 728 728 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+1 -1
drivers/gpu/drm/savage/savage_bci.c
··· 1072 1072 drm_idlelock_release(&file_priv->master->lock); 1073 1073 } 1074 1074 1075 - struct drm_ioctl_desc savage_ioctls[] = { 1075 + const struct drm_ioctl_desc savage_ioctls[] = { 1076 1076 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1077 1077 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH), 1078 1078 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH),
+1 -1
drivers/gpu/drm/savage/savage_drv.h
··· 104 104 S3_LAST 105 105 }; 106 106 107 - extern struct drm_ioctl_desc savage_ioctls[]; 107 + extern const struct drm_ioctl_desc savage_ioctls[]; 108 108 extern int savage_max_ioctl; 109 109 110 110 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
+1 -1
drivers/gpu/drm/sis/sis_drv.h
··· 70 70 struct drm_file *file_priv); 71 71 extern void sis_lastclose(struct drm_device *dev); 72 72 73 - extern struct drm_ioctl_desc sis_ioctls[]; 73 + extern const struct drm_ioctl_desc sis_ioctls[]; 74 74 extern int sis_max_ioctl; 75 75 76 76 #endif
+1 -1
drivers/gpu/drm/sis/sis_mm.c
··· 350 350 return; 351 351 } 352 352 353 - struct drm_ioctl_desc sis_ioctls[] = { 353 + const struct drm_ioctl_desc sis_ioctls[] = { 354 354 DRM_IOCTL_DEF_DRV(SIS_FB_ALLOC, sis_fb_alloc, DRM_AUTH), 355 355 DRM_IOCTL_DEF_DRV(SIS_FB_FREE, sis_drm_free, DRM_AUTH), 356 356 DRM_IOCTL_DEF_DRV(SIS_AGP_INIT, sis_ioctl_agp_init, DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
+1 -1
drivers/gpu/drm/via/via_dma.c
··· 720 720 return ret; 721 721 } 722 722 723 - struct drm_ioctl_desc via_ioctls[] = { 723 + const struct drm_ioctl_desc via_ioctls[] = { 724 724 DRM_IOCTL_DEF_DRV(VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH), 725 725 DRM_IOCTL_DEF_DRV(VIA_FREEMEM, via_mem_free, DRM_AUTH), 726 726 DRM_IOCTL_DEF_DRV(VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),
+1 -1
drivers/gpu/drm/via/via_drv.h
··· 114 114 #define VIA_READ8(reg) DRM_READ8(VIA_BASE, reg) 115 115 #define VIA_WRITE8(reg, val) DRM_WRITE8(VIA_BASE, reg, val) 116 116 117 - extern struct drm_ioctl_desc via_ioctls[]; 117 + extern const struct drm_ioctl_desc via_ioctls[]; 118 118 extern int via_max_ioctl; 119 119 120 120 extern int via_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
+2 -2
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
··· 124 124 * Ioctl definitions. 125 125 */ 126 126 127 - static struct drm_ioctl_desc vmw_ioctls[] = { 127 + static const struct drm_ioctl_desc vmw_ioctls[] = { 128 128 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 129 129 DRM_AUTH | DRM_UNLOCKED), 130 130 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, ··· 782 782 783 783 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 784 784 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 785 - struct drm_ioctl_desc *ioctl = 785 + const struct drm_ioctl_desc *ioctl = 786 786 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 787 787 788 788 if (unlikely(ioctl->cmd_drv != cmd)) {
+1 -1
drivers/gpu/host1x/drm/drm.c
··· 487 487 } 488 488 #endif 489 489 490 - static struct drm_ioctl_desc tegra_drm_ioctls[] = { 490 + static const struct drm_ioctl_desc tegra_drm_ioctls[] = { 491 491 #ifdef CONFIG_DRM_TEGRA_STAGING 492 492 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_UNLOCKED | DRM_AUTH), 493 493 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_UNLOCKED),
+1 -1
drivers/staging/imx-drm/imx-drm-core.c
··· 783 783 } 784 784 EXPORT_SYMBOL_GPL(imx_drm_remove_connector); 785 785 786 - static struct drm_ioctl_desc imx_drm_ioctls[] = { 786 + static const struct drm_ioctl_desc imx_drm_ioctls[] = { 787 787 /* none so far */ 788 788 }; 789 789
+1 -1
include/drm/drmP.h
··· 965 965 966 966 u32 driver_features; 967 967 int dev_priv_size; 968 - struct drm_ioctl_desc *ioctls; 968 + const struct drm_ioctl_desc *ioctls; 969 969 int num_ioctls; 970 970 const struct file_operations *fops; 971 971 union {