tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Treat R14000 like R10000.
[MIPS] Remove EXPERIMENTAL from PAGE_SIZE_16KB
[MIPS] Update/Fix instruction definitions
[MIPS] DSP and MDMX share the same config flag bit.
[MIPS] Fix deadlock on MP with cache aliases.
[MIPS] Use generic STABS_DEBUG macro.
[MIPS] Create consistency in "system type" selection.
[MIPS] Use generic DWARF_DEBUG
[MIPS] Fix kgdb exception handler from user mode.
[MIPS] Update struct sigcontext member names
[MIPS] Update/fix futex assembly
[MIPS] Remove support for sysmips(2) SETNAME and MIPS_RDNVRAM operations.
[MIPS] Fix detection and handling of the 74K processor.
[MIPS] Add missing 34K processor IDs
[MIPS] Fix marking buddy of pte global for MIPS32 w/36-bit physical address
[MIPS] AU1xxx mips_timer_interrupt() fixes
[MIPS] Fix typo

Linus Torvalds ba8f5bab 5cedae9c

+328 -206
unified split
+47 -49
arch/mips/Kconfig
··· 13 default SGI_IP22 14 15 config MIPS_MTX1 16 - bool "Support for 4G Systems MTX-1 board" 17 select DMA_NONCOHERENT 18 select HW_HAS_PCI 19 select SOC_AU1500 ··· 120 select SYS_SUPPORTS_LITTLE_ENDIAN 121 122 config MIPS_COBALT 123 - bool "Support for Cobalt Server" 124 select DMA_NONCOHERENT 125 select HW_HAS_PCI 126 select I8259 ··· 132 select SYS_SUPPORTS_LITTLE_ENDIAN 133 134 config MACH_DECSTATION 135 - bool "Support for DECstations" 136 select BOOT_ELF32 137 select DMA_NONCOHERENT 138 select EARLY_PRINTK ··· 158 otherwise choose R3000. 159 160 config MIPS_EV64120 161 - bool "Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)" 162 depends on EXPERIMENTAL 163 select DMA_NONCOHERENT 164 select HW_HAS_PCI ··· 175 kernel for this platform. 176 177 config MIPS_EV96100 178 - bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)" 179 depends on EXPERIMENTAL 180 select DMA_NONCOHERENT 181 select HW_HAS_PCI ··· 195 here if you wish to build a kernel for this platform. 196 197 config MIPS_IVR 198 - bool "Support for Globespan IVR board" 199 select DMA_NONCOHERENT 200 select HW_HAS_PCI 201 select ITE_BOARD_GEN ··· 211 build a kernel for this platform. 212 213 config MIPS_ITE8172 214 - bool "Support for ITE 8172G board" 215 select DMA_NONCOHERENT 216 select HW_HAS_PCI 217 select ITE_BOARD_GEN ··· 228 a kernel for this platform. 229 230 config MACH_JAZZ 231 - bool "Support for the Jazz family of machines" 232 select ARC 233 select ARC32 234 select ARCH_MAY_HAVE_PC_FDC ··· 246 Olivetti M700-10 workstations. 247 248 config LASAT 249 - bool "Support for LASAT Networks platforms" 250 select DMA_NONCOHERENT 251 select HW_HAS_PCI 252 select MIPS_GT64120 ··· 258 select SYS_SUPPORTS_LITTLE_ENDIAN 259 260 config MIPS_ATLAS 261 - bool "Support for MIPS Atlas board" 262 select BOOT_ELF32 263 select DMA_NONCOHERENT 264 select IRQ_CPU ··· 283 board. 284 285 config MIPS_MALTA 286 - bool "Support for MIPS Malta board" 287 select ARCH_MAY_HAVE_PC_FDC 288 select BOOT_ELF32 289 select HAVE_STD_PC_SERIAL_PORT ··· 311 board. 312 313 config MIPS_SEAD 314 - bool "Support for MIPS SEAD board (EXPERIMENTAL)" 315 depends on EXPERIMENTAL 316 select IRQ_CPU 317 select DMA_NONCOHERENT ··· 328 board. 329 330 config MIPS_SIM 331 - bool 'Support for MIPS simulator (MIPSsim)' 332 select DMA_NONCOHERENT 333 select IRQ_CPU 334 select SYS_HAS_CPU_MIPS32_R1 ··· 341 emulator. 342 343 config MOMENCO_JAGUAR_ATX 344 - bool "Support for Momentum Jaguar board" 345 select BOOT_ELF32 346 select DMA_NONCOHERENT 347 select HW_HAS_PCI ··· 361 Momentum Computer <http://www.momenco.com/>. 362 363 config MOMENCO_OCELOT 364 - bool "Support for Momentum Ocelot board" 365 select DMA_NONCOHERENT 366 select HW_HAS_PCI 367 select IRQ_CPU ··· 378 Momentum Computer <http://www.momenco.com/>. 379 380 config MOMENCO_OCELOT_3 381 - bool "Support for Momentum Ocelot-3 board" 382 select BOOT_ELF32 383 select DMA_NONCOHERENT 384 select HW_HAS_PCI ··· 397 PMC-Sierra Rm79000 core. 398 399 config MOMENCO_OCELOT_C 400 - bool "Support for Momentum Ocelot-C board" 401 select DMA_NONCOHERENT 402 select HW_HAS_PCI 403 select IRQ_CPU ··· 414 Momentum Computer <http://www.momenco.com/>. 415 416 config MOMENCO_OCELOT_G 417 - bool "Support for Momentum Ocelot-G board" 418 select DMA_NONCOHERENT 419 select HW_HAS_PCI 420 select IRQ_CPU ··· 431 Momentum Computer <http://www.momenco.com/>. 432 433 config MIPS_XXS1500 434 - bool "Support for MyCable XXS1500 board" 435 select DMA_NONCOHERENT 436 select SOC_AU1500 437 select SYS_SUPPORTS_LITTLE_ENDIAN 438 439 config PNX8550_V2PCI 440 - bool "Support for Philips PNX8550 based Viper2-PCI board" 441 select PNX8550 442 select SYS_SUPPORTS_LITTLE_ENDIAN 443 444 config PNX8550_JBS 445 - bool "Support for Philips PNX8550 based JBS board" 446 select PNX8550 447 select SYS_SUPPORTS_LITTLE_ENDIAN 448 449 config DDB5074 450 - bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)" 451 depends on EXPERIMENTAL 452 select DDB5XXX_COMMON 453 select DMA_NONCOHERENT ··· 465 evaluation board. 466 467 config DDB5476 468 - bool "Support for NEC DDB Vrc-5476" 469 select DDB5XXX_COMMON 470 select DMA_NONCOHERENT 471 select HAVE_STD_PC_SERIAL_PORT ··· 486 IDE controller, PS2 keyboard, PS2 mouse, etc. 487 488 config DDB5477 489 - bool "Support for NEC DDB Vrc-5477" 490 select DDB5XXX_COMMON 491 select DMA_NONCOHERENT 492 select HW_HAS_PCI ··· 504 ether port USB, AC97, PCI, etc. 505 506 config MACH_VR41XX 507 - bool "Support for NEC VR4100 series based machines" 508 select SYS_HAS_CPU_VR41XX 509 select SYS_SUPPORTS_32BIT_KERNEL 510 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 511 512 config PMC_YOSEMITE 513 - bool "Support for PMC-Sierra Yosemite eval board" 514 select DMA_COHERENT 515 select HW_HAS_PCI 516 select IRQ_CPU ··· 527 manufactured by PMC-Sierra. 528 529 config QEMU 530 - bool "Support for Qemu" 531 select DMA_COHERENT 532 select GENERIC_ISA_DMA 533 select HAVE_STD_PC_SERIAL_PORT ··· 547 can be found at http://www.linux-mips.org/wiki/Qemu. 548 549 config SGI_IP22 550 - bool "Support for SGI IP22 (Indy/Indigo2)" 551 select ARC 552 select ARC32 553 select BOOT_ELF32 ··· 567 that runs on these, say Y here. 568 569 config SGI_IP27 570 - bool "Support for SGI IP27 (Origin200/2000)" 571 select ARC 572 select ARC64 573 select BOOT_ELF64 ··· 583 here. 584 585 config SGI_IP32 586 - bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" 587 depends on EXPERIMENTAL 588 select ARC 589 select ARC32 ··· 604 If you want this kernel to run on SGI O2 workstation, say Y here. 605 606 config SIBYTE_BIGSUR 607 - bool "Support for Sibyte BCM91480B-BigSur" 608 select BOOT_ELF32 609 select DMA_COHERENT 610 select PCI_DOMAINS ··· 615 select SYS_SUPPORTS_LITTLE_ENDIAN 616 617 config SIBYTE_SWARM 618 - bool "Support for Sibyte BCM91250A-SWARM" 619 select BOOT_ELF32 620 select DMA_COHERENT 621 select SIBYTE_SB1250 ··· 626 select SYS_SUPPORTS_LITTLE_ENDIAN 627 628 config SIBYTE_SENTOSA 629 - bool "Support for Sibyte BCM91250E-Sentosa" 630 depends on EXPERIMENTAL 631 select BOOT_ELF32 632 select DMA_COHERENT ··· 637 select SYS_SUPPORTS_LITTLE_ENDIAN 638 639 config SIBYTE_RHONE 640 - bool "Support for Sibyte BCM91125E-Rhone" 641 depends on EXPERIMENTAL 642 select BOOT_ELF32 643 select DMA_COHERENT ··· 648 select SYS_SUPPORTS_LITTLE_ENDIAN 649 650 config SIBYTE_CARMEL 651 - bool "Support for Sibyte BCM91120x-Carmel" 652 depends on EXPERIMENTAL 653 select BOOT_ELF32 654 select DMA_COHERENT ··· 659 select SYS_SUPPORTS_LITTLE_ENDIAN 660 661 config SIBYTE_PTSWARM 662 - bool "Support for Sibyte BCM91250PT-PTSWARM" 663 depends on EXPERIMENTAL 664 select BOOT_ELF32 665 select DMA_COHERENT ··· 671 select SYS_SUPPORTS_LITTLE_ENDIAN 672 673 config SIBYTE_LITTLESUR 674 - bool "Support for Sibyte BCM91250C2-LittleSur" 675 depends on EXPERIMENTAL 676 select BOOT_ELF32 677 select DMA_COHERENT ··· 683 select SYS_SUPPORTS_LITTLE_ENDIAN 684 685 config SIBYTE_CRHINE 686 - bool "Support for Sibyte BCM91120C-CRhine" 687 depends on EXPERIMENTAL 688 select BOOT_ELF32 689 select DMA_COHERENT ··· 694 select SYS_SUPPORTS_LITTLE_ENDIAN 695 696 config SIBYTE_CRHONE 697 - bool "Support for Sibyte BCM91125C-CRhone" 698 depends on EXPERIMENTAL 699 select BOOT_ELF32 700 select DMA_COHERENT ··· 706 select SYS_SUPPORTS_LITTLE_ENDIAN 707 708 config SNI_RM200_PCI 709 - bool "Support for SNI RM200 PCI" 710 select ARC 711 select ARC32 712 select ARCH_MAY_HAVE_PC_FDC ··· 732 support this machine type. 733 734 config TOSHIBA_JMR3927 735 - bool "Support for Toshiba JMR-TX3927 board" 736 select DMA_NONCOHERENT 737 select HW_HAS_PCI 738 select MIPS_TX3927 ··· 743 select TOSHIBA_BOARDS 744 745 config TOSHIBA_RBTX4927 746 - bool "Support for Toshiba TBTX49[23]7 board" 747 select DMA_NONCOHERENT 748 select HAS_TXX9_SERIAL 749 select HW_HAS_PCI ··· 760 support this machine type 761 762 config TOSHIBA_RBTX4938 763 - bool "Support for Toshiba RBTX4938 board" 764 select HAVE_STD_PC_SERIAL_PORT 765 select DMA_NONCOHERENT 766 select GENERIC_ISA_DMA ··· 1411 1412 config PAGE_SIZE_16KB 1413 bool "16kB" 1414 - depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX 1415 help 1416 Using 16kB page size will result in higher performance kernel at 1417 the price of higher memory consumption. This option is available on 1418 - all non-R3000 family processor. Not that at the time of this 1419 - writing this option is still high experimental; there are also 1420 - issues with compatibility of user applications. 1421 1422 config PAGE_SIZE_64KB 1423 bool "64kB" ··· 1425 Using 64kB page size will result in higher performance kernel at 1426 the price of higher memory consumption. This option is available on 1427 all non-R3000 family processor. Not that at the time of this 1428 - writing this option is still high experimental; there are also 1429 - issues with compatibility of user applications. 1430 1431 endchoice 1432
··· 13 default SGI_IP22 14 15 config MIPS_MTX1 16 + bool "4G Systems MTX-1 board" 17 select DMA_NONCOHERENT 18 select HW_HAS_PCI 19 select SOC_AU1500 ··· 120 select SYS_SUPPORTS_LITTLE_ENDIAN 121 122 config MIPS_COBALT 123 + bool "Cobalt Server" 124 select DMA_NONCOHERENT 125 select HW_HAS_PCI 126 select I8259 ··· 132 select SYS_SUPPORTS_LITTLE_ENDIAN 133 134 config MACH_DECSTATION 135 + bool "DECstations" 136 select BOOT_ELF32 137 select DMA_NONCOHERENT 138 select EARLY_PRINTK ··· 158 otherwise choose R3000. 159 160 config MIPS_EV64120 161 + bool "Galileo EV64120 Evaluation board (EXPERIMENTAL)" 162 depends on EXPERIMENTAL 163 select DMA_NONCOHERENT 164 select HW_HAS_PCI ··· 175 kernel for this platform. 176 177 config MIPS_EV96100 178 + bool "Galileo EV96100 Evaluation board (EXPERIMENTAL)" 179 depends on EXPERIMENTAL 180 select DMA_NONCOHERENT 181 select HW_HAS_PCI ··· 195 here if you wish to build a kernel for this platform. 196 197 config MIPS_IVR 198 + bool "Globespan IVR board" 199 select DMA_NONCOHERENT 200 select HW_HAS_PCI 201 select ITE_BOARD_GEN ··· 211 build a kernel for this platform. 212 213 config MIPS_ITE8172 214 + bool "ITE 8172G board" 215 select DMA_NONCOHERENT 216 select HW_HAS_PCI 217 select ITE_BOARD_GEN ··· 228 a kernel for this platform. 229 230 config MACH_JAZZ 231 + bool "Jazz family of machines" 232 select ARC 233 select ARC32 234 select ARCH_MAY_HAVE_PC_FDC ··· 246 Olivetti M700-10 workstations. 247 248 config LASAT 249 + bool "LASAT Networks platforms" 250 select DMA_NONCOHERENT 251 select HW_HAS_PCI 252 select MIPS_GT64120 ··· 258 select SYS_SUPPORTS_LITTLE_ENDIAN 259 260 config MIPS_ATLAS 261 + bool "MIPS Atlas board" 262 select BOOT_ELF32 263 select DMA_NONCOHERENT 264 select IRQ_CPU ··· 283 board. 284 285 config MIPS_MALTA 286 + bool "MIPS Malta board" 287 select ARCH_MAY_HAVE_PC_FDC 288 select BOOT_ELF32 289 select HAVE_STD_PC_SERIAL_PORT ··· 311 board. 312 313 config MIPS_SEAD 314 + bool "MIPS SEAD board (EXPERIMENTAL)" 315 depends on EXPERIMENTAL 316 select IRQ_CPU 317 select DMA_NONCOHERENT ··· 328 board. 329 330 config MIPS_SIM 331 + bool 'MIPS simulator (MIPSsim)' 332 select DMA_NONCOHERENT 333 select IRQ_CPU 334 select SYS_HAS_CPU_MIPS32_R1 ··· 341 emulator. 342 343 config MOMENCO_JAGUAR_ATX 344 + bool "Momentum Jaguar board" 345 select BOOT_ELF32 346 select DMA_NONCOHERENT 347 select HW_HAS_PCI ··· 361 Momentum Computer <http://www.momenco.com/>. 362 363 config MOMENCO_OCELOT 364 + bool "Momentum Ocelot board" 365 select DMA_NONCOHERENT 366 select HW_HAS_PCI 367 select IRQ_CPU ··· 378 Momentum Computer <http://www.momenco.com/>. 379 380 config MOMENCO_OCELOT_3 381 + bool "Momentum Ocelot-3 board" 382 select BOOT_ELF32 383 select DMA_NONCOHERENT 384 select HW_HAS_PCI ··· 397 PMC-Sierra Rm79000 core. 398 399 config MOMENCO_OCELOT_C 400 + bool "Momentum Ocelot-C board" 401 select DMA_NONCOHERENT 402 select HW_HAS_PCI 403 select IRQ_CPU ··· 414 Momentum Computer <http://www.momenco.com/>. 415 416 config MOMENCO_OCELOT_G 417 + bool "Momentum Ocelot-G board" 418 select DMA_NONCOHERENT 419 select HW_HAS_PCI 420 select IRQ_CPU ··· 431 Momentum Computer <http://www.momenco.com/>. 432 433 config MIPS_XXS1500 434 + bool "MyCable XXS1500 board" 435 select DMA_NONCOHERENT 436 select SOC_AU1500 437 select SYS_SUPPORTS_LITTLE_ENDIAN 438 439 config PNX8550_V2PCI 440 + bool "Philips PNX8550 based Viper2-PCI board" 441 select PNX8550 442 select SYS_SUPPORTS_LITTLE_ENDIAN 443 444 config PNX8550_JBS 445 + bool "Philips PNX8550 based JBS board" 446 select PNX8550 447 select SYS_SUPPORTS_LITTLE_ENDIAN 448 449 config DDB5074 450 + bool "NEC DDB Vrc-5074 (EXPERIMENTAL)" 451 depends on EXPERIMENTAL 452 select DDB5XXX_COMMON 453 select DMA_NONCOHERENT ··· 465 evaluation board. 466 467 config DDB5476 468 + bool "NEC DDB Vrc-5476" 469 select DDB5XXX_COMMON 470 select DMA_NONCOHERENT 471 select HAVE_STD_PC_SERIAL_PORT ··· 486 IDE controller, PS2 keyboard, PS2 mouse, etc. 487 488 config DDB5477 489 + bool "NEC DDB Vrc-5477" 490 select DDB5XXX_COMMON 491 select DMA_NONCOHERENT 492 select HW_HAS_PCI ··· 504 ether port USB, AC97, PCI, etc. 505 506 config MACH_VR41XX 507 + bool "NEC VR41XX-based machines" 508 select SYS_HAS_CPU_VR41XX 509 select SYS_SUPPORTS_32BIT_KERNEL 510 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 511 512 config PMC_YOSEMITE 513 + bool "PMC-Sierra Yosemite eval board" 514 select DMA_COHERENT 515 select HW_HAS_PCI 516 select IRQ_CPU ··· 527 manufactured by PMC-Sierra. 528 529 config QEMU 530 + bool "Qemu" 531 select DMA_COHERENT 532 select GENERIC_ISA_DMA 533 select HAVE_STD_PC_SERIAL_PORT ··· 547 can be found at http://www.linux-mips.org/wiki/Qemu. 548 549 config SGI_IP22 550 + bool "SGI IP22 (Indy/Indigo2)" 551 select ARC 552 select ARC32 553 select BOOT_ELF32 ··· 567 that runs on these, say Y here. 568 569 config SGI_IP27 570 + bool "SGI IP27 (Origin200/2000)" 571 select ARC 572 select ARC64 573 select BOOT_ELF64 ··· 583 here. 584 585 config SGI_IP32 586 + bool "SGI IP32 (O2) (EXPERIMENTAL)" 587 depends on EXPERIMENTAL 588 select ARC 589 select ARC32 ··· 604 If you want this kernel to run on SGI O2 workstation, say Y here. 605 606 config SIBYTE_BIGSUR 607 + bool "Sibyte BCM91480B-BigSur" 608 select BOOT_ELF32 609 select DMA_COHERENT 610 select PCI_DOMAINS ··· 615 select SYS_SUPPORTS_LITTLE_ENDIAN 616 617 config SIBYTE_SWARM 618 + bool "Sibyte BCM91250A-SWARM" 619 select BOOT_ELF32 620 select DMA_COHERENT 621 select SIBYTE_SB1250 ··· 626 select SYS_SUPPORTS_LITTLE_ENDIAN 627 628 config SIBYTE_SENTOSA 629 + bool "Sibyte BCM91250E-Sentosa" 630 depends on EXPERIMENTAL 631 select BOOT_ELF32 632 select DMA_COHERENT ··· 637 select SYS_SUPPORTS_LITTLE_ENDIAN 638 639 config SIBYTE_RHONE 640 + bool "Sibyte BCM91125E-Rhone" 641 depends on EXPERIMENTAL 642 select BOOT_ELF32 643 select DMA_COHERENT ··· 648 select SYS_SUPPORTS_LITTLE_ENDIAN 649 650 config SIBYTE_CARMEL 651 + bool "Sibyte BCM91120x-Carmel" 652 depends on EXPERIMENTAL 653 select BOOT_ELF32 654 select DMA_COHERENT ··· 659 select SYS_SUPPORTS_LITTLE_ENDIAN 660 661 config SIBYTE_PTSWARM 662 + bool "Sibyte BCM91250PT-PTSWARM" 663 depends on EXPERIMENTAL 664 select BOOT_ELF32 665 select DMA_COHERENT ··· 671 select SYS_SUPPORTS_LITTLE_ENDIAN 672 673 config SIBYTE_LITTLESUR 674 + bool "Sibyte BCM91250C2-LittleSur" 675 depends on EXPERIMENTAL 676 select BOOT_ELF32 677 select DMA_COHERENT ··· 683 select SYS_SUPPORTS_LITTLE_ENDIAN 684 685 config SIBYTE_CRHINE 686 + bool "Sibyte BCM91120C-CRhine" 687 depends on EXPERIMENTAL 688 select BOOT_ELF32 689 select DMA_COHERENT ··· 694 select SYS_SUPPORTS_LITTLE_ENDIAN 695 696 config SIBYTE_CRHONE 697 + bool "Sibyte BCM91125C-CRhone" 698 depends on EXPERIMENTAL 699 select BOOT_ELF32 700 select DMA_COHERENT ··· 706 select SYS_SUPPORTS_LITTLE_ENDIAN 707 708 config SNI_RM200_PCI 709 + bool "SNI RM200 PCI" 710 select ARC 711 select ARC32 712 select ARCH_MAY_HAVE_PC_FDC ··· 732 support this machine type. 733 734 config TOSHIBA_JMR3927 735 + bool "Toshiba JMR-TX3927 board" 736 select DMA_NONCOHERENT 737 select HW_HAS_PCI 738 select MIPS_TX3927 ··· 743 select TOSHIBA_BOARDS 744 745 config TOSHIBA_RBTX4927 746 + bool "Toshiba TBTX49[23]7 board" 747 select DMA_NONCOHERENT 748 select HAS_TXX9_SERIAL 749 select HW_HAS_PCI ··· 760 support this machine type 761 762 config TOSHIBA_RBTX4938 763 + bool "Toshiba RBTX4938 board" 764 select HAVE_STD_PC_SERIAL_PORT 765 select DMA_NONCOHERENT 766 select GENERIC_ISA_DMA ··· 1411 1412 config PAGE_SIZE_16KB 1413 bool "16kB" 1414 + depends on !CPU_R3000 && !CPU_TX39XX 1415 help 1416 Using 16kB page size will result in higher performance kernel at 1417 the price of higher memory consumption. This option is available on 1418 + all non-R3000 family processors. Note that you will need a suitable 1419 + Linux distribution to support this. 1420 1421 config PAGE_SIZE_64KB 1422 bool "64kB" ··· 1426 Using 64kB page size will result in higher performance kernel at 1427 the price of higher memory consumption. This option is available on 1428 all non-R3000 family processor. Not that at the time of this 1429 + writing this option is still high experimental. 1430 1431 endchoice 1432
+1
arch/mips/au1000/common/irq.c
··· 68 69 extern void set_debug_traps(void); 70 extern irq_cpustat_t irq_stat [NR_CPUS]; 71 72 static void setup_local_irq(unsigned int irq, int type, int int_req); 73 static unsigned int startup_irq(unsigned int irq);
··· 68 69 extern void set_debug_traps(void); 70 extern irq_cpustat_t irq_stat [NR_CPUS]; 71 + extern void mips_timer_interrupt(struct pt_regs *regs); 72 73 static void setup_local_irq(unsigned int irq, int type, int int_req); 74 static unsigned int startup_irq(unsigned int irq);
+1
arch/mips/au1000/common/time.c
··· 116 117 null: 118 ack_r4ktimer(0); 119 } 120 121 #ifdef CONFIG_PM
··· 116 117 null: 118 ack_r4ktimer(0); 119 + irq_exit(); 120 } 121 122 #ifdef CONFIG_PM
+2 -2
arch/mips/kernel/asm-offsets.c
··· 272 text("/* Linux sigcontext offsets. */"); 273 offset("#define SC_REGS ", struct sigcontext, sc_regs); 274 offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); 275 - offset("#define SC_MDHI ", struct sigcontext, sc_hi); 276 - offset("#define SC_MDLO ", struct sigcontext, sc_lo); 277 offset("#define SC_PC ", struct sigcontext, sc_pc); 278 offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); 279 linefeed;
··· 272 text("/* Linux sigcontext offsets. */"); 273 offset("#define SC_REGS ", struct sigcontext, sc_regs); 274 offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); 275 + offset("#define SC_MDHI ", struct sigcontext, sc_mdhi); 276 + offset("#define SC_MDLO ", struct sigcontext, sc_mdlo); 277 offset("#define SC_PC ", struct sigcontext, sc_pc); 278 offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); 279 linefeed;
+13
arch/mips/kernel/cpu-probe.c
··· 121 case CPU_24K: 122 case CPU_25KF: 123 case CPU_34K: 124 case CPU_PR4450: 125 cpu_wait = r4k_wait; 126 printk(" available.\n"); ··· 433 MIPS_CPU_LLSC; 434 c->tlbsize = 64; 435 break; 436 } 437 } 438 ··· 602 break; 603 case PRID_IMP_34K: 604 c->cputype = CPU_34K; 605 break; 606 } 607 }
··· 121 case CPU_24K: 122 case CPU_25KF: 123 case CPU_34K: 124 + case CPU_74K: 125 case CPU_PR4450: 126 cpu_wait = r4k_wait; 127 printk(" available.\n"); ··· 432 MIPS_CPU_LLSC; 433 c->tlbsize = 64; 434 break; 435 + case PRID_IMP_R14000: 436 + c->cputype = CPU_R14000; 437 + c->isa_level = MIPS_CPU_ISA_IV; 438 + c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 439 + MIPS_CPU_FPU | MIPS_CPU_32FPR | 440 + MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 441 + MIPS_CPU_LLSC; 442 + c->tlbsize = 64; 443 + break; 444 } 445 } 446 ··· 592 break; 593 case PRID_IMP_34K: 594 c->cputype = CPU_34K; 595 + break; 596 + case PRID_IMP_74K: 597 + c->cputype = CPU_74K; 598 break; 599 } 600 }
+1 -1
arch/mips/kernel/entry.S
··· 101 EMT 102 1: 103 mfc0 v1, CP0_TCSTATUS 104 - /* We set IXMT above, XOR should cler it here */ 105 xori v1, v1, TCSTATUS_IXMT 106 or v1, v0, v1 107 mtc0 v1, CP0_TCSTATUS
··· 101 EMT 102 1: 103 mfc0 v1, CP0_TCSTATUS 104 + /* We set IXMT above, XOR should clear it here */ 105 xori v1, v1, TCSTATUS_IXMT 106 or v1, v0, v1 107 mtc0 v1, CP0_TCSTATUS
+5 -3
arch/mips/kernel/gdb-low.S
··· 54 */ 55 mfc0 k0, CP0_CAUSE 56 andi k0, k0, 0x7c 57 - add k1, k1, k0 58 - PTR_L k0, saved_vectors(k1) 59 - jr k0 60 nop 61 1: 62 move k0, sp
··· 54 */ 55 mfc0 k0, CP0_CAUSE 56 andi k0, k0, 0x7c 57 + #ifdef CONFIG_64BIT 58 + dsll k0, k0, 1 59 + #endif 60 + PTR_L k1, saved_vectors(k0) 61 + jr k1 62 nop 63 1: 64 move k0, sp
+2
arch/mips/kernel/proc.c
··· 42 [CPU_R8000] = "R8000", 43 [CPU_R10000] = "R10000", 44 [CPU_R12000] = "R12000", 45 [CPU_R4300] = "R4300", 46 [CPU_R4650] = "R4650", 47 [CPU_R4700] = "R4700", ··· 75 [CPU_24K] = "MIPS 24K", 76 [CPU_25KF] = "MIPS 25Kf", 77 [CPU_34K] = "MIPS 34K", 78 [CPU_VR4111] = "NEC VR4111", 79 [CPU_VR4121] = "NEC VR4121", 80 [CPU_VR4122] = "NEC VR4122",
··· 42 [CPU_R8000] = "R8000", 43 [CPU_R10000] = "R10000", 44 [CPU_R12000] = "R12000", 45 + [CPU_R14000] = "R14000", 46 [CPU_R4300] = "R4300", 47 [CPU_R4650] = "R4650", 48 [CPU_R4700] = "R4700", ··· 74 [CPU_24K] = "MIPS 24K", 75 [CPU_25KF] = "MIPS 25Kf", 76 [CPU_34K] = "MIPS 34K", 77 + [CPU_74K] = "MIPS 74K", 78 [CPU_VR4111] = "NEC VR4111", 79 [CPU_VR4121] = "NEC VR4121", 80 [CPU_VR4122] = "NEC VR4122",
-30
arch/mips/kernel/signal-common.h
··· 31 save_gp_reg(31); 32 #undef save_gp_reg 33 34 - #ifdef CONFIG_32BIT 35 err |= __put_user(regs->hi, &sc->sc_mdhi); 36 err |= __put_user(regs->lo, &sc->sc_mdlo); 37 if (cpu_has_dsp) { ··· 42 err |= __put_user(mflo3(), &sc->sc_lo3); 43 err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp); 44 } 45 - #endif 46 - #ifdef CONFIG_64BIT 47 - err |= __put_user(regs->hi, &sc->sc_hi[0]); 48 - err |= __put_user(regs->lo, &sc->sc_lo[0]); 49 - if (cpu_has_dsp) { 50 - err |= __put_user(mfhi1(), &sc->sc_hi[1]); 51 - err |= __put_user(mflo1(), &sc->sc_lo[1]); 52 - err |= __put_user(mfhi2(), &sc->sc_hi[2]); 53 - err |= __put_user(mflo2(), &sc->sc_lo[2]); 54 - err |= __put_user(mfhi3(), &sc->sc_hi[3]); 55 - err |= __put_user(mflo3(), &sc->sc_lo[3]); 56 - err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp); 57 - } 58 - #endif 59 60 err |= __put_user(!!used_math(), &sc->sc_used_math); 61 ··· 77 current_thread_info()->restart_block.fn = do_no_restart_syscall; 78 79 err |= __get_user(regs->cp0_epc, &sc->sc_pc); 80 - #ifdef CONFIG_32BIT 81 err |= __get_user(regs->hi, &sc->sc_mdhi); 82 err |= __get_user(regs->lo, &sc->sc_mdlo); 83 if (cpu_has_dsp) { ··· 88 err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg); 89 err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); 90 } 91 - #endif 92 - #ifdef CONFIG_64BIT 93 - err |= __get_user(regs->hi, &sc->sc_hi[0]); 94 - err |= __get_user(regs->lo, &sc->sc_lo[0]); 95 - if (cpu_has_dsp) { 96 - err |= __get_user(treg, &sc->sc_hi[1]); mthi1(treg); 97 - err |= __get_user(treg, &sc->sc_lo[1]); mthi1(treg); 98 - err |= __get_user(treg, &sc->sc_hi[2]); mthi2(treg); 99 - err |= __get_user(treg, &sc->sc_lo[2]); mthi2(treg); 100 - err |= __get_user(treg, &sc->sc_hi[3]); mthi3(treg); 101 - err |= __get_user(treg, &sc->sc_lo[3]); mthi3(treg); 102 - err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); 103 - } 104 - #endif 105 106 #define restore_gp_reg(i) do { \ 107 err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \
··· 31 save_gp_reg(31); 32 #undef save_gp_reg 33 34 err |= __put_user(regs->hi, &sc->sc_mdhi); 35 err |= __put_user(regs->lo, &sc->sc_mdlo); 36 if (cpu_has_dsp) { ··· 43 err |= __put_user(mflo3(), &sc->sc_lo3); 44 err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp); 45 } 46 47 err |= __put_user(!!used_math(), &sc->sc_used_math); 48 ··· 92 current_thread_info()->restart_block.fn = do_no_restart_syscall; 93 94 err |= __get_user(regs->cp0_epc, &sc->sc_pc); 95 err |= __get_user(regs->hi, &sc->sc_mdhi); 96 err |= __get_user(regs->lo, &sc->sc_mdlo); 97 if (cpu_has_dsp) { ··· 104 err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg); 105 err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK); 106 } 107 108 #define restore_gp_reg(i) do { \ 109 err |= __get_user(regs->regs[i], &sc->sc_regs[i]); \
-24
arch/mips/kernel/syscall.c
··· 280 char __user *name; 281 282 switch(cmd) { 283 - case SETNAME: { 284 - char nodename[__NEW_UTS_LEN + 1]; 285 - 286 - if (!capable(CAP_SYS_ADMIN)) 287 - return -EPERM; 288 - 289 - name = (char __user *) arg1; 290 - 291 - len = strncpy_from_user(nodename, name, __NEW_UTS_LEN); 292 - if (len < 0) 293 - return -EFAULT; 294 - 295 - down_write(&uts_sem); 296 - strncpy(system_utsname.nodename, nodename, len); 297 - nodename[__NEW_UTS_LEN] = '\0'; 298 - strlcpy(system_utsname.nodename, nodename, 299 - sizeof(system_utsname.nodename)); 300 - up_write(&uts_sem); 301 - return 0; 302 - } 303 - 304 case MIPS_ATOMIC_SET: 305 printk(KERN_CRIT "How did I get here?\n"); 306 return -EINVAL; ··· 292 case FLUSH_CACHE: 293 __flush_cache_all(); 294 return 0; 295 - 296 - case MIPS_RDNVRAM: 297 - return -EIO; 298 } 299 300 return -EINVAL;
··· 280 char __user *name; 281 282 switch(cmd) { 283 case MIPS_ATOMIC_SET: 284 printk(KERN_CRIT "How did I get here?\n"); 285 return -EINVAL; ··· 313 case FLUSH_CACHE: 314 __flush_cache_all(); 315 return 0; 316 } 317 318 return -EINVAL;
+1
arch/mips/kernel/traps.c
··· 902 { 903 switch (current_cpu_data.cputype) { 904 case CPU_24K: 905 case CPU_5KC: 906 write_c0_ecc(0x80000000); 907 back_to_back_c0_hazard();
··· 902 { 903 switch (current_cpu_data.cputype) { 904 case CPU_24K: 905 + case CPU_34K: 906 case CPU_5KC: 907 write_c0_ecc(0x80000000); 908 back_to_back_c0_hazard();
+5 -15
arch/mips/kernel/vmlinux.lds.S
··· 151 152 /* This is the MIPS specific mdebug section. */ 153 .mdebug : { *(.mdebug) } 154 - /* These are needed for ELF backends which have not yet been 155 - converted to the new style linker. */ 156 - .stab 0 : { *(.stab) } 157 - .stabstr 0 : { *(.stabstr) } 158 - /* DWARF debug sections. 159 - Symbols in the .debug DWARF section are relative to the beginning of the 160 - section so we begin .debug at 0. It's not clear yet what needs to happen 161 - for the others. */ 162 - .debug 0 : { *(.debug) } 163 - .debug_srcinfo 0 : { *(.debug_srcinfo) } 164 - .debug_aranges 0 : { *(.debug_aranges) } 165 - .debug_pubnames 0 : { *(.debug_pubnames) } 166 - .debug_sfnames 0 : { *(.debug_sfnames) } 167 - .line 0 : { *(.line) } 168 /* These must appear regardless of . */ 169 .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } 170 .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } 171 - .comment : { *(.comment) } 172 .note : { *(.note) } 173 }
··· 151 152 /* This is the MIPS specific mdebug section. */ 153 .mdebug : { *(.mdebug) } 154 + 155 + STABS_DEBUG 156 + 157 + DWARF_DEBUG 158 + 159 /* These must appear regardless of . */ 160 .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } 161 .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } 162 .note : { *(.note) } 163 }
+35 -9
arch/mips/mm/c-r4k.c
··· 29 #include <asm/war.h> 30 #include <asm/cacheflush.h> /* for run_uncached() */ 31 32 /* 33 * Must die. 34 */ ··· 320 if (!cpu_has_dc_aliases) 321 return; 322 323 - on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); 324 } 325 326 static inline void local_r4k___flush_cache_all(void * args) ··· 335 case CPU_R4400MC: 336 case CPU_R10000: 337 case CPU_R12000: 338 r4k_blast_scache(); 339 } 340 } 341 342 static void r4k___flush_cache_all(void) 343 { 344 - on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); 345 } 346 347 static inline void local_r4k_flush_cache_range(void * args) ··· 363 static void r4k_flush_cache_range(struct vm_area_struct *vma, 364 unsigned long start, unsigned long end) 365 { 366 - on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); 367 } 368 369 static inline void local_r4k_flush_cache_mm(void * args) ··· 392 if (!cpu_has_dc_aliases) 393 return; 394 395 - on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); 396 } 397 398 struct flush_cache_page_args { ··· 483 args.addr = addr; 484 args.pfn = pfn; 485 486 - on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); 487 } 488 489 static inline void local_r4k_flush_data_cache_page(void * addr) ··· 493 494 static void r4k_flush_data_cache_page(unsigned long addr) 495 { 496 - on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); 497 } 498 499 struct flush_icache_range_args { ··· 536 args.start = start; 537 args.end = end; 538 539 - on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); 540 instruction_hazard(); 541 } 542 ··· 612 args.vma = vma; 613 args.page = page; 614 615 - on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); 616 } 617 618 ··· 711 712 static void r4k_flush_cache_sigtramp(unsigned long addr) 713 { 714 - on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); 715 } 716 717 static void r4k_flush_icache_all(void) ··· 834 835 case CPU_R10000: 836 case CPU_R12000: 837 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 838 c->icache.linesz = 64; 839 c->icache.ways = 2; ··· 988 c->dcache.flags |= MIPS_CACHE_PINDEX; 989 case CPU_R10000: 990 case CPU_R12000: 991 case CPU_SB1: 992 break; 993 case CPU_24K: 994 if (!(read_c0_config7() & (1 << 16))) 995 default: 996 if (c->dcache.waysize > PAGE_SIZE) ··· 1116 1117 case CPU_R10000: 1118 case CPU_R12000: 1119 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1120 c->scache.linesz = 64 << ((config >> 13) & 1); 1121 c->scache.ways = 2;
··· 29 #include <asm/war.h> 30 #include <asm/cacheflush.h> /* for run_uncached() */ 31 32 + 33 + /* 34 + * Special Variant of smp_call_function for use by cache functions: 35 + * 36 + * o No return value 37 + * o collapses to normal function call on UP kernels 38 + * o collapses to normal function call on systems with a single shared 39 + * primary cache. 40 + */ 41 + static inline void r4k_on_each_cpu(void (*func) (void *info), void *info, 42 + int retry, int wait) 43 + { 44 + preempt_disable(); 45 + 46 + #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) 47 + smp_call_function(func, info, retry, wait); 48 + #endif 49 + func(info); 50 + preempt_enable(); 51 + } 52 + 53 /* 54 * Must die. 55 */ ··· 299 if (!cpu_has_dc_aliases) 300 return; 301 302 + r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); 303 } 304 305 static inline void local_r4k___flush_cache_all(void * args) ··· 314 case CPU_R4400MC: 315 case CPU_R10000: 316 case CPU_R12000: 317 + case CPU_R14000: 318 r4k_blast_scache(); 319 } 320 } 321 322 static void r4k___flush_cache_all(void) 323 { 324 + r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); 325 } 326 327 static inline void local_r4k_flush_cache_range(void * args) ··· 341 static void r4k_flush_cache_range(struct vm_area_struct *vma, 342 unsigned long start, unsigned long end) 343 { 344 + r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); 345 } 346 347 static inline void local_r4k_flush_cache_mm(void * args) ··· 370 if (!cpu_has_dc_aliases) 371 return; 372 373 + r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); 374 } 375 376 struct flush_cache_page_args { ··· 461 args.addr = addr; 462 args.pfn = pfn; 463 464 + r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); 465 } 466 467 static inline void local_r4k_flush_data_cache_page(void * addr) ··· 471 472 static void r4k_flush_data_cache_page(unsigned long addr) 473 { 474 + r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); 475 } 476 477 struct flush_icache_range_args { ··· 514 args.start = start; 515 args.end = end; 516 517 + r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); 518 instruction_hazard(); 519 } 520 ··· 590 args.vma = vma; 591 args.page = page; 592 593 + r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); 594 } 595 596 ··· 689 690 static void r4k_flush_cache_sigtramp(unsigned long addr) 691 { 692 + r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); 693 } 694 695 static void r4k_flush_icache_all(void) ··· 812 813 case CPU_R10000: 814 case CPU_R12000: 815 + case CPU_R14000: 816 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 817 c->icache.linesz = 64; 818 c->icache.ways = 2; ··· 965 c->dcache.flags |= MIPS_CACHE_PINDEX; 966 case CPU_R10000: 967 case CPU_R12000: 968 + case CPU_R14000: 969 case CPU_SB1: 970 break; 971 case CPU_24K: 972 + case CPU_34K: 973 if (!(read_c0_config7() & (1 << 16))) 974 default: 975 if (c->dcache.waysize > PAGE_SIZE) ··· 1091 1092 case CPU_R10000: 1093 case CPU_R12000: 1094 + case CPU_R14000: 1095 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1096 c->scache.linesz = 64 << ((config >> 13) & 1); 1097 c->scache.ways = 2;
+1
arch/mips/mm/pg-r4k.c
··· 357 358 case CPU_R10000: 359 case CPU_R12000: 360 pref_src_mode = Pref_LoadStreamed; 361 pref_dst_mode = Pref_StoreStreamed; 362 break;
··· 357 358 case CPU_R10000: 359 case CPU_R12000: 360 + case CPU_R14000: 361 pref_src_mode = Pref_LoadStreamed; 362 pref_dst_mode = Pref_StoreStreamed; 363 break;
+2
arch/mips/mm/tlbex.c
··· 875 876 case CPU_R10000: 877 case CPU_R12000: 878 case CPU_4KC: 879 case CPU_SB1: 880 case CPU_SB1A: ··· 907 case CPU_4KEC: 908 case CPU_24K: 909 case CPU_34K: 910 i_ehb(p); 911 tlbw(p); 912 break;
··· 875 876 case CPU_R10000: 877 case CPU_R12000: 878 + case CPU_R14000: 879 case CPU_4KC: 880 case CPU_SB1: 881 case CPU_SB1A: ··· 906 case CPU_4KEC: 907 case CPU_24K: 908 case CPU_34K: 909 + case CPU_74K: 910 i_ehb(p); 911 tlbw(p); 912 break;
+1
arch/mips/oprofile/common.c
··· 80 case CPU_24K: 81 case CPU_25KF: 82 case CPU_34K: 83 case CPU_SB1: 84 case CPU_SB1A: 85 lmodel = &op_model_mipsxx;
··· 80 case CPU_24K: 81 case CPU_25KF: 82 case CPU_34K: 83 + case CPU_74K: 84 case CPU_SB1: 85 case CPU_SB1A: 86 lmodel = &op_model_mipsxx;
+4
arch/mips/oprofile/op_model_mipsxx.c
··· 205 case CPU_34K: 206 op_model_mipsxx.cpu_type = "mips/34K"; 207 break; 208 #endif 209 210 case CPU_5KC:
··· 205 case CPU_34K: 206 op_model_mipsxx.cpu_type = "mips/34K"; 207 break; 208 + 209 + case CPU_74K: 210 + op_model_mipsxx.cpu_type = "mips/74K"; 211 + break; 212 #endif 213 214 case CPU_5KC:
+5 -1
include/asm-mips/cpu.h
··· 51 #define PRID_IMP_R4300 0x0b00 52 #define PRID_IMP_VR41XX 0x0c00 53 #define PRID_IMP_R12000 0x0e00 54 #define PRID_IMP_R8000 0x1000 55 #define PRID_IMP_PR4450 0x1200 56 #define PRID_IMP_R4600 0x2000 ··· 88 #define PRID_IMP_24K 0x9300 89 #define PRID_IMP_34K 0x9500 90 #define PRID_IMP_24KE 0x9600 91 92 /* 93 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE ··· 198 #define CPU_34K 60 199 #define CPU_PR4450 61 200 #define CPU_SB1A 62 201 - #define CPU_LAST 62 202 203 /* 204 * ISA Level encodings
··· 51 #define PRID_IMP_R4300 0x0b00 52 #define PRID_IMP_VR41XX 0x0c00 53 #define PRID_IMP_R12000 0x0e00 54 + #define PRID_IMP_R14000 0x0f00 55 #define PRID_IMP_R8000 0x1000 56 #define PRID_IMP_PR4450 0x1200 57 #define PRID_IMP_R4600 0x2000 ··· 87 #define PRID_IMP_24K 0x9300 88 #define PRID_IMP_34K 0x9500 89 #define PRID_IMP_24KE 0x9600 90 + #define PRID_IMP_74K 0x9700 91 92 /* 93 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE ··· 196 #define CPU_34K 60 197 #define CPU_PR4450 61 198 #define CPU_SB1A 62 199 + #define CPU_74K 63 200 + #define CPU_R14000 64 201 + #define CPU_LAST 64 202 203 /* 204 * ISA Level encodings
+116 -25
include/asm-mips/futex.h
··· 7 #include <linux/futex.h> 8 #include <asm/errno.h> 9 #include <asm/uaccess.h> 10 11 #ifdef CONFIG_SMP 12 #define __FUTEX_SMP_SYNC " sync \n" ··· 17 18 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 19 { \ 20 - __asm__ __volatile__( \ 21 - " .set push \n" \ 22 - " .set noat \n" \ 23 - " .set mips3 \n" \ 24 - "1: ll %1, (%3) # __futex_atomic_op1 \n" \ 25 - " .set mips0 \n" \ 26 - " " insn " \n" \ 27 - " .set mips3 \n" \ 28 - "2: sc $1, (%3) \n" \ 29 - " beqzl $1, 1b \n" \ 30 - __FUTEX_SMP_SYNC \ 31 - "3: \n" \ 32 - " .set pop \n" \ 33 - " .set mips0 \n" \ 34 - " .section .fixup,\"ax\" \n" \ 35 - "4: li %0, %5 \n" \ 36 - " j 2b \n" \ 37 - " .previous \n" \ 38 - " .section __ex_table,\"a\" \n" \ 39 - " "__UA_ADDR "\t1b, 4b \n" \ 40 - " "__UA_ADDR "\t2b, 4b \n" \ 41 - " .previous \n" \ 42 - : "=r" (ret), "=r" (oldval) \ 43 - : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ 44 } 45 46 static inline int ··· 131 static inline int 132 futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) 133 { 134 - return -ENOSYS; 135 } 136 137 #endif
··· 7 #include <linux/futex.h> 8 #include <asm/errno.h> 9 #include <asm/uaccess.h> 10 + #include <asm/war.h> 11 12 #ifdef CONFIG_SMP 13 #define __FUTEX_SMP_SYNC " sync \n" ··· 16 17 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 18 { \ 19 + if (cpu_has_llsc && R10000_LLSC_WAR) { \ 20 + __asm__ __volatile__( \ 21 + " .set push \n" \ 22 + " .set noat \n" \ 23 + " .set mips3 \n" \ 24 + "1: ll %1, (%3) # __futex_atomic_op \n" \ 25 + " .set mips0 \n" \ 26 + " " insn " \n" \ 27 + " .set mips3 \n" \ 28 + "2: sc $1, (%3) \n" \ 29 + " beqzl $1, 1b \n" \ 30 + __FUTEX_SMP_SYNC \ 31 + "3: \n" \ 32 + " .set pop \n" \ 33 + " .set mips0 \n" \ 34 + " .section .fixup,\"ax\" \n" \ 35 + "4: li %0, %5 \n" \ 36 + " j 2b \n" \ 37 + " .previous \n" \ 38 + " .section __ex_table,\"a\" \n" \ 39 + " "__UA_ADDR "\t1b, 4b \n" \ 40 + " "__UA_ADDR "\t2b, 4b \n" \ 41 + " .previous \n" \ 42 + : "=r" (ret), "=r" (oldval) \ 43 + : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ 44 + } else if (cpu_has_llsc) { \ 45 + __asm__ __volatile__( \ 46 + " .set push \n" \ 47 + " .set noat \n" \ 48 + " .set mips3 \n" \ 49 + "1: ll %1, (%3) # __futex_atomic_op \n" \ 50 + " .set mips0 \n" \ 51 + " " insn " \n" \ 52 + " .set mips3 \n" \ 53 + "2: sc $1, (%3) \n" \ 54 + " beqz $1, 1b \n" \ 55 + __FUTEX_SMP_SYNC \ 56 + "3: \n" \ 57 + " .set pop \n" \ 58 + " .set mips0 \n" \ 59 + " .section .fixup,\"ax\" \n" \ 60 + "4: li %0, %5 \n" \ 61 + " j 2b \n" \ 62 + " .previous \n" \ 63 + " .section __ex_table,\"a\" \n" \ 64 + " "__UA_ADDR "\t1b, 4b \n" \ 65 + " "__UA_ADDR "\t2b, 4b \n" \ 66 + " .previous \n" \ 67 + : "=r" (ret), "=r" (oldval) \ 68 + : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ 69 + } else \ 70 + ret = -ENOSYS; \ 71 } 72 73 static inline int ··· 102 static inline int 103 futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) 104 { 105 + int retval; 106 + 107 + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) 108 + return -EFAULT; 109 + 110 + if (cpu_has_llsc && R10000_LLSC_WAR) { 111 + __asm__ __volatile__( 112 + "# futex_atomic_cmpxchg_inatomic \n" 113 + " .set push \n" 114 + " .set noat \n" 115 + " .set mips3 \n" 116 + "1: ll %0, %2 \n" 117 + " bne %0, %z3, 3f \n" 118 + " .set mips0 \n" 119 + " move $1, %z4 \n" 120 + " .set mips3 \n" 121 + "2: sc $1, %1 \n" 122 + " beqzl $1, 1b \n" 123 + __FUTEX_SMP_SYNC 124 + "3: \n" 125 + " .set pop \n" 126 + " .section .fixup,\"ax\" \n" 127 + "4: li %0, %5 \n" 128 + " j 3b \n" 129 + " .previous \n" 130 + " .section __ex_table,\"a\" \n" 131 + " "__UA_ADDR "\t1b, 4b \n" 132 + " "__UA_ADDR "\t2b, 4b \n" 133 + " .previous \n" 134 + : "=&r" (retval), "=R" (*uaddr) 135 + : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) 136 + : "memory"); 137 + } else if (cpu_has_llsc) { 138 + __asm__ __volatile__( 139 + "# futex_atomic_cmpxchg_inatomic \n" 140 + " .set push \n" 141 + " .set noat \n" 142 + " .set mips3 \n" 143 + "1: ll %0, %2 \n" 144 + " bne %0, %z3, 3f \n" 145 + " .set mips0 \n" 146 + " move $1, %z4 \n" 147 + " .set mips3 \n" 148 + "2: sc $1, %1 \n" 149 + " beqz $1, 1b \n" 150 + __FUTEX_SMP_SYNC 151 + "3: \n" 152 + " .set pop \n" 153 + " .section .fixup,\"ax\" \n" 154 + "4: li %0, %5 \n" 155 + " j 3b \n" 156 + " .previous \n" 157 + " .section __ex_table,\"a\" \n" 158 + " "__UA_ADDR "\t1b, 4b \n" 159 + " "__UA_ADDR "\t2b, 4b \n" 160 + " .previous \n" 161 + : "=&r" (retval), "=R" (*uaddr) 162 + : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) 163 + : "memory"); 164 + } else 165 + return -ENOSYS; 166 + 167 + return retval; 168 } 169 170 #endif
+28 -5
include/asm-mips/inst.h
··· 6 * for more details. 7 * 8 * Copyright (C) 1996, 2000 by Ralf Baechle 9 */ 10 #ifndef _ASM_INST_H 11 #define _ASM_INST_H ··· 22 cop0_op, cop1_op, cop2_op, cop1x_op, 23 beql_op, bnel_op, blezl_op, bgtzl_op, 24 daddi_op, daddiu_op, ldl_op, ldr_op, 25 - major_1c_op, jalx_op, major_1e_op, major_1f_op, 26 lb_op, lh_op, lwl_op, lw_op, 27 lbu_op, lhu_op, lwr_op, lwu_op, 28 sb_op, sh_op, swl_op, sw_op, 29 sdl_op, sdr_op, swr_op, cache_op, 30 ll_op, lwc1_op, lwc2_op, pref_op, 31 lld_op, ldc1_op, ldc2_op, ld_op, 32 - sc_op, swc1_op, swc2_op, rdhwr_op, 33 scd_op, sdc1_op, sdc2_op, sd_op 34 }; 35 ··· 38 */ 39 enum spec_op { 40 sll_op, movc_op, srl_op, sra_op, 41 - sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ 42 jr_op, jalr_op, movz_op, movn_op, 43 syscall_op, break_op, spim_op, sync_op, 44 mfhi_op, mthi_op, mflo_op, mtlo_op, ··· 53 teq_op, spec5_unused_op, tne_op, spec6_unused_op, 54 dsll_op, spec7_unused_op, dsrl_op, dsra_op, 55 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op 56 }; 57 58 /* ··· 174 * func field for mad opcodes (MIPS IV). 175 */ 176 enum mad_func { 177 - madd_op = 0x08, msub_op = 0x0a, 178 - nmadd_op = 0x0c, nmsub_op = 0x0e 179 }; 180 181 /*
··· 6 * for more details. 7 * 8 * Copyright (C) 1996, 2000 by Ralf Baechle 9 + * Copyright (C) 2006 by Thiemo Seufer 10 */ 11 #ifndef _ASM_INST_H 12 #define _ASM_INST_H ··· 21 cop0_op, cop1_op, cop2_op, cop1x_op, 22 beql_op, bnel_op, blezl_op, bgtzl_op, 23 daddi_op, daddiu_op, ldl_op, ldr_op, 24 + spec2_op, jalx_op, mdmx_op, spec3_op, 25 lb_op, lh_op, lwl_op, lw_op, 26 lbu_op, lhu_op, lwr_op, lwu_op, 27 sb_op, sh_op, swl_op, sw_op, 28 sdl_op, sdr_op, swr_op, cache_op, 29 ll_op, lwc1_op, lwc2_op, pref_op, 30 lld_op, ldc1_op, ldc2_op, ld_op, 31 + sc_op, swc1_op, swc2_op, major_3b_op, 32 scd_op, sdc1_op, sdc2_op, sd_op 33 }; 34 ··· 37 */ 38 enum spec_op { 39 sll_op, movc_op, srl_op, sra_op, 40 + sllv_op, pmon_op, srlv_op, srav_op, 41 jr_op, jalr_op, movz_op, movn_op, 42 syscall_op, break_op, spim_op, sync_op, 43 mfhi_op, mthi_op, mflo_op, mtlo_op, ··· 52 teq_op, spec5_unused_op, tne_op, spec6_unused_op, 53 dsll_op, spec7_unused_op, dsrl_op, dsra_op, 54 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op 55 + }; 56 + 57 + /* 58 + * func field of spec2 opcode. 59 + */ 60 + enum spec2_op { 61 + madd_op, maddu_op, mul_op, spec2_3_unused_op, 62 + msub_op, msubu_op, /* more unused ops */ 63 + clz_op = 0x20, clo_op, 64 + dclz_op = 0x24, dclo_op, 65 + sdbpp_op = 0x3f 66 + }; 67 + 68 + /* 69 + * func field of spec3 opcode. 70 + */ 71 + enum spec3_op { 72 + ext_op, dextm_op, dextu_op, dext_op, 73 + ins_op, dinsm_op, dinsu_op, dins_op, 74 + bshfl_op = 0x20, 75 + dbshfl_op = 0x24, 76 + rdhwr_op = 0x3f 77 }; 78 79 /* ··· 151 * func field for mad opcodes (MIPS IV). 152 */ 153 enum mad_func { 154 + madd_fp_op = 0x08, msub_fp_op = 0x0a, 155 + nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 156 }; 157 158 /*
+1 -1
include/asm-mips/mipsregs.h
··· 291 #define ST0_DL (_ULCAST_(1) << 24) 292 293 /* 294 - * Enable the MIPS DSP ASE 295 */ 296 #define ST0_MX 0x01000000 297
··· 291 #define ST0_DL (_ULCAST_(1) << 24) 292 293 /* 294 + * Enable the MIPS MDMX and DSP ASEs 295 */ 296 #define ST0_MX 0x01000000 297
+49 -39
include/asm-mips/pgtable.h
··· 82 #define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 83 #define pmd_page_kernel(pmd) pmd_val(pmd) 84 85 - #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) 86 - #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 87 - 88 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 89 static inline void set_pte(pte_t *ptep, pte_t pte) 90 { 91 ptep->pte_high = pte.pte_high; ··· 94 ptep->pte_low = pte.pte_low; 95 //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low); 96 97 - if (pte_val(pte) & _PAGE_GLOBAL) { 98 pte_t *buddy = ptep_buddy(ptep); 99 /* 100 * Make sure the buddy is global too (if it's !none, 101 * it better already be global) 102 */ 103 - if (pte_none(*buddy)) 104 - buddy->pte_low |= _PAGE_GLOBAL; 105 } 106 } 107 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 108 109 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 110 { 111 /* Preserve global status for the pair */ 112 - if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) 113 - set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL)); 114 - else 115 - set_pte_at(mm, addr, ptep, __pte(0)); 116 } 117 #else 118 /* 119 * Certain architectures need to do special things when pte's 120 * within a page table are directly modified. Thus, the following ··· 183 */ 184 static inline int pte_user(pte_t pte) { BUG(); return 0; } 185 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 186 - static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; } 187 - static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; } 188 - static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; } 189 - static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; } 190 - static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; } 191 static inline pte_t pte_wrprotect(pte_t pte) 192 { 193 - (pte).pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); 194 - (pte).pte_high &= ~_PAGE_SILENT_WRITE; 195 return pte; 196 } 197 198 static inline pte_t pte_rdprotect(pte_t pte) 199 { 200 - (pte).pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); 201 - (pte).pte_high &= ~_PAGE_SILENT_READ; 202 return pte; 203 } 204 205 static inline pte_t pte_mkclean(pte_t pte) 206 { 207 - (pte).pte_low &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); 208 - (pte).pte_high &= ~_PAGE_SILENT_WRITE; 209 return pte; 210 } 211 212 static inline pte_t pte_mkold(pte_t pte) 213 { 214 - (pte).pte_low &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); 215 - (pte).pte_high &= ~_PAGE_SILENT_READ; 216 return pte; 217 } 218 219 static inline pte_t pte_mkwrite(pte_t pte) 220 { 221 - (pte).pte_low |= _PAGE_WRITE; 222 - if ((pte).pte_low & _PAGE_MODIFIED) { 223 - (pte).pte_low |= _PAGE_SILENT_WRITE; 224 - (pte).pte_high |= _PAGE_SILENT_WRITE; 225 } 226 return pte; 227 } 228 229 static inline pte_t pte_mkread(pte_t pte) 230 { 231 - (pte).pte_low |= _PAGE_READ; 232 - if ((pte).pte_low & _PAGE_ACCESSED) { 233 - (pte).pte_low |= _PAGE_SILENT_READ; 234 - (pte).pte_high |= _PAGE_SILENT_READ; 235 } 236 return pte; 237 } 238 239 static inline pte_t pte_mkdirty(pte_t pte) 240 { 241 - (pte).pte_low |= _PAGE_MODIFIED; 242 - if ((pte).pte_low & _PAGE_WRITE) { 243 - (pte).pte_low |= _PAGE_SILENT_WRITE; 244 - (pte).pte_high |= _PAGE_SILENT_WRITE; 245 } 246 return pte; 247 } 248 249 static inline pte_t pte_mkyoung(pte_t pte) 250 { 251 - (pte).pte_low |= _PAGE_ACCESSED; 252 - if ((pte).pte_low & _PAGE_READ) 253 - (pte).pte_low |= _PAGE_SILENT_READ; 254 - (pte).pte_high |= _PAGE_SILENT_READ; 255 return pte; 256 } 257 #else
··· 82 #define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 83 #define pmd_page_kernel(pmd) pmd_val(pmd) 84 85 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 86 + 87 + #define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 88 + #define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) 89 + 90 static inline void set_pte(pte_t *ptep, pte_t pte) 91 { 92 ptep->pte_high = pte.pte_high; ··· 93 ptep->pte_low = pte.pte_low; 94 //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low); 95 96 + if (pte.pte_low & _PAGE_GLOBAL) { 97 pte_t *buddy = ptep_buddy(ptep); 98 /* 99 * Make sure the buddy is global too (if it's !none, 100 * it better already be global) 101 */ 102 + if (pte_none(*buddy)) { 103 + buddy->pte_low |= _PAGE_GLOBAL; 104 + buddy->pte_high |= _PAGE_GLOBAL; 105 + } 106 } 107 } 108 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 109 110 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 111 { 112 + pte_t null = __pte(0); 113 + 114 /* Preserve global status for the pair */ 115 + if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL) 116 + null.pte_low = null.pte_high = _PAGE_GLOBAL; 117 + 118 + set_pte_at(mm, addr, ptep, null); 119 } 120 #else 121 + 122 + #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) 123 + #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 124 + 125 /* 126 * Certain architectures need to do special things when pte's 127 * within a page table are directly modified. Thus, the following ··· 174 */ 175 static inline int pte_user(pte_t pte) { BUG(); return 0; } 176 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 177 + static inline int pte_read(pte_t pte) { return pte.pte_low & _PAGE_READ; } 178 + static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } 179 + static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } 180 + static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } 181 + static inline int pte_file(pte_t pte) { return pte.pte_low & _PAGE_FILE; } 182 + 183 static inline pte_t pte_wrprotect(pte_t pte) 184 { 185 + pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); 186 + pte.pte_high &= ~_PAGE_SILENT_WRITE; 187 return pte; 188 } 189 190 static inline pte_t pte_rdprotect(pte_t pte) 191 { 192 + pte.pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); 193 + pte.pte_high &= ~_PAGE_SILENT_READ; 194 return pte; 195 } 196 197 static inline pte_t pte_mkclean(pte_t pte) 198 { 199 + pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); 200 + pte.pte_high &= ~_PAGE_SILENT_WRITE; 201 return pte; 202 } 203 204 static inline pte_t pte_mkold(pte_t pte) 205 { 206 + pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); 207 + pte.pte_high &= ~_PAGE_SILENT_READ; 208 return pte; 209 } 210 211 static inline pte_t pte_mkwrite(pte_t pte) 212 { 213 + pte.pte_low |= _PAGE_WRITE; 214 + if (pte.pte_low & _PAGE_MODIFIED) { 215 + pte.pte_low |= _PAGE_SILENT_WRITE; 216 + pte.pte_high |= _PAGE_SILENT_WRITE; 217 } 218 return pte; 219 } 220 221 static inline pte_t pte_mkread(pte_t pte) 222 { 223 + pte.pte_low |= _PAGE_READ; 224 + if (pte.pte_low & _PAGE_ACCESSED) { 225 + pte.pte_low |= _PAGE_SILENT_READ; 226 + pte.pte_high |= _PAGE_SILENT_READ; 227 } 228 return pte; 229 } 230 231 static inline pte_t pte_mkdirty(pte_t pte) 232 { 233 + pte.pte_low |= _PAGE_MODIFIED; 234 + if (pte.pte_low & _PAGE_WRITE) { 235 + pte.pte_low |= _PAGE_SILENT_WRITE; 236 + pte.pte_high |= _PAGE_SILENT_WRITE; 237 } 238 return pte; 239 } 240 241 static inline pte_t pte_mkyoung(pte_t pte) 242 { 243 + pte.pte_low |= _PAGE_ACCESSED; 244 + if (pte.pte_low & _PAGE_READ) 245 + pte.pte_low |= _PAGE_SILENT_READ; 246 + pte.pte_high |= _PAGE_SILENT_READ; 247 return pte; 248 } 249 #else
+8 -2
include/asm-mips/sigcontext.h
··· 55 struct sigcontext { 56 unsigned long sc_regs[32]; 57 unsigned long sc_fpregs[32]; 58 - unsigned long sc_hi[4]; 59 - unsigned long sc_lo[4]; 60 unsigned long sc_pc; 61 unsigned int sc_fpc_csr; 62 unsigned int sc_used_math;
··· 55 struct sigcontext { 56 unsigned long sc_regs[32]; 57 unsigned long sc_fpregs[32]; 58 + unsigned long sc_mdhi; 59 + unsigned long sc_hi1; 60 + unsigned long sc_hi2; 61 + unsigned long sc_hi3; 62 + unsigned long sc_mdlo; 63 + unsigned long sc_lo1; 64 + unsigned long sc_lo2; 65 + unsigned long sc_lo3; 66 unsigned long sc_pc; 67 unsigned int sc_fpc_csr; 68 unsigned int sc_used_math;