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kernel os linux

mtd: nand: Add an option to maximize the ECC strength

The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.

In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).

Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>

+13
+9
Documentation/devicetree/bindings/mtd/nand.txt
··· 35 35 - nand-ecc-step-size: integer representing the number of data bytes 36 36 that are covered by a single ECC step. 37 37 38 + - nand-ecc-maximize: boolean used to specify that you want to maximize ECC 39 + strength. The maximum ECC strength is both controller and 40 + chip dependent. The controller side has to select the ECC 41 + config providing the best strength and taking the OOB area 42 + size constraint into account. 43 + This is particularly useful when only the in-band area is 44 + used by the upper layers, and you want to make your NAND 45 + as reliable as possible. 46 + 38 47 The ECC strength and ECC step size properties define the correction capability 39 48 of a controller. Together, they say a controller can correct "{strength} bit 40 49 errors per {size} bytes".
+3
drivers/mtd/nand/nand_base.c
··· 4272 4272 if (ecc_step > 0) 4273 4273 chip->ecc.size = ecc_step; 4274 4274 4275 + if (of_property_read_bool(dn, "nand-ecc-maximize")) 4276 + chip->ecc.options |= NAND_ECC_MAXIMIZE; 4277 + 4275 4278 return 0; 4276 4279 } 4277 4280
+1
include/linux/mtd/nand.h
··· 141 141 * pages and you want to rely on the default implementation. 142 142 */ 143 143 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 144 + #define NAND_ECC_MAXIMIZE BIT(1) 144 145 145 146 /* Bit mask for flags passed to do_nand_read_ecc */ 146 147 #define NAND_GET_DEVICE 0x80