Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc

tjh.dev / kernel

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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc

Pull sparc fixes from David Miller:

1) Fix panics with SR-IOV, from Babu Moger.

2) Wire up preadv2/pwritev2.

3) Allow proper auto-loading of VIO devices, from John Paul Adrian
Glaubitz.

4) Recognize Sonoma cpus, from Khalid Aziz.

5) Fix bootup regressions caused by syscall trace fixes made recently.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
sparc64: Fix bootup regressions on some Kconfig combinations.
sparc64: recognize and support Sonoma CPU type
sparc: Implement and wire up vio_hotplug for vio.
sparc: Implement and wire up modalias_show for vio.
sparc/pci: Refactor dev_archdata initialization into pci_init_dev_archdata
sparc/defconfigs: Remove CONFIG_IPV6_PRIVACY
sparc: Write up preadv2/pwritev2 syscalls.
sparc/PCI: Fix for panic while enabling SR-IOV

Linus Torvalds 10 years ago ba22906a 04974df8

+119 -68

20 changed files

expand all collapse all

arch

sparc

configs

sparc32_defconfig

sparc64_defconfig

include

asm

spitfire.h

uapi

asm

unistd.h

kernel

cherrs.S

cpu.c

cpumap.c

fpu_traps.S

head_64.S

misctrap.S

pci.c

setup_64.c

spiterrs.S

systbls_32.S

systbls_64.S

utrap.S

vio.c

vmlinux.lds.S

winfixup.S

init_64.c

-1

arch/sparc/configs/sparc32_defconfig

reviewed

··· 24 24 CONFIG_INET_ESP=y 25 25 CONFIG_INET_IPCOMP=y 26 26 # CONFIG_INET_LRO is not set 27 27 - CONFIG_IPV6_PRIVACY=y 28 27 CONFIG_INET6_AH=m 29 28 CONFIG_INET6_ESP=m 30 29 CONFIG_INET6_IPCOMP=m

-1

arch/sparc/configs/sparc64_defconfig

reviewed

··· 48 48 CONFIG_INET_AH=y 49 49 CONFIG_INET_ESP=y 50 50 CONFIG_INET_IPCOMP=y 51 51 - CONFIG_IPV6_PRIVACY=y 52 51 CONFIG_IPV6_ROUTER_PREF=y 53 52 CONFIG_IPV6_ROUTE_INFO=y 54 53 CONFIG_IPV6_OPTIMISTIC_DAD=y

arch/sparc/include/asm/spitfire.h

reviewed

··· 48 48 #define SUN4V_CHIP_SPARC_M6 0x06 49 49 #define SUN4V_CHIP_SPARC_M7 0x07 50 50 #define SUN4V_CHIP_SPARC64X 0x8a 51 51 + #define SUN4V_CHIP_SPARC_SN 0x8b 51 52 #define SUN4V_CHIP_UNKNOWN 0xff 52 53 53 54 #ifndef __ASSEMBLY__

+3 -1

arch/sparc/include/uapi/asm/unistd.h

reviewed

··· 423 423 #define __NR_setsockopt 355 424 424 #define __NR_mlock2 356 425 425 #define __NR_copy_file_range 357 426 426 + #define __NR_preadv2 358 427 427 + #define __NR_pwritev2 359 426 428 427 427 - #define NR_syscalls 358 429 429 + #define NR_syscalls 360 428 430 429 431 /* Bitmask values returned from kern_features system call. */ 430 432 #define KERN_FEATURE_MIXED_MODE_STACK 0x00000001

+5 -9

arch/sparc/kernel/cherrs.S

reviewed

··· 214 214 subcc %g1, %g2, %g1 ! Next cacheline 215 215 bge,pt %icc, 1b 216 216 nop 217 217 - ba,pt %xcc, dcpe_icpe_tl1_common 218 218 - nop 217 217 + ba,a,pt %xcc, dcpe_icpe_tl1_common 219 218 220 219 do_dcpe_tl1_fatal: 221 220 sethi %hi(1f), %g7 ··· 223 224 mov 0x2, %o0 224 225 call cheetah_plus_parity_error 225 226 add %sp, PTREGS_OFF, %o1 226 226 - ba,pt %xcc, rtrap 227 227 - nop 227 227 + ba,a,pt %xcc, rtrap 228 228 .size do_dcpe_tl1,.-do_dcpe_tl1 229 229 230 230 .globl do_icpe_tl1 ··· 257 259 subcc %g1, %g2, %g1 258 260 bge,pt %icc, 1b 259 261 nop 260 260 - ba,pt %xcc, dcpe_icpe_tl1_common 261 261 - nop 262 262 + ba,a,pt %xcc, dcpe_icpe_tl1_common 262 263 263 264 do_icpe_tl1_fatal: 264 265 sethi %hi(1f), %g7 ··· 266 269 mov 0x3, %o0 267 270 call cheetah_plus_parity_error 268 271 add %sp, PTREGS_OFF, %o1 269 269 - ba,pt %xcc, rtrap 270 270 - nop 272 272 + ba,a,pt %xcc, rtrap 271 273 .size do_icpe_tl1,.-do_icpe_tl1 272 274 273 275 .type dcpe_icpe_tl1_common,#function ··· 452 456 cmp %g2, 0x63 453 457 be c_cee 454 458 nop 455 455 - ba,pt %xcc, c_deferred 459 459 + ba,a,pt %xcc, c_deferred 456 460 .size __cheetah_log_error,.-__cheetah_log_error 457 461 458 462 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc

arch/sparc/kernel/cpu.c

reviewed

··· 506 506 sparc_pmu_type = "sparc-m7"; 507 507 break; 508 508 509 509 + case SUN4V_CHIP_SPARC_SN: 510 510 + sparc_cpu_type = "SPARC-SN"; 511 511 + sparc_fpu_type = "SPARC-SN integrated FPU"; 512 512 + sparc_pmu_type = "sparc-sn"; 513 513 + break; 514 514 + 509 515 case SUN4V_CHIP_SPARC64X: 510 516 sparc_cpu_type = "SPARC64-X"; 511 517 sparc_fpu_type = "SPARC64-X integrated FPU";

arch/sparc/kernel/cpumap.c

reviewed

··· 328 328 case SUN4V_CHIP_NIAGARA5: 329 329 case SUN4V_CHIP_SPARC_M6: 330 330 case SUN4V_CHIP_SPARC_M7: 331 331 + case SUN4V_CHIP_SPARC_SN: 331 332 case SUN4V_CHIP_SPARC64X: 332 333 rover_inc_table = niagara_iterate_method; 333 334 break;

+5 -6

arch/sparc/kernel/fpu_traps.S

reviewed

··· 100 100 fmuld %f0, %f2, %f26 101 101 faddd %f0, %f2, %f28 102 102 fmuld %f0, %f2, %f30 103 103 - b,pt %xcc, fpdis_exit 104 104 - nop 103 103 + ba,a,pt %xcc, fpdis_exit 104 104 + 105 105 2: andcc %g5, FPRS_DU, %g0 106 106 bne,pt %icc, 3f 107 107 fzero %f32 ··· 144 144 fmuld %f32, %f34, %f58 145 145 faddd %f32, %f34, %f60 146 146 fmuld %f32, %f34, %f62 147 147 - ba,pt %xcc, fpdis_exit 148 148 - nop 147 147 + ba,a,pt %xcc, fpdis_exit 148 148 + 149 149 3: mov SECONDARY_CONTEXT, %g3 150 150 add %g6, TI_FPREGS, %g1 151 151 ··· 197 197 fp_other_bounce: 198 198 call do_fpother 199 199 add %sp, PTREGS_OFF, %o0 200 200 - ba,pt %xcc, rtrap 201 201 - nop 200 200 + ba,a,pt %xcc, rtrap 202 201 .size fp_other_bounce,.-fp_other_bounce 203 202 204 203 .align 32

+16 -16

arch/sparc/kernel/head_64.S

reviewed

··· 414 414 cmp %g2, 'T' 415 415 be,pt %xcc, 70f 416 416 cmp %g2, 'M' 417 417 + be,pt %xcc, 70f 418 418 + cmp %g2, 'S' 417 419 bne,pn %xcc, 49f 418 420 nop 419 421 ··· 435 433 cmp %g2, '7' 436 434 be,pt %xcc, 5f 437 435 mov SUN4V_CHIP_SPARC_M7, %g4 436 436 + cmp %g2, 'N' 437 437 + be,pt %xcc, 5f 438 438 + mov SUN4V_CHIP_SPARC_SN, %g4 438 439 ba,pt %xcc, 49f 439 440 nop 440 441 ··· 466 461 subcc %g3, 1, %g3 467 462 bne,pt %xcc, 41b 468 463 add %g1, 1, %g1 469 469 - mov SUN4V_CHIP_SPARC64X, %g4 470 464 ba,pt %xcc, 5f 471 471 - nop 465 465 + mov SUN4V_CHIP_SPARC64X, %g4 472 466 473 467 49: 474 468 mov SUN4V_CHIP_UNKNOWN, %g4 ··· 552 548 stxa %g0, [%g7] ASI_DMMU 553 549 membar #Sync 554 550 555 555 - ba,pt %xcc, sun4u_continue 556 556 - nop 551 551 + ba,a,pt %xcc, sun4u_continue 557 552 558 553 sun4v_init: 559 554 /* Set ctx 0 */ ··· 563 560 mov SECONDARY_CONTEXT, %g7 564 561 stxa %g0, [%g7] ASI_MMU 565 562 membar #Sync 566 566 - ba,pt %xcc, niagara_tlb_fixup 567 567 - nop 563 563 + ba,a,pt %xcc, niagara_tlb_fixup 568 564 569 565 sun4u_continue: 570 566 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup) 571 567 572 572 - ba,pt %xcc, spitfire_tlb_fixup 573 573 - nop 568 568 + ba,a,pt %xcc, spitfire_tlb_fixup 574 569 575 570 niagara_tlb_fixup: 576 571 mov 3, %g2 /* Set TLB type to hypervisor. */ ··· 596 595 be,pt %xcc, niagara4_patch 597 596 nop 598 597 cmp %g1, SUN4V_CHIP_SPARC_M7 598 598 + be,pt %xcc, niagara4_patch 599 599 + nop 600 600 + cmp %g1, SUN4V_CHIP_SPARC_SN 599 601 be,pt %xcc, niagara4_patch 600 602 nop 601 603 ··· 643 639 call hypervisor_patch_cachetlbops 644 640 nop 645 641 646 646 - ba,pt %xcc, tlb_fixup_done 647 647 - nop 642 642 + ba,a,pt %xcc, tlb_fixup_done 648 643 649 644 cheetah_tlb_fixup: 650 645 mov 2, %g2 /* Set TLB type to cheetah+. */ ··· 662 659 call cheetah_patch_cachetlbops 663 660 nop 664 661 665 665 - ba,pt %xcc, tlb_fixup_done 666 666 - nop 662 662 + ba,a,pt %xcc, tlb_fixup_done 667 663 668 664 spitfire_tlb_fixup: 669 665 /* Set TLB type to spitfire. */ ··· 776 774 call %o1 777 775 add %sp, (2047 + 128), %o0 778 776 779 779 - ba,pt %xcc, 2f 780 780 - nop 777 777 + ba,a,pt %xcc, 2f 781 778 782 779 1: sethi %hi(sparc64_ttable_tl0), %o0 783 780 set prom_set_trap_table_name, %g2 ··· 815 814 816 815 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f) 817 816 818 818 - ba,pt %xcc, 2f 819 819 - nop 817 817 + ba,a,pt %xcc, 2f 820 818 821 819 /* Disable STICK_INT interrupts. */ 822 820 1:

+4 -8

arch/sparc/kernel/misctrap.S

reviewed

··· 18 18 109: or %g7, %lo(109b), %g7 19 19 call do_privact 20 20 add %sp, PTREGS_OFF, %o0 21 21 - ba,pt %xcc, rtrap 22 22 - nop 21 21 + ba,a,pt %xcc, rtrap 23 22 .size __do_privact,.-__do_privact 24 23 25 24 .type do_mna,#function ··· 45 46 mov %l5, %o2 46 47 call mem_address_unaligned 47 48 add %sp, PTREGS_OFF, %o0 48 48 - ba,pt %xcc, rtrap 49 49 - nop 49 49 + ba,a,pt %xcc, rtrap 50 50 .size do_mna,.-do_mna 51 51 52 52 .type do_lddfmna,#function ··· 63 65 mov %l5, %o2 64 66 call handle_lddfmna 65 67 add %sp, PTREGS_OFF, %o0 66 66 - ba,pt %xcc, rtrap 67 67 - nop 68 68 + ba,a,pt %xcc, rtrap 68 69 .size do_lddfmna,.-do_lddfmna 69 70 70 71 .type do_stdfmna,#function ··· 81 84 mov %l5, %o2 82 85 call handle_stdfmna 83 86 add %sp, PTREGS_OFF, %o0 84 84 - ba,pt %xcc, rtrap 85 85 - nop 87 87 + ba,a,pt %xcc, rtrap 86 88 .size do_stdfmna,.-do_stdfmna 87 89 88 90 .type breakpoint_trap,#function

+36 -6

arch/sparc/kernel/pci.c

reviewed

··· 245 245 } 246 246 } 247 247 248 248 + static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu, 249 249 + void *stc, void *host_controller, 250 250 + struct platform_device *op, 251 251 + int numa_node) 252 252 + { 253 253 + sd->iommu = iommu; 254 254 + sd->stc = stc; 255 255 + sd->host_controller = host_controller; 256 256 + sd->op = op; 257 257 + sd->numa_node = numa_node; 258 258 + } 259 259 + 248 260 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, 249 261 struct device_node *node, 250 262 struct pci_bus *bus, int devfn) ··· 271 259 if (!dev) 272 260 return NULL; 273 261 262 262 + op = of_find_device_by_node(node); 274 263 sd = &dev->dev.archdata; 275 275 - sd->iommu = pbm->iommu; 276 276 - sd->stc = &pbm->stc; 277 277 - sd->host_controller = pbm; 278 278 - sd->op = op = of_find_device_by_node(node); 279 279 - sd->numa_node = pbm->numa_node; 280 280 - 264 264 + pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op, 265 265 + pbm->numa_node); 281 266 sd = &op->dev.archdata; 282 267 sd->iommu = pbm->iommu; 283 268 sd->stc = &pbm->stc; ··· 1002 993 { 1003 994 /* No special bus mastering setup handling */ 1004 995 } 996 996 + 997 997 + #ifdef CONFIG_PCI_IOV 998 998 + int pcibios_add_device(struct pci_dev *dev) 999 999 + { 1000 1000 + struct pci_dev *pdev; 1001 1001 + 1002 1002 + /* Add sriov arch specific initialization here. 1003 1003 + * Copy dev_archdata from PF to VF 1004 1004 + */ 1005 1005 + if (dev->is_virtfn) { 1006 1006 + struct dev_archdata *psd; 1007 1007 + 1008 1008 + pdev = dev->physfn; 1009 1009 + psd = &pdev->dev.archdata; 1010 1010 + pci_init_dev_archdata(&dev->dev.archdata, psd->iommu, 1011 1011 + psd->stc, psd->host_controller, NULL, 1012 1012 + psd->numa_node); 1013 1013 + } 1014 1014 + return 0; 1015 1015 + } 1016 1016 + #endif /* CONFIG_PCI_IOV */ 1005 1017 1006 1018 static int __init pcibios_init(void) 1007 1019 {

+6 -1

arch/sparc/kernel/setup_64.c

reviewed

··· 285 285 286 286 sun4v_patch_2insn_range(&__sun4v_2insn_patch, 287 287 &__sun4v_2insn_patch_end); 288 288 - if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7) 288 288 + if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 289 289 + sun4v_chip_type == SUN4V_CHIP_SPARC_SN) 289 290 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch, 290 291 &__sun_m7_2insn_patch_end); 291 292 ··· 525 524 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 526 525 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 527 526 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 527 527 + sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 528 528 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 529 529 cap |= HWCAP_SPARC_BLKINIT; 530 530 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || ··· 534 532 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 535 533 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 536 534 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 535 535 + sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 537 536 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 538 537 cap |= HWCAP_SPARC_N2; 539 538 } ··· 564 561 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 565 562 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 566 563 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 564 564 + sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 567 565 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 568 566 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | 569 567 AV_SPARC_ASI_BLK_INIT | ··· 574 570 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 575 571 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 576 572 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 573 573 + sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 577 574 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 578 575 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | 579 576 AV_SPARC_FMAF);

+6 -12

arch/sparc/kernel/spiterrs.S

reviewed

··· 85 85 ba,pt %xcc, etraptl1 86 86 rd %pc, %g7 87 87 88 88 - ba,pt %xcc, 2f 89 89 - nop 88 88 + ba,a,pt %xcc, 2f 90 89 91 90 1: ba,pt %xcc, etrap_irq 92 91 rd %pc, %g7 ··· 99 100 mov %l5, %o2 100 101 call spitfire_access_error 101 102 add %sp, PTREGS_OFF, %o0 102 102 - ba,pt %xcc, rtrap 103 103 - nop 103 103 + ba,a,pt %xcc, rtrap 104 104 .size __spitfire_access_error,.-__spitfire_access_error 105 105 106 106 /* This is the trap handler entry point for ECC correctable ··· 177 179 mov %l5, %o2 178 180 call spitfire_data_access_exception_tl1 179 181 add %sp, PTREGS_OFF, %o0 180 180 - ba,pt %xcc, rtrap 181 181 - nop 182 182 + ba,a,pt %xcc, rtrap 182 183 .size __spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1 183 184 184 185 .type __spitfire_data_access_exception,#function ··· 197 200 mov %l5, %o2 198 201 call spitfire_data_access_exception 199 202 add %sp, PTREGS_OFF, %o0 200 200 - ba,pt %xcc, rtrap 201 201 - nop 203 203 + ba,a,pt %xcc, rtrap 202 204 .size __spitfire_data_access_exception,.-__spitfire_data_access_exception 203 205 204 206 .type __spitfire_insn_access_exception_tl1,#function ··· 216 220 mov %l5, %o2 217 221 call spitfire_insn_access_exception_tl1 218 222 add %sp, PTREGS_OFF, %o0 219 219 - ba,pt %xcc, rtrap 220 220 - nop 223 223 + ba,a,pt %xcc, rtrap 221 224 .size __spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1 222 225 223 226 .type __spitfire_insn_access_exception,#function ··· 235 240 mov %l5, %o2 236 241 call spitfire_insn_access_exception 237 242 add %sp, PTREGS_OFF, %o0 238 238 - ba,pt %xcc, rtrap 239 239 - nop 243 243 + ba,a,pt %xcc, rtrap 240 244 .size __spitfire_insn_access_exception,.-__spitfire_insn_access_exception

+1 -1

arch/sparc/kernel/systbls_32.S

reviewed

··· 88 88 /*340*/ .long sys_ni_syscall, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr 89 89 /*345*/ .long sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf 90 90 /*350*/ .long sys_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen 91 91 - /*355*/ .long sys_setsockopt, sys_mlock2, sys_copy_file_range 91 91 + /*355*/ .long sys_setsockopt, sys_mlock2, sys_copy_file_range, sys_preadv2, sys_pwritev2

+2 -2

arch/sparc/kernel/systbls_64.S

reviewed

··· 89 89 /*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr 90 90 .word sys32_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf 91 91 /*350*/ .word sys32_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen 92 92 - .word compat_sys_setsockopt, sys_mlock2, sys_copy_file_range 92 92 + .word compat_sys_setsockopt, sys_mlock2, sys_copy_file_range, compat_sys_preadv2, compat_sys_pwritev2 93 93 94 94 #endif /* CONFIG_COMPAT */ 95 95 ··· 170 170 /*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr 171 171 .word sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf 172 172 /*350*/ .word sys64_execveat, sys_membarrier, sys_userfaultfd, sys_bind, sys_listen 173 173 - .word sys_setsockopt, sys_mlock2, sys_copy_file_range 173 173 + .word sys_setsockopt, sys_mlock2, sys_copy_file_range, sys_preadv2, sys_pwritev2

+1 -2

arch/sparc/kernel/utrap.S

reviewed

··· 11 11 mov %l4, %o1 12 12 call bad_trap 13 13 add %sp, PTREGS_OFF, %o0 14 14 - ba,pt %xcc, rtrap 15 15 - nop 14 14 + ba,a,pt %xcc, rtrap 16 15 17 16 invoke_utrap: 18 17 sllx %g3, 3, %g3

+18

arch/sparc/kernel/vio.c

reviewed

··· 45 45 return NULL; 46 46 } 47 47 48 48 + static int vio_hotplug(struct device *dev, struct kobj_uevent_env *env) 49 49 + { 50 50 + const struct vio_dev *vio_dev = to_vio_dev(dev); 51 51 + 52 52 + add_uevent_var(env, "MODALIAS=vio:T%sS%s", vio_dev->type, vio_dev->compat); 53 53 + return 0; 54 54 + } 55 55 + 48 56 static int vio_bus_match(struct device *dev, struct device_driver *drv) 49 57 { 50 58 struct vio_dev *vio_dev = to_vio_dev(dev); ··· 113 105 return sprintf(buf, "%s\n", vdev->type); 114 106 } 115 107 108 108 + static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, 109 109 + char *buf) 110 110 + { 111 111 + const struct vio_dev *vdev = to_vio_dev(dev); 112 112 + 113 113 + return sprintf(buf, "vio:T%sS%s\n", vdev->type, vdev->compat); 114 114 + } 115 115 + 116 116 static struct device_attribute vio_dev_attrs[] = { 117 117 __ATTR_RO(devspec), 118 118 __ATTR_RO(type), 119 119 + __ATTR_RO(modalias), 119 120 __ATTR_NULL 120 121 }; 121 122 122 123 static struct bus_type vio_bus_type = { 123 124 .name = "vio", 124 125 .dev_attrs = vio_dev_attrs, 126 126 + .uevent = vio_hotplug, 125 127 .match = vio_bus_match, 126 128 .probe = vio_device_probe, 127 129 .remove = vio_device_remove,

arch/sparc/kernel/vmlinux.lds.S

reviewed

··· 33 33 jiffies = jiffies_64; 34 34 #endif 35 35 36 36 + #ifdef CONFIG_SPARC64 37 37 + ASSERT((swapper_tsb == 0x0000000000408000), "Error: sparc64 early assembler too large") 38 38 + #endif 39 39 + 36 40 SECTIONS 37 41 { 38 42 #ifdef CONFIG_SPARC64

+1 -2

arch/sparc/kernel/winfixup.S

reviewed

··· 32 32 rd %pc, %g7 33 33 call do_sparc64_fault 34 34 add %sp, PTREGS_OFF, %o0 35 35 - ba,pt %xcc, rtrap 36 36 - nop 35 35 + ba,a,pt %xcc, rtrap 37 36 38 37 /* Be very careful about usage of the trap globals here. 39 38 * You cannot touch %g5 as that has the fault information.

arch/sparc/mm/init_64.c

reviewed

··· 1769 1769 max_phys_bits = 47; 1770 1770 break; 1771 1771 case SUN4V_CHIP_SPARC_M7: 1772 1772 + case SUN4V_CHIP_SPARC_SN: 1772 1773 default: 1773 1774 /* M7 and later support 52-bit virtual addresses. */ 1774 1775 sparc64_va_hole_top = 0xfff8000000000000UL; ··· 1987 1986 */ 1988 1987 switch (sun4v_chip_type) { 1989 1988 case SUN4V_CHIP_SPARC_M7: 1989 1989 + case SUN4V_CHIP_SPARC_SN: 1990 1990 pagecv_flag = 0x00; 1991 1991 break; 1992 1992 default: ··· 2140 2138 */ 2141 2139 switch (sun4v_chip_type) { 2142 2140 case SUN4V_CHIP_SPARC_M7: 2141 2141 + case SUN4V_CHIP_SPARC_SN: 2143 2142 page_cache4v_flag = _PAGE_CP_4V; 2144 2143 break; 2145 2144 default: