tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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regulator: mt6358: Remove shift fields from struct mt6358_regulator_info

The shift setting can be calculated via the corresponding mask field,
so remove these shift fields.

The usage of da_vsel_mask is different from other mask defines because
current code does shift regval before mask with the da_vsel_mask.
Do proper shit to da_vsel_mask setting so we can calculate the shift.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Link: https://lore.kernel.org/r/20210629130503.2183574-1-axel.lin@ingics.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Axel Lin and committed by
Mark Brown b99b7b79 3cb5992c

+40 -47
+40 -47
drivers/regulator/mt6358-regulator.c
··· 28 28 u32 qi; 29 29 const u32 *index_table; 30 30 unsigned int n_table; 31 - u32 vsel_shift; 32 31 u32 da_vsel_reg; 33 32 u32 da_vsel_mask; 34 - u32 da_vsel_shift; 35 33 u32 modeset_reg; 36 34 u32 modeset_mask; 37 - u32 modeset_shift; 38 35 }; 39 36 40 37 #define MT6358_BUCK(match, vreg, min, max, step, \ 41 38 volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \ 42 - _da_vsel_shift, _modeset_reg, _modeset_shift) \ 39 + _modeset_reg, _modeset_shift) \ 43 40 [MT6358_ID_##vreg] = { \ 44 41 .desc = { \ 45 42 .name = #vreg, \ ··· 58 61 .qi = BIT(0), \ 59 62 .da_vsel_reg = _da_vsel_reg, \ 60 63 .da_vsel_mask = _da_vsel_mask, \ 61 - .da_vsel_shift = _da_vsel_shift, \ 62 64 .modeset_reg = _modeset_reg, \ 63 65 .modeset_mask = BIT(_modeset_shift), \ 64 - .modeset_shift = _modeset_shift \ 65 66 } 66 67 67 68 #define MT6358_LDO(match, vreg, ldo_volt_table, \ 68 69 ldo_index_table, enreg, enbit, vosel, \ 69 - vosel_mask, vosel_shift) \ 70 + vosel_mask) \ 70 71 [MT6358_ID_##vreg] = { \ 71 72 .desc = { \ 72 73 .name = #vreg, \ ··· 84 89 .qi = BIT(15), \ 85 90 .index_table = ldo_index_table, \ 86 91 .n_table = ARRAY_SIZE(ldo_index_table), \ 87 - .vsel_shift = vosel_shift, \ 88 92 } 89 93 90 94 #define MT6358_LDO1(match, vreg, min, max, step, \ 91 95 volt_ranges, _da_vsel_reg, _da_vsel_mask, \ 92 - _da_vsel_shift, vosel, vosel_mask) \ 96 + vosel, vosel_mask) \ 93 97 [MT6358_ID_##vreg] = { \ 94 98 .desc = { \ 95 99 .name = #vreg, \ ··· 107 113 }, \ 108 114 .da_vsel_reg = _da_vsel_reg, \ 109 115 .da_vsel_mask = _da_vsel_mask, \ 110 - .da_vsel_shift = _da_vsel_shift, \ 111 116 .status_reg = MT6358_LDO_##vreg##_DBG1, \ 112 117 .qi = BIT(0), \ 113 118 } ··· 253 260 pvol = info->index_table; 254 261 255 262 idx = pvol[selector]; 263 + idx <<= ffs(info->desc.vsel_mask) - 1; 256 264 ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg, 257 - info->desc.vsel_mask, 258 - idx << info->vsel_shift); 265 + info->desc.vsel_mask, idx); 259 266 260 267 return ret; 261 268 } ··· 275 282 return ret; 276 283 } 277 284 278 - selector = (selector & info->desc.vsel_mask) >> info->vsel_shift; 285 + selector = (selector & info->desc.vsel_mask) >> 286 + (ffs(info->desc.vsel_mask) - 1); 279 287 pvol = info->index_table; 280 288 for (idx = 0; idx < info->desc.n_voltages; idx++) { 281 289 if (pvol[idx] == selector) ··· 299 305 return ret; 300 306 } 301 307 302 - ret = (regval >> info->da_vsel_shift) & info->da_vsel_mask; 308 + ret = (regval & info->da_vsel_mask) >> (ffs(info->da_vsel_mask) - 1); 303 309 304 310 return ret; 305 311 } ··· 336 342 return -EINVAL; 337 343 } 338 344 339 - dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x, %#x\n", 340 - info->modeset_reg, info->modeset_mask, 341 - info->modeset_shift, val); 345 + dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x\n", 346 + info->modeset_reg, info->modeset_mask, val); 342 347 343 - val <<= info->modeset_shift; 348 + val <<= ffs(info->modeset_mask) - 1; 344 349 345 350 return regmap_update_bits(rdev->regmap, info->modeset_reg, 346 351 info->modeset_mask, val); ··· 357 364 return ret; 358 365 } 359 366 360 - switch ((regval & info->modeset_mask) >> info->modeset_shift) { 367 + switch ((regval & info->modeset_mask) >> (ffs(info->modeset_mask) - 1)) { 361 368 case MT6358_BUCK_MODE_AUTO: 362 369 return REGULATOR_MODE_NORMAL; 363 370 case MT6358_BUCK_MODE_FORCE_PWM: ··· 405 412 static struct mt6358_regulator_info mt6358_regulators[] = { 406 413 MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500, 407 414 buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, 408 - 0, MT6358_VDRAM1_ANA_CON0, 8), 415 + MT6358_VDRAM1_ANA_CON0, 8), 409 416 MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250, 410 417 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, 411 - 0, MT6358_VCORE_VGPU_ANA_CON0, 1), 418 + MT6358_VCORE_VGPU_ANA_CON0, 1), 412 419 MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, 413 - buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, 0, 420 + buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, 414 421 MT6358_VPA_ANA_CON0, 3), 415 422 MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250, 416 423 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, 417 - 0, MT6358_VPROC_ANA_CON0, 1), 424 + MT6358_VPROC_ANA_CON0, 1), 418 425 MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250, 419 426 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, 420 - 0, MT6358_VPROC_ANA_CON0, 2), 427 + MT6358_VPROC_ANA_CON0, 2), 421 428 MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250, 422 - buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, 0, 429 + buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, 423 430 MT6358_VCORE_VGPU_ANA_CON0, 2), 424 431 MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500, 425 - buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, 0, 432 + buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, 426 433 MT6358_VS2_ANA_CON0, 8), 427 434 MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250, 428 435 buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, 429 - 0, MT6358_VMODEM_ANA_CON0, 8), 436 + MT6358_VMODEM_ANA_CON0, 8), 430 437 MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500, 431 - buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, 0, 438 + buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, 432 439 MT6358_VS1_ANA_CON0, 8), 433 440 MT6358_REG_FIXED("ldo_vrf12", VRF12, 434 441 MT6358_LDO_VRF12_CON0, 0, 1200000), ··· 450 457 MT6358_REG_FIXED("ldo_vaud28", VAUD28, 451 458 MT6358_LDO_VAUD28_CON0, 0, 2800000), 452 459 MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx, 453 - MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf, 0), 460 + MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf), 454 461 MT6358_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx, 455 - MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00, 8), 462 + MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00), 456 463 MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx, 457 - MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00, 8), 464 + MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00), 458 465 MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx, 459 - MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700, 8), 466 + MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700), 460 467 MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx, 461 - MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00, 8), 468 + MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00), 462 469 MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx, 463 - MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00, 8), 470 + MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00), 464 471 MT6358_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx, 465 - MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700, 8), 472 + MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700), 466 473 MT6358_LDO("ldo_vcama1", VCAMA1, vcama_voltages, vcama_idx, 467 - MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00, 8), 474 + MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00), 468 475 MT6358_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx, 469 - MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700, 8), 476 + MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700), 470 477 MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages, 471 478 vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0, 472 - 0, MT6358_VCN33_ANA_CON0, 0x300, 8), 479 + 0, MT6358_VCN33_ANA_CON0, 0x300), 473 480 MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages, 474 481 vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1, 475 - 0, MT6358_VCN33_ANA_CON0, 0x300, 8), 482 + 0, MT6358_VCN33_ANA_CON0, 0x300), 476 483 MT6358_LDO("ldo_vcama2", VCAMA2, vcama_voltages, vcama_idx, 477 - MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00, 8), 484 + MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00), 478 485 MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx, 479 - MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00, 8), 486 + MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00), 480 487 MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx, 481 488 MT6358_LDO_VLDO28_CON0_0, 0, 482 - MT6358_VLDO28_ANA_CON0, 0x300, 8), 489 + MT6358_VLDO28_ANA_CON0, 0x300), 483 490 MT6358_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx, 484 - MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00, 8), 491 + MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00), 485 492 MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250, 486 - buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f, 8, 493 + buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, 487 494 MT6358_LDO_VSRAM_CON0, 0x7f), 488 495 MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, 489 - buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f, 8, 496 + buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, 490 497 MT6358_LDO_VSRAM_CON2, 0x7f), 491 498 MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250, 492 - buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f, 8, 499 + buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, 493 500 MT6358_LDO_VSRAM_CON3, 0x7f), 494 501 MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250, 495 - buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f, 8, 502 + buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, 496 503 MT6358_LDO_VSRAM_CON1, 0x7f), 497 504 }; 498 505