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dt-bindings: dmaengine: Add X1830 bindings.
Add the dmaengine bindings for the X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1576591140-125668-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
周琰杰 (Zhou Yanjie)
and committed by
Vinod Koul
b9890054
ed5a0ab4
+43
-2
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-2
Documentation/devicetree/bindings/dma/jz4780-dma.txt
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-2
Documentation/devicetree/bindings/dma/jz4780-dma.txt
···
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* Ingenic JZ4780 DMA Controller
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* Ingenic XBurst DMA Controller
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Required properties:
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···
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* ingenic,jz4770-dma
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* ingenic,jz4780-dma
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* ingenic,x1000-dma
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* ingenic,x1830-dma
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- reg: Should contain the DMA channel registers location and length, followed
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by the DMA controller registers location and length.
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- interrupts: Should contain the interrupt specifier of the DMA controller.
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- clocks: Should contain a clock specifier for the JZ4780/X1000 PDMA clock.
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- clocks: Should contain a clock specifier for the JZ4780/X1000/X1830 PDMA
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clock.
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- #dma-cells: Must be <2>. Number of integer cells in the dmas property of
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DMA clients (see below).
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+39
include/dt-bindings/dma/x1830-dma.h
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include/dt-bindings/dma/x1830-dma.h
···
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This header provides macros for X1830 DMA bindings.
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*
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* Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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*/
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#ifndef __DT_BINDINGS_DMA_X1830_DMA_H__
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#define __DT_BINDINGS_DMA_X1830_DMA_H__
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/*
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* Request type numbers for the X1830 DMA controller (written to the DRTn
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* register for the channel).
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*/
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#define X1830_DMA_I2S0_TX 0x6
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#define X1830_DMA_I2S0_RX 0x7
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#define X1830_DMA_AUTO 0x8
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#define X1830_DMA_SADC_RX 0x9
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#define X1830_DMA_UART1_TX 0x12
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#define X1830_DMA_UART1_RX 0x13
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#define X1830_DMA_UART0_TX 0x14
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#define X1830_DMA_UART0_RX 0x15
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#define X1830_DMA_SSI0_TX 0x16
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#define X1830_DMA_SSI0_RX 0x17
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#define X1830_DMA_SSI1_TX 0x18
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#define X1830_DMA_SSI1_RX 0x19
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#define X1830_DMA_MSC0_TX 0x1a
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#define X1830_DMA_MSC0_RX 0x1b
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#define X1830_DMA_MSC1_TX 0x1c
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#define X1830_DMA_MSC1_RX 0x1d
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#define X1830_DMA_DMIC_RX 0x21
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#define X1830_DMA_SMB0_TX 0x24
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#define X1830_DMA_SMB0_RX 0x25
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#define X1830_DMA_SMB1_TX 0x26
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#define X1830_DMA_SMB1_RX 0x27
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#define X1830_DMA_DES_TX 0x2e
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#define X1830_DMA_DES_RX 0x2f
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#endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */