Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git

ath.git patches for 4.10. Major changes:

ath10k

* allow setting coverage class for first generation cards
* read regulatory domain from ACPI

ath9k

* disable RNG by default

+432 -12
+13
drivers/net/wireless/ath/ath10k/core.c
··· 198 198 .name = "qca9984/qca9994 hw1.0", 199 199 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 200 200 .uart_pin = 7, 201 + .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 201 202 .otp_exe_param = 0x00000700, 202 203 .continuous_frag_desc = true, 203 204 .cck_rate_map_rev2 = true, ··· 224 223 .name = "qca9888 hw2.0", 225 224 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 226 225 .uart_pin = 7, 226 + .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 227 227 .otp_exe_param = 0x00000700, 228 228 .continuous_frag_desc = true, 229 229 .channel_counters_freq_hz = 150000, ··· 1562 1560 mutex_unlock(&ar->conf_mutex); 1563 1561 } 1564 1562 1563 + static void ath10k_core_set_coverage_class_work(struct work_struct *work) 1564 + { 1565 + struct ath10k *ar = container_of(work, struct ath10k, 1566 + set_coverage_class_work); 1567 + 1568 + if (ar->hw_params.hw_ops->set_coverage_class) 1569 + ar->hw_params.hw_ops->set_coverage_class(ar, -1); 1570 + } 1571 + 1565 1572 static int ath10k_core_init_firmware_features(struct ath10k *ar) 1566 1573 { 1567 1574 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; ··· 2353 2342 2354 2343 INIT_WORK(&ar->register_work, ath10k_core_register_work); 2355 2344 INIT_WORK(&ar->restart_work, ath10k_core_restart); 2345 + INIT_WORK(&ar->set_coverage_class_work, 2346 + ath10k_core_set_coverage_class_work); 2356 2347 2357 2348 init_dummy_netdev(&ar->napi_dev); 2358 2349
+14
drivers/net/wireless/ath/ath10k/core.h
··· 713 713 u32 phy_capability; 714 714 u32 hw_min_tx_power; 715 715 u32 hw_max_tx_power; 716 + u32 hw_eeprom_rd; 716 717 u32 ht_cap_info; 717 718 u32 vht_cap_info; 718 719 u32 num_rf_chains; ··· 911 910 /* NAPI */ 912 911 struct net_device napi_dev; 913 912 struct napi_struct napi; 913 + 914 + struct work_struct set_coverage_class_work; 915 + /* protected by conf_mutex */ 916 + struct { 917 + /* writing also protected by data_lock */ 918 + s16 coverage_class; 919 + 920 + u32 reg_phyclk; 921 + u32 reg_slottime_conf; 922 + u32 reg_slottime_orig; 923 + u32 reg_ack_cts_timeout_conf; 924 + u32 reg_ack_cts_timeout_orig; 925 + } fw_coverage; 914 926 915 927 /* must be last */ 916 928 u8 drv_priv[0] __aligned(sizeof(void *));
+22
drivers/net/wireless/ath/ath10k/debug.h
··· 94 94 void ath10k_debug_get_et_stats(struct ieee80211_hw *hw, 95 95 struct ieee80211_vif *vif, 96 96 struct ethtool_stats *stats, u64 *data); 97 + 98 + static inline u64 ath10k_debug_get_fw_dbglog_mask(struct ath10k *ar) 99 + { 100 + return ar->debug.fw_dbglog_mask; 101 + } 102 + 103 + static inline u32 ath10k_debug_get_fw_dbglog_level(struct ath10k *ar) 104 + { 105 + return ar->debug.fw_dbglog_level; 106 + } 107 + 97 108 #else 109 + 98 110 static inline int ath10k_debug_start(struct ath10k *ar) 99 111 { 100 112 return 0; ··· 154 142 ath10k_debug_get_new_fw_crash_data(struct ath10k *ar) 155 143 { 156 144 return NULL; 145 + } 146 + 147 + static inline u64 ath10k_debug_get_fw_dbglog_mask(struct ath10k *ar) 148 + { 149 + return 0; 150 + } 151 + 152 + static inline u32 ath10k_debug_get_fw_dbglog_level(struct ath10k *ar) 153 + { 154 + return 0; 157 155 } 158 156 159 157 #define ATH10K_DFS_STAT_INC(ar, c) do { } while (0)
+6 -6
drivers/net/wireless/ath/ath10k/htt_rx.c
··· 1463 1463 } 1464 1464 1465 1465 static void ath10k_htt_rx_h_unchain(struct ath10k *ar, 1466 - struct sk_buff_head *amsdu, 1467 - bool chained) 1466 + struct sk_buff_head *amsdu) 1468 1467 { 1469 1468 struct sk_buff *first; 1470 1469 struct htt_rx_desc *rxd; ··· 1473 1474 rxd = (void *)first->data - sizeof(*rxd); 1474 1475 decap = MS(__le32_to_cpu(rxd->msdu_start.common.info1), 1475 1476 RX_MSDU_START_INFO1_DECAP_FORMAT); 1476 - 1477 - if (!chained) 1478 - return; 1479 1477 1480 1478 /* FIXME: Current unchaining logic can only handle simple case of raw 1481 1479 * msdu chaining. If decapping is other than raw the chaining may be ··· 1551 1555 1552 1556 num_msdus = skb_queue_len(&amsdu); 1553 1557 ath10k_htt_rx_h_ppdu(ar, &amsdu, rx_status, 0xffff); 1554 - ath10k_htt_rx_h_unchain(ar, &amsdu, ret > 0); 1558 + 1559 + /* only for ret = 1 indicates chained msdus */ 1560 + if (ret > 0) 1561 + ath10k_htt_rx_h_unchain(ar, &amsdu); 1562 + 1555 1563 ath10k_htt_rx_h_filter(ar, &amsdu, rx_status); 1556 1564 ath10k_htt_rx_h_mpdu(ar, &amsdu, rx_status); 1557 1565 ath10k_htt_rx_h_deliver(ar, &amsdu, rx_status);
+142
drivers/net/wireless/ath/ath10k/hw.c
··· 17 17 #include <linux/types.h> 18 18 #include "core.h" 19 19 #include "hw.h" 20 + #include "hif.h" 21 + #include "wmi-ops.h" 20 22 21 23 const struct ath10k_hw_regs qca988x_regs = { 22 24 .rtc_soc_base_address = 0x00004000, 23 25 .rtc_wmac_base_address = 0x00005000, 24 26 .soc_core_base_address = 0x00009000, 27 + .wlan_mac_base_address = 0x00020000, 25 28 .ce_wrapper_base_address = 0x00057000, 26 29 .ce0_base_address = 0x00057400, 27 30 .ce1_base_address = 0x00057800, ··· 51 48 .rtc_soc_base_address = 0x00000800, 52 49 .rtc_wmac_base_address = 0x00001000, 53 50 .soc_core_base_address = 0x0003a000, 51 + .wlan_mac_base_address = 0x00020000, 54 52 .ce_wrapper_base_address = 0x00034000, 55 53 .ce0_base_address = 0x00034400, 56 54 .ce1_base_address = 0x00034800, ··· 78 74 .rtc_soc_base_address = 0x00080000, 79 75 .rtc_wmac_base_address = 0x00000000, 80 76 .soc_core_base_address = 0x00082000, 77 + .wlan_mac_base_address = 0x00030000, 81 78 .ce_wrapper_base_address = 0x0004d000, 82 79 .ce0_base_address = 0x0004a000, 83 80 .ce1_base_address = 0x0004a400, ··· 114 109 const struct ath10k_hw_regs qca4019_regs = { 115 110 .rtc_soc_base_address = 0x00080000, 116 111 .soc_core_base_address = 0x00082000, 112 + .wlan_mac_base_address = 0x00030000, 117 113 .ce_wrapper_base_address = 0x0004d000, 118 114 .ce0_base_address = 0x0004a000, 119 115 .ce1_base_address = 0x0004a400, ··· 226 220 survey->time_busy = CCNT_TO_MSEC(ar, rcc); 227 221 } 228 222 223 + /* The firmware does not support setting the coverage class. Instead this 224 + * function monitors and modifies the corresponding MAC registers. 225 + */ 226 + static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar, 227 + s16 value) 228 + { 229 + u32 slottime_reg; 230 + u32 slottime; 231 + u32 timeout_reg; 232 + u32 ack_timeout; 233 + u32 cts_timeout; 234 + u32 phyclk_reg; 235 + u32 phyclk; 236 + u64 fw_dbglog_mask; 237 + u32 fw_dbglog_level; 238 + 239 + mutex_lock(&ar->conf_mutex); 240 + 241 + /* Only modify registers if the core is started. */ 242 + if ((ar->state != ATH10K_STATE_ON) && 243 + (ar->state != ATH10K_STATE_RESTARTED)) 244 + goto unlock; 245 + 246 + /* Retrieve the current values of the two registers that need to be 247 + * adjusted. 248 + */ 249 + slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 250 + WAVE1_PCU_GBL_IFS_SLOT); 251 + timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 252 + WAVE1_PCU_ACK_CTS_TIMEOUT); 253 + phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS + 254 + WAVE1_PHYCLK); 255 + phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1; 256 + 257 + if (value < 0) 258 + value = ar->fw_coverage.coverage_class; 259 + 260 + /* Break out if the coverage class and registers have the expected 261 + * value. 262 + */ 263 + if (value == ar->fw_coverage.coverage_class && 264 + slottime_reg == ar->fw_coverage.reg_slottime_conf && 265 + timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf && 266 + phyclk_reg == ar->fw_coverage.reg_phyclk) 267 + goto unlock; 268 + 269 + /* Store new initial register values from the firmware. */ 270 + if (slottime_reg != ar->fw_coverage.reg_slottime_conf) 271 + ar->fw_coverage.reg_slottime_orig = slottime_reg; 272 + if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf) 273 + ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg; 274 + ar->fw_coverage.reg_phyclk = phyclk_reg; 275 + 276 + /* Calculat new value based on the (original) firmware calculation. */ 277 + slottime_reg = ar->fw_coverage.reg_slottime_orig; 278 + timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig; 279 + 280 + /* Do some sanity checks on the slottime register. */ 281 + if (slottime_reg % phyclk) { 282 + ath10k_warn(ar, 283 + "failed to set coverage class: expected integer microsecond value in register\n"); 284 + 285 + goto store_regs; 286 + } 287 + 288 + slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT); 289 + slottime = slottime / phyclk; 290 + if (slottime != 9 && slottime != 20) { 291 + ath10k_warn(ar, 292 + "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n", 293 + slottime); 294 + 295 + goto store_regs; 296 + } 297 + 298 + /* Recalculate the register values by adding the additional propagation 299 + * delay (3us per coverage class). 300 + */ 301 + 302 + slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT); 303 + slottime += value * 3 * phyclk; 304 + slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX); 305 + slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT); 306 + slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime; 307 + 308 + /* Update ack timeout (lower halfword). */ 309 + ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); 310 + ack_timeout += 3 * value * phyclk; 311 + ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX); 312 + ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); 313 + 314 + /* Update cts timeout (upper halfword). */ 315 + cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); 316 + cts_timeout += 3 * value * phyclk; 317 + cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX); 318 + cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); 319 + 320 + timeout_reg = ack_timeout | cts_timeout; 321 + 322 + ath10k_hif_write32(ar, 323 + WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT, 324 + slottime_reg); 325 + ath10k_hif_write32(ar, 326 + WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT, 327 + timeout_reg); 328 + 329 + /* Ensure we have a debug level of WARN set for the case that the 330 + * coverage class is larger than 0. This is important as we need to 331 + * set the registers again if the firmware does an internal reset and 332 + * this way we will be notified of the event. 333 + */ 334 + fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar); 335 + fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar); 336 + 337 + if (value > 0) { 338 + if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN) 339 + fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN; 340 + fw_dbglog_mask = ~0; 341 + } 342 + 343 + ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level); 344 + 345 + store_regs: 346 + /* After an error we will not retry setting the coverage class. */ 347 + spin_lock_bh(&ar->data_lock); 348 + ar->fw_coverage.coverage_class = value; 349 + spin_unlock_bh(&ar->data_lock); 350 + 351 + ar->fw_coverage.reg_slottime_conf = slottime_reg; 352 + ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg; 353 + 354 + unlock: 355 + mutex_unlock(&ar->conf_mutex); 356 + } 357 + 229 358 const struct ath10k_hw_ops qca988x_ops = { 359 + .set_coverage_class = ath10k_hw_qca988x_set_coverage_class, 230 360 }; 231 361 232 362 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
+27 -1
drivers/net/wireless/ath/ath10k/hw.h
··· 230 230 u32 rtc_soc_base_address; 231 231 u32 rtc_wmac_base_address; 232 232 u32 soc_core_base_address; 233 + u32 wlan_mac_base_address; 233 234 u32 ce_wrapper_base_address; 234 235 u32 ce0_base_address; 235 236 u32 ce1_base_address; ··· 419 418 /* Defines needed for Rx descriptor abstraction */ 420 419 struct ath10k_hw_ops { 421 420 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 421 + void (*set_coverage_class)(struct ath10k *ar, s16 value); 422 422 }; 423 423 424 424 extern const struct ath10k_hw_ops qca988x_ops; ··· 616 614 #define WLAN_SI_BASE_ADDRESS 0x00010000 617 615 #define WLAN_GPIO_BASE_ADDRESS 0x00014000 618 616 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 619 - #define WLAN_MAC_BASE_ADDRESS 0x00020000 617 + #define WLAN_MAC_BASE_ADDRESS ar->regs->wlan_mac_base_address 620 618 #define EFUSE_BASE_ADDRESS 0x00030000 621 619 #define FPGA_REG_BASE_ADDRESS 0x00039000 622 620 #define WLAN_UART2_BASE_ADDRESS 0x00054c00 ··· 815 813 #define QCA9887_EEPROM_ADDR_LO_LSB 16 816 814 817 815 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 816 + 817 + /* Register definitions for first generation ath10k cards. These cards include 818 + * a mac thich has a register allocation similar to ath9k and at least some 819 + * registers including the ones relevant for modifying the coverage class are 820 + * identical to the ath9k definitions. 821 + * These registers are usually managed by the ath10k firmware. However by 822 + * overriding them it is possible to support coverage class modifications. 823 + */ 824 + #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014 825 + #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF 826 + #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF 827 + #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0 828 + #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000 829 + #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB 16 830 + 831 + #define WAVE1_PCU_GBL_IFS_SLOT 0x1070 832 + #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF 833 + #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF 834 + #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0 835 + #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000 836 + 837 + #define WAVE1_PHYCLK 0x801C 838 + #define WAVE1_PHYCLK_USEC_MASK 0x0000007F 839 + #define WAVE1_PHYCLK_USEC_LSB 0 818 840 819 841 #endif /* _HW_H_ */
+137 -1
drivers/net/wireless/ath/ath10k/mac.c
··· 19 19 20 20 #include <net/mac80211.h> 21 21 #include <linux/etherdevice.h> 22 + #include <linux/acpi.h> 22 23 23 24 #include "hif.h" 24 25 #include "core.h" ··· 3180 3179 ath10k_mac_vif_tx_unlock(arvif, pause_id); 3181 3180 break; 3182 3181 default: 3183 - ath10k_warn(ar, "received unknown tx pause action %d on vdev %i, ignoring\n", 3182 + ath10k_dbg(ar, ATH10K_DBG_BOOT, 3183 + "received unknown tx pause action %d on vdev %i, ignoring\n", 3184 3184 action, arvif->vdev_id); 3185 3185 break; 3186 3186 } ··· 4931 4929 } 4932 4930 4933 4931 ar->free_vdev_map &= ~(1LL << arvif->vdev_id); 4932 + spin_lock_bh(&ar->data_lock); 4934 4933 list_add(&arvif->list, &ar->arvifs); 4934 + spin_unlock_bh(&ar->data_lock); 4935 4935 4936 4936 /* It makes no sense to have firmware do keepalives. mac80211 already 4937 4937 * takes care of this with idle connection polling. ··· 5084 5080 err_vdev_delete: 5085 5081 ath10k_wmi_vdev_delete(ar, arvif->vdev_id); 5086 5082 ar->free_vdev_map |= 1LL << arvif->vdev_id; 5083 + spin_lock_bh(&ar->data_lock); 5087 5084 list_del(&arvif->list); 5085 + spin_unlock_bh(&ar->data_lock); 5088 5086 5089 5087 err: 5090 5088 if (arvif->beacon_buf) { ··· 5132 5126 arvif->vdev_id, ret); 5133 5127 5134 5128 ar->free_vdev_map |= 1LL << arvif->vdev_id; 5129 + spin_lock_bh(&ar->data_lock); 5135 5130 list_del(&arvif->list); 5131 + spin_unlock_bh(&ar->data_lock); 5136 5132 5137 5133 if (arvif->vdev_type == WMI_VDEV_TYPE_AP || 5138 5134 arvif->vdev_type == WMI_VDEV_TYPE_IBSS) { ··· 5416 5408 } 5417 5409 5418 5410 mutex_unlock(&ar->conf_mutex); 5411 + } 5412 + 5413 + static void ath10k_mac_op_set_coverage_class(struct ieee80211_hw *hw, s16 value) 5414 + { 5415 + struct ath10k *ar = hw->priv; 5416 + 5417 + /* This function should never be called if setting the coverage class 5418 + * is not supported on this hardware. 5419 + */ 5420 + if (!ar->hw_params.hw_ops->set_coverage_class) { 5421 + WARN_ON_ONCE(1); 5422 + return; 5423 + } 5424 + ar->hw_params.hw_ops->set_coverage_class(ar, value); 5419 5425 } 5420 5426 5421 5427 static int ath10k_hw_scan(struct ieee80211_hw *hw, ··· 7457 7435 .remove_interface = ath10k_remove_interface, 7458 7436 .configure_filter = ath10k_configure_filter, 7459 7437 .bss_info_changed = ath10k_bss_info_changed, 7438 + .set_coverage_class = ath10k_mac_op_set_coverage_class, 7460 7439 .hw_scan = ath10k_hw_scan, 7461 7440 .cancel_hw_scan = ath10k_cancel_hw_scan, 7462 7441 .set_key = ath10k_set_key, ··· 7812 7789 return arvif_iter.arvif; 7813 7790 } 7814 7791 7792 + #define WRD_METHOD "WRDD" 7793 + #define WRDD_WIFI (0x07) 7794 + 7795 + static u32 ath10k_mac_wrdd_get_mcc(struct ath10k *ar, union acpi_object *wrdd) 7796 + { 7797 + union acpi_object *mcc_pkg; 7798 + union acpi_object *domain_type; 7799 + union acpi_object *mcc_value; 7800 + u32 i; 7801 + 7802 + if (wrdd->type != ACPI_TYPE_PACKAGE || 7803 + wrdd->package.count < 2 || 7804 + wrdd->package.elements[0].type != ACPI_TYPE_INTEGER || 7805 + wrdd->package.elements[0].integer.value != 0) { 7806 + ath10k_warn(ar, "ignoring malformed/unsupported wrdd structure\n"); 7807 + return 0; 7808 + } 7809 + 7810 + for (i = 1; i < wrdd->package.count; ++i) { 7811 + mcc_pkg = &wrdd->package.elements[i]; 7812 + 7813 + if (mcc_pkg->type != ACPI_TYPE_PACKAGE) 7814 + continue; 7815 + if (mcc_pkg->package.count < 2) 7816 + continue; 7817 + if (mcc_pkg->package.elements[0].type != ACPI_TYPE_INTEGER || 7818 + mcc_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) 7819 + continue; 7820 + 7821 + domain_type = &mcc_pkg->package.elements[0]; 7822 + if (domain_type->integer.value != WRDD_WIFI) 7823 + continue; 7824 + 7825 + mcc_value = &mcc_pkg->package.elements[1]; 7826 + return mcc_value->integer.value; 7827 + } 7828 + return 0; 7829 + } 7830 + 7831 + static int ath10k_mac_get_wrdd_regulatory(struct ath10k *ar, u16 *rd) 7832 + { 7833 + struct pci_dev __maybe_unused *pdev = to_pci_dev(ar->dev); 7834 + acpi_handle root_handle; 7835 + acpi_handle handle; 7836 + struct acpi_buffer wrdd = {ACPI_ALLOCATE_BUFFER, NULL}; 7837 + acpi_status status; 7838 + u32 alpha2_code; 7839 + char alpha2[3]; 7840 + 7841 + root_handle = ACPI_HANDLE(&pdev->dev); 7842 + if (!root_handle) 7843 + return -EOPNOTSUPP; 7844 + 7845 + status = acpi_get_handle(root_handle, (acpi_string)WRD_METHOD, &handle); 7846 + if (ACPI_FAILURE(status)) { 7847 + ath10k_dbg(ar, ATH10K_DBG_BOOT, 7848 + "failed to get wrd method %d\n", status); 7849 + return -EIO; 7850 + } 7851 + 7852 + status = acpi_evaluate_object(handle, NULL, NULL, &wrdd); 7853 + if (ACPI_FAILURE(status)) { 7854 + ath10k_dbg(ar, ATH10K_DBG_BOOT, 7855 + "failed to call wrdc %d\n", status); 7856 + return -EIO; 7857 + } 7858 + 7859 + alpha2_code = ath10k_mac_wrdd_get_mcc(ar, wrdd.pointer); 7860 + kfree(wrdd.pointer); 7861 + if (!alpha2_code) 7862 + return -EIO; 7863 + 7864 + alpha2[0] = (alpha2_code >> 8) & 0xff; 7865 + alpha2[1] = (alpha2_code >> 0) & 0xff; 7866 + alpha2[2] = '\0'; 7867 + 7868 + ath10k_dbg(ar, ATH10K_DBG_BOOT, 7869 + "regulatory hint from WRDD (alpha2-code): %s\n", alpha2); 7870 + 7871 + *rd = ath_regd_find_country_by_name(alpha2); 7872 + if (*rd == 0xffff) 7873 + return -EIO; 7874 + 7875 + *rd |= COUNTRY_ERD_FLAG; 7876 + return 0; 7877 + } 7878 + 7879 + static int ath10k_mac_init_rd(struct ath10k *ar) 7880 + { 7881 + int ret; 7882 + u16 rd; 7883 + 7884 + ret = ath10k_mac_get_wrdd_regulatory(ar, &rd); 7885 + if (ret) { 7886 + ath10k_dbg(ar, ATH10K_DBG_BOOT, 7887 + "fallback to eeprom programmed regulatory settings\n"); 7888 + rd = ar->hw_eeprom_rd; 7889 + } 7890 + 7891 + ar->ath_common.regulatory.current_rd = rd; 7892 + return 0; 7893 + } 7894 + 7815 7895 int ath10k_mac_register(struct ath10k *ar) 7816 7896 { 7817 7897 static const u32 cipher_suites[] = { ··· 8137 8011 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 8138 8012 ar->running_fw->fw_file.fw_features)) 8139 8013 ar->ops->wake_tx_queue = NULL; 8014 + 8015 + ret = ath10k_mac_init_rd(ar); 8016 + if (ret) { 8017 + ath10k_err(ar, "failed to derive regdom: %d\n", ret); 8018 + goto err_dfs_detector_exit; 8019 + } 8020 + 8021 + /* Disable set_coverage_class for chipsets that do not support it. */ 8022 + if (!ar->hw_params.hw_ops->set_coverage_class) 8023 + ar->ops->set_coverage_class = NULL; 8140 8024 8141 8025 ret = ath_regd_init(&ar->ath_common.regulatory, ar->hw->wiphy, 8142 8026 ath10k_reg_notifier);
+53 -1
drivers/net/wireless/ath/ath10k/wmi.c
··· 4676 4676 ar->fw_version_build = (__le32_to_cpu(arg.sw_ver1) & 0x0000ffff); 4677 4677 ar->phy_capability = __le32_to_cpu(arg.phy_capab); 4678 4678 ar->num_rf_chains = __le32_to_cpu(arg.num_rf_chains); 4679 - ar->ath_common.regulatory.current_rd = __le32_to_cpu(arg.eeprom_rd); 4679 + ar->hw_eeprom_rd = __le32_to_cpu(arg.eeprom_rd); 4680 4680 4681 4681 ath10k_dbg_dump(ar, ATH10K_DBG_WMI, NULL, "wmi svc: ", 4682 4682 arg.service_map, arg.service_map_len); ··· 4931 4931 return 0; 4932 4932 } 4933 4933 4934 + static inline void ath10k_wmi_queue_set_coverage_class_work(struct ath10k *ar) 4935 + { 4936 + if (ar->hw_params.hw_ops->set_coverage_class) { 4937 + spin_lock_bh(&ar->data_lock); 4938 + 4939 + /* This call only ensures that the modified coverage class 4940 + * persists in case the firmware sets the registers back to 4941 + * their default value. So calling it is only necessary if the 4942 + * coverage class has a non-zero value. 4943 + */ 4944 + if (ar->fw_coverage.coverage_class) 4945 + queue_work(ar->workqueue, &ar->set_coverage_class_work); 4946 + 4947 + spin_unlock_bh(&ar->data_lock); 4948 + } 4949 + } 4950 + 4934 4951 static void ath10k_wmi_op_rx(struct ath10k *ar, struct sk_buff *skb) 4935 4952 { 4936 4953 struct wmi_cmd_hdr *cmd_hdr; ··· 4968 4951 return; 4969 4952 case WMI_SCAN_EVENTID: 4970 4953 ath10k_wmi_event_scan(ar, skb); 4954 + ath10k_wmi_queue_set_coverage_class_work(ar); 4971 4955 break; 4972 4956 case WMI_CHAN_INFO_EVENTID: 4973 4957 ath10k_wmi_event_chan_info(ar, skb); ··· 4978 4960 break; 4979 4961 case WMI_DEBUG_MESG_EVENTID: 4980 4962 ath10k_wmi_event_debug_mesg(ar, skb); 4963 + ath10k_wmi_queue_set_coverage_class_work(ar); 4981 4964 break; 4982 4965 case WMI_UPDATE_STATS_EVENTID: 4983 4966 ath10k_wmi_event_update_stats(ar, skb); 4984 4967 break; 4985 4968 case WMI_VDEV_START_RESP_EVENTID: 4986 4969 ath10k_wmi_event_vdev_start_resp(ar, skb); 4970 + ath10k_wmi_queue_set_coverage_class_work(ar); 4987 4971 break; 4988 4972 case WMI_VDEV_STOPPED_EVENTID: 4989 4973 ath10k_wmi_event_vdev_stopped(ar, skb); 4974 + ath10k_wmi_queue_set_coverage_class_work(ar); 4990 4975 break; 4991 4976 case WMI_PEER_STA_KICKOUT_EVENTID: 4992 4977 ath10k_wmi_event_peer_sta_kickout(ar, skb); ··· 5005 4984 break; 5006 4985 case WMI_ROAM_EVENTID: 5007 4986 ath10k_wmi_event_roam(ar, skb); 4987 + ath10k_wmi_queue_set_coverage_class_work(ar); 5008 4988 break; 5009 4989 case WMI_PROFILE_MATCH: 5010 4990 ath10k_wmi_event_profile_match(ar, skb); 5011 4991 break; 5012 4992 case WMI_DEBUG_PRINT_EVENTID: 5013 4993 ath10k_wmi_event_debug_print(ar, skb); 4994 + ath10k_wmi_queue_set_coverage_class_work(ar); 5014 4995 break; 5015 4996 case WMI_PDEV_QVIT_EVENTID: 5016 4997 ath10k_wmi_event_pdev_qvit(ar, skb); ··· 5061 5038 return; 5062 5039 case WMI_READY_EVENTID: 5063 5040 ath10k_wmi_event_ready(ar, skb); 5041 + ath10k_wmi_queue_set_coverage_class_work(ar); 5064 5042 break; 5065 5043 default: 5066 5044 ath10k_warn(ar, "Unknown eventid: %d\n", id); ··· 5105 5081 return; 5106 5082 case WMI_10X_SCAN_EVENTID: 5107 5083 ath10k_wmi_event_scan(ar, skb); 5084 + ath10k_wmi_queue_set_coverage_class_work(ar); 5108 5085 break; 5109 5086 case WMI_10X_CHAN_INFO_EVENTID: 5110 5087 ath10k_wmi_event_chan_info(ar, skb); ··· 5115 5090 break; 5116 5091 case WMI_10X_DEBUG_MESG_EVENTID: 5117 5092 ath10k_wmi_event_debug_mesg(ar, skb); 5093 + ath10k_wmi_queue_set_coverage_class_work(ar); 5118 5094 break; 5119 5095 case WMI_10X_UPDATE_STATS_EVENTID: 5120 5096 ath10k_wmi_event_update_stats(ar, skb); 5121 5097 break; 5122 5098 case WMI_10X_VDEV_START_RESP_EVENTID: 5123 5099 ath10k_wmi_event_vdev_start_resp(ar, skb); 5100 + ath10k_wmi_queue_set_coverage_class_work(ar); 5124 5101 break; 5125 5102 case WMI_10X_VDEV_STOPPED_EVENTID: 5126 5103 ath10k_wmi_event_vdev_stopped(ar, skb); 5104 + ath10k_wmi_queue_set_coverage_class_work(ar); 5127 5105 break; 5128 5106 case WMI_10X_PEER_STA_KICKOUT_EVENTID: 5129 5107 ath10k_wmi_event_peer_sta_kickout(ar, skb); ··· 5142 5114 break; 5143 5115 case WMI_10X_ROAM_EVENTID: 5144 5116 ath10k_wmi_event_roam(ar, skb); 5117 + ath10k_wmi_queue_set_coverage_class_work(ar); 5145 5118 break; 5146 5119 case WMI_10X_PROFILE_MATCH: 5147 5120 ath10k_wmi_event_profile_match(ar, skb); 5148 5121 break; 5149 5122 case WMI_10X_DEBUG_PRINT_EVENTID: 5150 5123 ath10k_wmi_event_debug_print(ar, skb); 5124 + ath10k_wmi_queue_set_coverage_class_work(ar); 5151 5125 break; 5152 5126 case WMI_10X_PDEV_QVIT_EVENTID: 5153 5127 ath10k_wmi_event_pdev_qvit(ar, skb); ··· 5189 5159 return; 5190 5160 case WMI_10X_READY_EVENTID: 5191 5161 ath10k_wmi_event_ready(ar, skb); 5162 + ath10k_wmi_queue_set_coverage_class_work(ar); 5192 5163 break; 5193 5164 case WMI_10X_PDEV_UTF_EVENTID: 5194 5165 /* ignore utf events */ ··· 5236 5205 return; 5237 5206 case WMI_10_2_SCAN_EVENTID: 5238 5207 ath10k_wmi_event_scan(ar, skb); 5208 + ath10k_wmi_queue_set_coverage_class_work(ar); 5239 5209 break; 5240 5210 case WMI_10_2_CHAN_INFO_EVENTID: 5241 5211 ath10k_wmi_event_chan_info(ar, skb); ··· 5246 5214 break; 5247 5215 case WMI_10_2_DEBUG_MESG_EVENTID: 5248 5216 ath10k_wmi_event_debug_mesg(ar, skb); 5217 + ath10k_wmi_queue_set_coverage_class_work(ar); 5249 5218 break; 5250 5219 case WMI_10_2_UPDATE_STATS_EVENTID: 5251 5220 ath10k_wmi_event_update_stats(ar, skb); 5252 5221 break; 5253 5222 case WMI_10_2_VDEV_START_RESP_EVENTID: 5254 5223 ath10k_wmi_event_vdev_start_resp(ar, skb); 5224 + ath10k_wmi_queue_set_coverage_class_work(ar); 5255 5225 break; 5256 5226 case WMI_10_2_VDEV_STOPPED_EVENTID: 5257 5227 ath10k_wmi_event_vdev_stopped(ar, skb); 5228 + ath10k_wmi_queue_set_coverage_class_work(ar); 5258 5229 break; 5259 5230 case WMI_10_2_PEER_STA_KICKOUT_EVENTID: 5260 5231 ath10k_wmi_event_peer_sta_kickout(ar, skb); ··· 5273 5238 break; 5274 5239 case WMI_10_2_ROAM_EVENTID: 5275 5240 ath10k_wmi_event_roam(ar, skb); 5241 + ath10k_wmi_queue_set_coverage_class_work(ar); 5276 5242 break; 5277 5243 case WMI_10_2_PROFILE_MATCH: 5278 5244 ath10k_wmi_event_profile_match(ar, skb); 5279 5245 break; 5280 5246 case WMI_10_2_DEBUG_PRINT_EVENTID: 5281 5247 ath10k_wmi_event_debug_print(ar, skb); 5248 + ath10k_wmi_queue_set_coverage_class_work(ar); 5282 5249 break; 5283 5250 case WMI_10_2_PDEV_QVIT_EVENTID: 5284 5251 ath10k_wmi_event_pdev_qvit(ar, skb); ··· 5311 5274 break; 5312 5275 case WMI_10_2_VDEV_STANDBY_REQ_EVENTID: 5313 5276 ath10k_wmi_event_vdev_standby_req(ar, skb); 5277 + ath10k_wmi_queue_set_coverage_class_work(ar); 5314 5278 break; 5315 5279 case WMI_10_2_VDEV_RESUME_REQ_EVENTID: 5316 5280 ath10k_wmi_event_vdev_resume_req(ar, skb); 5281 + ath10k_wmi_queue_set_coverage_class_work(ar); 5317 5282 break; 5318 5283 case WMI_10_2_SERVICE_READY_EVENTID: 5319 5284 ath10k_wmi_event_service_ready(ar, skb); 5320 5285 return; 5321 5286 case WMI_10_2_READY_EVENTID: 5322 5287 ath10k_wmi_event_ready(ar, skb); 5288 + ath10k_wmi_queue_set_coverage_class_work(ar); 5323 5289 break; 5324 5290 case WMI_10_2_PDEV_TEMPERATURE_EVENTID: 5325 5291 ath10k_wmi_event_temperature(ar, skb); ··· 5385 5345 break; 5386 5346 case WMI_10_4_DEBUG_MESG_EVENTID: 5387 5347 ath10k_wmi_event_debug_mesg(ar, skb); 5348 + ath10k_wmi_queue_set_coverage_class_work(ar); 5388 5349 break; 5389 5350 case WMI_10_4_SERVICE_READY_EVENTID: 5390 5351 ath10k_wmi_event_service_ready(ar, skb); 5391 5352 return; 5392 5353 case WMI_10_4_SCAN_EVENTID: 5393 5354 ath10k_wmi_event_scan(ar, skb); 5355 + ath10k_wmi_queue_set_coverage_class_work(ar); 5394 5356 break; 5395 5357 case WMI_10_4_CHAN_INFO_EVENTID: 5396 5358 ath10k_wmi_event_chan_info(ar, skb); ··· 5402 5360 break; 5403 5361 case WMI_10_4_READY_EVENTID: 5404 5362 ath10k_wmi_event_ready(ar, skb); 5363 + ath10k_wmi_queue_set_coverage_class_work(ar); 5405 5364 break; 5406 5365 case WMI_10_4_PEER_STA_KICKOUT_EVENTID: 5407 5366 ath10k_wmi_event_peer_sta_kickout(ar, skb); 5408 5367 break; 5409 5368 case WMI_10_4_ROAM_EVENTID: 5410 5369 ath10k_wmi_event_roam(ar, skb); 5370 + ath10k_wmi_queue_set_coverage_class_work(ar); 5411 5371 break; 5412 5372 case WMI_10_4_HOST_SWBA_EVENTID: 5413 5373 ath10k_wmi_event_host_swba(ar, skb); ··· 5419 5375 break; 5420 5376 case WMI_10_4_DEBUG_PRINT_EVENTID: 5421 5377 ath10k_wmi_event_debug_print(ar, skb); 5378 + ath10k_wmi_queue_set_coverage_class_work(ar); 5422 5379 break; 5423 5380 case WMI_10_4_VDEV_START_RESP_EVENTID: 5424 5381 ath10k_wmi_event_vdev_start_resp(ar, skb); 5382 + ath10k_wmi_queue_set_coverage_class_work(ar); 5425 5383 break; 5426 5384 case WMI_10_4_VDEV_STOPPED_EVENTID: 5427 5385 ath10k_wmi_event_vdev_stopped(ar, skb); 5386 + ath10k_wmi_queue_set_coverage_class_work(ar); 5428 5387 break; 5429 5388 case WMI_10_4_WOW_WAKEUP_HOST_EVENTID: 5430 5389 case WMI_10_4_PEER_RATECODE_LIST_EVENTID: ··· 5443 5396 break; 5444 5397 case WMI_10_4_PDEV_BSS_CHAN_INFO_EVENTID: 5445 5398 ath10k_wmi_event_pdev_bss_chan_info(ar, skb); 5399 + break; 5400 + case WMI_10_4_PDEV_TPC_CONFIG_EVENTID: 5401 + ath10k_wmi_event_pdev_tpc_config(ar, skb); 5446 5402 break; 5447 5403 default: 5448 5404 ath10k_warn(ar, "Unknown eventid: %d\n", id); ··· 6146 6096 | WMI_SCAN_EVENT_COMPLETED 6147 6097 | WMI_SCAN_EVENT_BSS_CHANNEL 6148 6098 | WMI_SCAN_EVENT_FOREIGN_CHANNEL 6099 + | WMI_SCAN_EVENT_FOREIGN_CHANNEL_EXIT 6149 6100 | WMI_SCAN_EVENT_DEQUEUED; 6150 6101 arg->scan_ctrl_flags |= WMI_SCAN_CHAN_STAT_EVENT; 6151 6102 arg->n_bssids = 1; ··· 8204 8153 .get_vdev_subtype = ath10k_wmi_10_4_op_get_vdev_subtype, 8205 8154 .gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info, 8206 8155 .gen_echo = ath10k_wmi_op_gen_echo, 8156 + .gen_pdev_get_tpc_config = ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config, 8207 8157 }; 8208 8158 8209 8159 int ath10k_wmi_attach(struct ath10k *ar)
+14 -1
drivers/net/wireless/ath/ath6kl/sdio.c
··· 75 75 #define CMD53_ARG_FIXED_ADDRESS 0 76 76 #define CMD53_ARG_INCR_ADDRESS 1 77 77 78 + static int ath6kl_sdio_config(struct ath6kl *ar); 79 + 78 80 static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar) 79 81 { 80 82 return ar->hif_priv; ··· 528 526 */ 529 527 msleep(10); 530 528 529 + ret = ath6kl_sdio_config(ar); 530 + if (ret) { 531 + ath6kl_err("Failed to config sdio: %d\n", ret); 532 + goto out; 533 + } 534 + 531 535 ar_sdio->is_disabled = false; 532 536 537 + out: 533 538 return ret; 534 539 } 535 540 ··· 712 703 * ath6kl_hif_rw_comp_handler() with status -ECANCELED so 713 704 * that the packet is properly freed? 714 705 */ 715 - if (s_req->busrequest) 706 + if (s_req->busrequest) { 707 + s_req->busrequest->scat_req = 0; 716 708 ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest); 709 + } 717 710 kfree(s_req->virt_dma_buf); 718 711 kfree(s_req->sgentries); 719 712 kfree(s_req); ··· 723 712 spin_lock_bh(&ar_sdio->scat_lock); 724 713 } 725 714 spin_unlock_bh(&ar_sdio->scat_lock); 715 + 716 + ar_sdio->scatter_enabled = false; 726 717 } 727 718 728 719 /* setup of HIF scatter resources */
+1 -1
drivers/net/wireless/ath/ath9k/rng.c
··· 22 22 #include "ar9003_phy.h" 23 23 24 24 #define ATH9K_RNG_BUF_SIZE 320 25 - #define ATH9K_RNG_ENTROPY(x) (((x) * 8 * 320) >> 10) /* quality: 320/1024 */ 25 + #define ATH9K_RNG_ENTROPY(x) (((x) * 8 * 10) >> 5) /* quality: 10/32 */ 26 26 27 27 static int ath9k_rng_data_read(struct ath_softc *sc, u32 *buf, u32 buf_size) 28 28 {
+2 -1
drivers/net/wireless/ath/regd.c
··· 449 449 } 450 450 } 451 451 452 - static u16 ath_regd_find_country_by_name(char *alpha2) 452 + u16 ath_regd_find_country_by_name(char *alpha2) 453 453 { 454 454 unsigned int i; 455 455 ··· 460 460 461 461 return -1; 462 462 } 463 + EXPORT_SYMBOL(ath_regd_find_country_by_name); 463 464 464 465 static int __ath_reg_dyn_country(struct wiphy *wiphy, 465 466 struct ath_regulatory *reg,
+1
drivers/net/wireless/ath/regd.h
··· 251 251 252 252 bool ath_is_world_regd(struct ath_regulatory *reg); 253 253 bool ath_is_49ghz_allowed(u16 redomain); 254 + u16 ath_regd_find_country_by_name(char *alpha2); 254 255 int ath_regd_init(struct ath_regulatory *reg, struct wiphy *wiphy, 255 256 void (*reg_notifier)(struct wiphy *wiphy, 256 257 struct regulatory_request *request));