tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'icc-sdm670' into icc-next
* icc-sdm670
dt-bindings: interconnect: add sdm670 interconnects
interconnect: qcom: add sdm670 interconnects
Link: https://lore.kernel.org/r/20230111005155.50452-1-mailingradian@gmail.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
+970
-35
+2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
···
27
27
- qcom,sc7280-cpu-bwmon
28
28
- qcom,sc8280xp-cpu-bwmon
29
29
- qcom,sdm845-bwmon
30
+
- qcom,sm8550-cpu-bwmon
30
31
- const: qcom,msm8998-bwmon
31
32
- const: qcom,msm8998-bwmon # BWMON v4
32
33
- items:
33
34
- enum:
34
35
- qcom,sc8280xp-llcc-bwmon
36
+
- qcom,sm8550-llcc-bwmon
35
37
- const: qcom,sc7280-llcc-bwmon
36
38
- const: qcom,sc7280-llcc-bwmon # BWMON v5
37
39
- const: qcom,sdm845-llcc-bwmon # BWMON v5
+1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+8
-35
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+8
-35
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
···
39
39
- qcom,sc7180-npu-noc
40
40
- qcom,sc7180-qup-virt
41
41
- qcom,sc7180-system-noc
42
-
- qcom,sc7280-aggre1-noc
43
-
- qcom,sc7280-aggre2-noc
44
-
- qcom,sc7280-clk-virt
45
-
- qcom,sc7280-cnoc2
46
-
- qcom,sc7280-cnoc3
47
-
- qcom,sc7280-dc-noc
48
-
- qcom,sc7280-gem-noc
49
-
- qcom,sc7280-lpass-ag-noc
50
-
- qcom,sc7280-mc-virt
51
-
- qcom,sc7280-mmss-noc
52
-
- qcom,sc7280-nsp-noc
53
-
- qcom,sc7280-system-noc
54
42
- qcom,sc8180x-aggre1-noc
55
43
- qcom,sc8180x-aggre2-noc
56
44
- qcom,sc8180x-camnoc-virt
···
50
62
- qcom,sc8180x-mmss-noc
51
63
- qcom,sc8180x-qup-virt
52
64
- qcom,sc8180x-system-noc
53
-
- qcom,sc8280xp-aggre1-noc
54
-
- qcom,sc8280xp-aggre2-noc
55
-
- qcom,sc8280xp-clk-virt
56
-
- qcom,sc8280xp-config-noc
57
-
- qcom,sc8280xp-dc-noc
58
-
- qcom,sc8280xp-gem-noc
59
-
- qcom,sc8280xp-lpass-ag-noc
60
-
- qcom,sc8280xp-mc-virt
61
-
- qcom,sc8280xp-mmss-noc
62
-
- qcom,sc8280xp-nspa-noc
63
-
- qcom,sc8280xp-nspb-noc
64
-
- qcom,sc8280xp-system-noc
65
+
- qcom,sdm670-aggre1-noc
66
+
- qcom,sdm670-aggre2-noc
67
+
- qcom,sdm670-config-noc
68
+
- qcom,sdm670-dc-noc
69
+
- qcom,sdm670-gladiator-noc
70
+
- qcom,sdm670-mem-noc
71
+
- qcom,sdm670-mmss-noc
72
+
- qcom,sdm670-system-noc
65
73
- qcom,sdm845-aggre1-noc
66
74
- qcom,sdm845-aggre2-noc
67
75
- qcom,sdm845-config-noc
···
102
118
- qcom,sm8350-mmss-noc
103
119
- qcom,sm8350-compute-noc
104
120
- qcom,sm8350-system-noc
105
-
- qcom,sm8450-aggre1-noc
106
-
- qcom,sm8450-aggre2-noc
107
-
- qcom,sm8450-clk-virt
108
-
- qcom,sm8450-config-noc
109
-
- qcom,sm8450-gem-noc
110
-
- qcom,sm8450-lpass-ag-noc
111
-
- qcom,sm8450-mc-virt
112
-
- qcom,sm8450-mmss-noc
113
-
- qcom,sm8450-nsp-noc
114
-
- qcom,sm8450-pcie-anoc
115
-
- qcom,sm8450-system-noc
116
121
117
122
'#interconnect-cells': true
118
123
+71
Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
+71
Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
12
+
13
+
description: |
14
+
RPMh interconnect providers support system bandwidth requirements through
15
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
16
+
17
+
See also:: include/dt-bindings/interconnect/qcom,sc7280.h
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,sc7280-aggre1-noc
23
+
- qcom,sc7280-aggre2-noc
24
+
- qcom,sc7280-clk-virt
25
+
- qcom,sc7280-cnoc2
26
+
- qcom,sc7280-cnoc3
27
+
- qcom,sc7280-dc-noc
28
+
- qcom,sc7280-gem-noc
29
+
- qcom,sc7280-lpass-ag-noc
30
+
- qcom,sc7280-mc-virt
31
+
- qcom,sc7280-mmss-noc
32
+
- qcom,sc7280-nsp-noc
33
+
- qcom,sc7280-system-noc
34
+
35
+
reg:
36
+
maxItems: 1
37
+
38
+
required:
39
+
- compatible
40
+
41
+
allOf:
42
+
- $ref: qcom,rpmh-common.yaml#
43
+
- if:
44
+
properties:
45
+
compatible:
46
+
contains:
47
+
enum:
48
+
- qcom,sc7280-clk-virt
49
+
then:
50
+
properties:
51
+
reg: false
52
+
else:
53
+
required:
54
+
- reg
55
+
56
+
unevaluatedProperties: false
57
+
58
+
examples:
59
+
- |
60
+
interconnect {
61
+
compatible = "qcom,sc7280-clk-virt";
62
+
#interconnect-cells = <2>;
63
+
qcom,bcm-voters = <&apps_bcm_voter>;
64
+
};
65
+
66
+
interconnect@9100000 {
67
+
reg = <0x9100000 0xe2200>;
68
+
compatible = "qcom,sc7280-gem-noc";
69
+
#interconnect-cells = <2>;
70
+
qcom,bcm-voters = <&apps_bcm_voter>;
71
+
};
+49
Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml
+49
Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sc8280xp-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
12
+
13
+
description: |
14
+
RPMh interconnect providers support system bandwidth requirements through
15
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
16
+
17
+
See also:: include/dt-bindings/interconnect/qcom,sc8280xp.h
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,sc8280xp-aggre1-noc
23
+
- qcom,sc8280xp-aggre2-noc
24
+
- qcom,sc8280xp-clk-virt
25
+
- qcom,sc8280xp-config-noc
26
+
- qcom,sc8280xp-dc-noc
27
+
- qcom,sc8280xp-gem-noc
28
+
- qcom,sc8280xp-lpass-ag-noc
29
+
- qcom,sc8280xp-mc-virt
30
+
- qcom,sc8280xp-mmss-noc
31
+
- qcom,sc8280xp-nspa-noc
32
+
- qcom,sc8280xp-nspb-noc
33
+
- qcom,sc8280xp-system-noc
34
+
35
+
required:
36
+
- compatible
37
+
38
+
allOf:
39
+
- $ref: qcom,rpmh-common.yaml#
40
+
41
+
unevaluatedProperties: false
42
+
43
+
examples:
44
+
- |
45
+
interconnect-0 {
46
+
compatible = "qcom,sc8280xp-aggre1-noc";
47
+
#interconnect-cells = <2>;
48
+
qcom,bcm-voters = <&apps_bcm_voter>;
49
+
};
+124
Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml
+124
Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
12
+
13
+
description: |
14
+
RPMh interconnect providers support system bandwidth requirements through
15
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
16
+
17
+
See also:: include/dt-bindings/interconnect/qcom,sm8450.h
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,sm8450-aggre1-noc
23
+
- qcom,sm8450-aggre2-noc
24
+
- qcom,sm8450-clk-virt
25
+
- qcom,sm8450-config-noc
26
+
- qcom,sm8450-gem-noc
27
+
- qcom,sm8450-lpass-ag-noc
28
+
- qcom,sm8450-mc-virt
29
+
- qcom,sm8450-mmss-noc
30
+
- qcom,sm8450-nsp-noc
31
+
- qcom,sm8450-pcie-anoc
32
+
- qcom,sm8450-system-noc
33
+
34
+
reg:
35
+
maxItems: 1
36
+
37
+
clocks:
38
+
minItems: 1
39
+
maxItems: 4
40
+
41
+
required:
42
+
- compatible
43
+
44
+
allOf:
45
+
- $ref: qcom,rpmh-common.yaml#
46
+
- if:
47
+
properties:
48
+
compatible:
49
+
contains:
50
+
enum:
51
+
- qcom,sm8450-clk-virt
52
+
- qcom,sm8450-mc-virt
53
+
then:
54
+
properties:
55
+
reg: false
56
+
else:
57
+
required:
58
+
- reg
59
+
60
+
- if:
61
+
properties:
62
+
compatible:
63
+
contains:
64
+
enum:
65
+
- qcom,sm8450-aggre1-noc
66
+
then:
67
+
properties:
68
+
clocks:
69
+
items:
70
+
- description: aggre UFS PHY AXI clock
71
+
- description: aggre USB3 PRIM AXI clock
72
+
73
+
- if:
74
+
properties:
75
+
compatible:
76
+
contains:
77
+
enum:
78
+
- qcom,sm8450-aggre2-noc
79
+
then:
80
+
properties:
81
+
clocks:
82
+
items:
83
+
- description: aggre-NOC PCIe 0 AXI clock
84
+
- description: aggre-NOC PCIe 1 AXI clock
85
+
- description: aggre UFS PHY AXI clock
86
+
- description: RPMH CC IPA clock
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
enum:
93
+
- qcom,sm8450-aggre1-noc
94
+
- qcom,sm8450-aggre2-noc
95
+
then:
96
+
required:
97
+
- clocks
98
+
else:
99
+
properties:
100
+
clocks: false
101
+
102
+
unevaluatedProperties: false
103
+
104
+
examples:
105
+
- |
106
+
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
107
+
#include <dt-bindings/clock/qcom,rpmh.h>
108
+
109
+
interconnect-0 {
110
+
compatible = "qcom,sm8450-clk-virt";
111
+
#interconnect-cells = <2>;
112
+
qcom,bcm-voters = <&apps_bcm_voter>;
113
+
};
114
+
115
+
interconnect@1700000 {
116
+
compatible = "qcom,sm8450-aggre2-noc";
117
+
reg = <0x01700000 0x31080>;
118
+
#interconnect-cells = <2>;
119
+
qcom,bcm-voters = <&apps_bcm_voter>;
120
+
clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
121
+
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
122
+
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
123
+
<&rpmhcc RPMH_IPA_CLK>;
124
+
};
+9
drivers/interconnect/qcom/Kconfig
+9
drivers/interconnect/qcom/Kconfig
···
137
137
This is a driver for the Qualcomm Network-on-Chip on sdm660-based
138
138
platforms.
139
139
140
+
config INTERCONNECT_QCOM_SDM670
141
+
tristate "Qualcomm SDM670 interconnect driver"
142
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
143
+
select INTERCONNECT_QCOM_RPMH
144
+
select INTERCONNECT_QCOM_BCM_VOTER
145
+
help
146
+
This is a driver for the Qualcomm Network-on-Chip on sdm670-based
147
+
platforms.
148
+
140
149
config INTERCONNECT_QCOM_SDM845
141
150
tristate "Qualcomm SDM845 interconnect driver"
142
151
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
+2
drivers/interconnect/qcom/Makefile
+2
drivers/interconnect/qcom/Makefile
···
18
18
qnoc-sc8180x-objs := sc8180x.o
19
19
qnoc-sc8280xp-objs := sc8280xp.o
20
20
qnoc-sdm660-objs := sdm660.o
21
+
qnoc-sdm670-objs := sdm670.o
21
22
qnoc-sdm845-objs := sdm845.o
22
23
qnoc-sdx55-objs := sdx55.o
23
24
qnoc-sdx65-objs := sdx65.o
···
45
44
obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o
46
45
obj-$(CONFIG_INTERCONNECT_QCOM_SC8280XP) += qnoc-sc8280xp.o
47
46
obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
47
+
obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o
48
48
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
49
49
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
50
50
obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o
+440
drivers/interconnect/qcom/sdm670.c
+440
drivers/interconnect/qcom/sdm670.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/device.h>
7
+
#include <linux/interconnect.h>
8
+
#include <linux/interconnect-provider.h>
9
+
#include <linux/module.h>
10
+
#include <linux/of_platform.h>
11
+
#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
12
+
13
+
#include "bcm-voter.h"
14
+
#include "icc-rpmh.h"
15
+
#include "sdm670.h"
16
+
17
+
DEFINE_QNODE(qhm_a1noc_cfg, SDM670_MASTER_A1NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A1NOC);
18
+
DEFINE_QNODE(qhm_qup1, SDM670_MASTER_BLSP_1, 1, 4, SDM670_SLAVE_A1NOC_SNOC);
19
+
DEFINE_QNODE(qhm_tsif, SDM670_MASTER_TSIF, 1, 4, SDM670_SLAVE_A1NOC_SNOC);
20
+
DEFINE_QNODE(xm_emmc, SDM670_MASTER_EMMC, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
21
+
DEFINE_QNODE(xm_sdc2, SDM670_MASTER_SDCC_2, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
22
+
DEFINE_QNODE(xm_sdc4, SDM670_MASTER_SDCC_4, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
23
+
DEFINE_QNODE(xm_ufs_mem, SDM670_MASTER_UFS_MEM, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
24
+
DEFINE_QNODE(qhm_a2noc_cfg, SDM670_MASTER_A2NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A2NOC);
25
+
DEFINE_QNODE(qhm_qdss_bam, SDM670_MASTER_QDSS_BAM, 1, 4, SDM670_SLAVE_A2NOC_SNOC);
26
+
DEFINE_QNODE(qhm_qup2, SDM670_MASTER_BLSP_2, 1, 4, SDM670_SLAVE_A2NOC_SNOC);
27
+
DEFINE_QNODE(qnm_cnoc, SDM670_MASTER_CNOC_A2NOC, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
28
+
DEFINE_QNODE(qxm_crypto, SDM670_MASTER_CRYPTO_CORE_0, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
29
+
DEFINE_QNODE(qxm_ipa, SDM670_MASTER_IPA, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
30
+
DEFINE_QNODE(xm_qdss_etr, SDM670_MASTER_QDSS_ETR, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
31
+
DEFINE_QNODE(xm_usb3_0, SDM670_MASTER_USB3, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
32
+
DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM670_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
33
+
DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM670_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
34
+
DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM670_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
35
+
DEFINE_QNODE(qhm_spdm, SDM670_MASTER_SPDM, 1, 4, SDM670_SLAVE_CNOC_A2NOC);
36
+
DEFINE_QNODE(qnm_snoc, SDM670_MASTER_SNOC_CNOC, 1, 8, SDM670_SLAVE_TLMM_SOUTH, SDM670_SLAVE_CAMERA_CFG, SDM670_SLAVE_SDCC_4, SDM670_SLAVE_SDCC_2, SDM670_SLAVE_CNOC_MNOC_CFG, SDM670_SLAVE_UFS_MEM_CFG, SDM670_SLAVE_GLM, SDM670_SLAVE_PDM, SDM670_SLAVE_A2NOC_CFG, SDM670_SLAVE_QDSS_CFG, SDM670_SLAVE_DISPLAY_CFG, SDM670_SLAVE_TCSR, SDM670_SLAVE_DCC_CFG, SDM670_SLAVE_CNOC_DDRSS, SDM670_SLAVE_SNOC_CFG, SDM670_SLAVE_SOUTH_PHY_CFG, SDM670_SLAVE_GRAPHICS_3D_CFG, SDM670_SLAVE_VENUS_CFG, SDM670_SLAVE_TSIF, SDM670_SLAVE_CDSP_CFG, SDM670_SLAVE_AOP, SDM670_SLAVE_BLSP_2, SDM670_SLAVE_SERVICE_CNOC, SDM670_SLAVE_USB3, SDM670_SLAVE_IPA_CFG, SDM670_SLAVE_RBCPR_CX_CFG, SDM670_SLAVE_A1NOC_CFG, SDM670_SLAVE_AOSS, SDM670_SLAVE_PRNG, SDM670_SLAVE_VSENSE_CTRL_CFG, SDM670_SLAVE_EMMC_CFG, SDM670_SLAVE_BLSP_1, SDM670_SLAVE_SPDM_WRAPPER, SDM670_SLAVE_CRYPTO_0_CFG, SDM670_SLAVE_PIMEM_CFG, SDM670_SLAVE_TLMM_NORTH, SDM670_SLAVE_CLK_CTL, SDM670_SLAVE_IMEM_CFG);
37
+
DEFINE_QNODE(qhm_cnoc, SDM670_MASTER_CNOC_DC_NOC, 1, 4, SDM670_SLAVE_MEM_NOC_CFG, SDM670_SLAVE_LLCC_CFG);
38
+
DEFINE_QNODE(acm_l3, SDM670_MASTER_AMPSS_M0, 1, 16, SDM670_SLAVE_SERVICE_GNOC, SDM670_SLAVE_GNOC_SNOC, SDM670_SLAVE_GNOC_MEM_NOC);
39
+
DEFINE_QNODE(pm_gnoc_cfg, SDM670_MASTER_GNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_GNOC);
40
+
DEFINE_QNODE(llcc_mc, SDM670_MASTER_LLCC, 2, 4, SDM670_SLAVE_EBI_CH0);
41
+
DEFINE_QNODE(acm_tcu, SDM670_MASTER_TCU_0, 1, 8, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
42
+
DEFINE_QNODE(qhm_memnoc_cfg, SDM670_MASTER_MEM_NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MEM_NOC, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG);
43
+
DEFINE_QNODE(qnm_apps, SDM670_MASTER_GNOC_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC);
44
+
DEFINE_QNODE(qnm_mnoc_hf, SDM670_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC);
45
+
DEFINE_QNODE(qnm_mnoc_sf, SDM670_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
46
+
DEFINE_QNODE(qnm_snoc_gc, SDM670_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM670_SLAVE_LLCC);
47
+
DEFINE_QNODE(qnm_snoc_sf, SDM670_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC);
48
+
DEFINE_QNODE(qxm_gpu, SDM670_MASTER_GRAPHICS_3D, 2, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
49
+
DEFINE_QNODE(qhm_mnoc_cfg, SDM670_MASTER_CNOC_MNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MNOC);
50
+
DEFINE_QNODE(qxm_camnoc_hf0, SDM670_MASTER_CAMNOC_HF0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
51
+
DEFINE_QNODE(qxm_camnoc_hf1, SDM670_MASTER_CAMNOC_HF1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
52
+
DEFINE_QNODE(qxm_camnoc_sf, SDM670_MASTER_CAMNOC_SF, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
53
+
DEFINE_QNODE(qxm_mdp0, SDM670_MASTER_MDP_PORT0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
54
+
DEFINE_QNODE(qxm_mdp1, SDM670_MASTER_MDP_PORT1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
55
+
DEFINE_QNODE(qxm_rot, SDM670_MASTER_ROTATOR, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
56
+
DEFINE_QNODE(qxm_venus0, SDM670_MASTER_VIDEO_P0, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
57
+
DEFINE_QNODE(qxm_venus1, SDM670_MASTER_VIDEO_P1, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
58
+
DEFINE_QNODE(qxm_venus_arm9, SDM670_MASTER_VIDEO_PROC, 1, 8, SDM670_SLAVE_MNOC_SF_MEM_NOC);
59
+
DEFINE_QNODE(qhm_snoc_cfg, SDM670_MASTER_SNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_SNOC);
60
+
DEFINE_QNODE(qnm_aggre1_noc, SDM670_MASTER_A1NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM);
61
+
DEFINE_QNODE(qnm_aggre2_noc, SDM670_MASTER_A2NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM);
62
+
DEFINE_QNODE(qnm_gladiator_sodv, SDM670_MASTER_GNOC_SNOC, 1, 8, SDM670_SLAVE_PIMEM, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM);
63
+
DEFINE_QNODE(qnm_memnoc, SDM670_MASTER_MEM_NOC_SNOC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM);
64
+
DEFINE_QNODE(qxm_pimem, SDM670_MASTER_PIMEM, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC);
65
+
DEFINE_QNODE(xm_gic, SDM670_MASTER_GIC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC);
66
+
DEFINE_QNODE(qns_a1noc_snoc, SDM670_SLAVE_A1NOC_SNOC, 1, 16, SDM670_MASTER_A1NOC_SNOC);
67
+
DEFINE_QNODE(srvc_aggre1_noc, SDM670_SLAVE_SERVICE_A1NOC, 1, 4);
68
+
DEFINE_QNODE(qns_a2noc_snoc, SDM670_SLAVE_A2NOC_SNOC, 1, 16, SDM670_MASTER_A2NOC_SNOC);
69
+
DEFINE_QNODE(srvc_aggre2_noc, SDM670_SLAVE_SERVICE_A2NOC, 1, 4);
70
+
DEFINE_QNODE(qns_camnoc_uncomp, SDM670_SLAVE_CAMNOC_UNCOMP, 1, 32);
71
+
DEFINE_QNODE(qhs_a1_noc_cfg, SDM670_SLAVE_A1NOC_CFG, 1, 4, SDM670_MASTER_A1NOC_CFG);
72
+
DEFINE_QNODE(qhs_a2_noc_cfg, SDM670_SLAVE_A2NOC_CFG, 1, 4, SDM670_MASTER_A2NOC_CFG);
73
+
DEFINE_QNODE(qhs_aop, SDM670_SLAVE_AOP, 1, 4);
74
+
DEFINE_QNODE(qhs_aoss, SDM670_SLAVE_AOSS, 1, 4);
75
+
DEFINE_QNODE(qhs_camera_cfg, SDM670_SLAVE_CAMERA_CFG, 1, 4);
76
+
DEFINE_QNODE(qhs_clk_ctl, SDM670_SLAVE_CLK_CTL, 1, 4);
77
+
DEFINE_QNODE(qhs_compute_dsp_cfg, SDM670_SLAVE_CDSP_CFG, 1, 4);
78
+
DEFINE_QNODE(qhs_cpr_cx, SDM670_SLAVE_RBCPR_CX_CFG, 1, 4);
79
+
DEFINE_QNODE(qhs_crypto0_cfg, SDM670_SLAVE_CRYPTO_0_CFG, 1, 4);
80
+
DEFINE_QNODE(qhs_dcc_cfg, SDM670_SLAVE_DCC_CFG, 1, 4, SDM670_MASTER_CNOC_DC_NOC);
81
+
DEFINE_QNODE(qhs_ddrss_cfg, SDM670_SLAVE_CNOC_DDRSS, 1, 4);
82
+
DEFINE_QNODE(qhs_display_cfg, SDM670_SLAVE_DISPLAY_CFG, 1, 4);
83
+
DEFINE_QNODE(qhs_emmc_cfg, SDM670_SLAVE_EMMC_CFG, 1, 4);
84
+
DEFINE_QNODE(qhs_glm, SDM670_SLAVE_GLM, 1, 4);
85
+
DEFINE_QNODE(qhs_gpuss_cfg, SDM670_SLAVE_GRAPHICS_3D_CFG, 1, 8);
86
+
DEFINE_QNODE(qhs_imem_cfg, SDM670_SLAVE_IMEM_CFG, 1, 4);
87
+
DEFINE_QNODE(qhs_ipa, SDM670_SLAVE_IPA_CFG, 1, 4);
88
+
DEFINE_QNODE(qhs_mnoc_cfg, SDM670_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM670_MASTER_CNOC_MNOC_CFG);
89
+
DEFINE_QNODE(qhs_pdm, SDM670_SLAVE_PDM, 1, 4);
90
+
DEFINE_QNODE(qhs_phy_refgen_south, SDM670_SLAVE_SOUTH_PHY_CFG, 1, 4);
91
+
DEFINE_QNODE(qhs_pimem_cfg, SDM670_SLAVE_PIMEM_CFG, 1, 4);
92
+
DEFINE_QNODE(qhs_prng, SDM670_SLAVE_PRNG, 1, 4);
93
+
DEFINE_QNODE(qhs_qdss_cfg, SDM670_SLAVE_QDSS_CFG, 1, 4);
94
+
DEFINE_QNODE(qhs_qupv3_north, SDM670_SLAVE_BLSP_2, 1, 4);
95
+
DEFINE_QNODE(qhs_qupv3_south, SDM670_SLAVE_BLSP_1, 1, 4);
96
+
DEFINE_QNODE(qhs_sdc2, SDM670_SLAVE_SDCC_2, 1, 4);
97
+
DEFINE_QNODE(qhs_sdc4, SDM670_SLAVE_SDCC_4, 1, 4);
98
+
DEFINE_QNODE(qhs_snoc_cfg, SDM670_SLAVE_SNOC_CFG, 1, 4, SDM670_MASTER_SNOC_CFG);
99
+
DEFINE_QNODE(qhs_spdm, SDM670_SLAVE_SPDM_WRAPPER, 1, 4);
100
+
DEFINE_QNODE(qhs_tcsr, SDM670_SLAVE_TCSR, 1, 4);
101
+
DEFINE_QNODE(qhs_tlmm_north, SDM670_SLAVE_TLMM_NORTH, 1, 4);
102
+
DEFINE_QNODE(qhs_tlmm_south, SDM670_SLAVE_TLMM_SOUTH, 1, 4);
103
+
DEFINE_QNODE(qhs_tsif, SDM670_SLAVE_TSIF, 1, 4);
104
+
DEFINE_QNODE(qhs_ufs_mem_cfg, SDM670_SLAVE_UFS_MEM_CFG, 1, 4);
105
+
DEFINE_QNODE(qhs_usb3_0, SDM670_SLAVE_USB3, 1, 4);
106
+
DEFINE_QNODE(qhs_venus_cfg, SDM670_SLAVE_VENUS_CFG, 1, 4);
107
+
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM670_SLAVE_VSENSE_CTRL_CFG, 1, 4);
108
+
DEFINE_QNODE(qns_cnoc_a2noc, SDM670_SLAVE_CNOC_A2NOC, 1, 8, SDM670_MASTER_CNOC_A2NOC);
109
+
DEFINE_QNODE(srvc_cnoc, SDM670_SLAVE_SERVICE_CNOC, 1, 4);
110
+
DEFINE_QNODE(qhs_llcc, SDM670_SLAVE_LLCC_CFG, 1, 4);
111
+
DEFINE_QNODE(qhs_memnoc, SDM670_SLAVE_MEM_NOC_CFG, 1, 4, SDM670_MASTER_MEM_NOC_CFG);
112
+
DEFINE_QNODE(qns_gladiator_sodv, SDM670_SLAVE_GNOC_SNOC, 1, 8, SDM670_MASTER_GNOC_SNOC);
113
+
DEFINE_QNODE(qns_gnoc_memnoc, SDM670_SLAVE_GNOC_MEM_NOC, 2, 32, SDM670_MASTER_GNOC_MEM_NOC);
114
+
DEFINE_QNODE(srvc_gnoc, SDM670_SLAVE_SERVICE_GNOC, 1, 4);
115
+
DEFINE_QNODE(ebi, SDM670_SLAVE_EBI_CH0, 2, 4);
116
+
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
117
+
DEFINE_QNODE(qns_apps_io, SDM670_SLAVE_MEM_NOC_GNOC, 1, 32);
118
+
DEFINE_QNODE(qns_llcc, SDM670_SLAVE_LLCC, 2, 16, SDM670_MASTER_LLCC);
119
+
DEFINE_QNODE(qns_memnoc_snoc, SDM670_SLAVE_MEM_NOC_SNOC, 1, 8, SDM670_MASTER_MEM_NOC_SNOC);
120
+
DEFINE_QNODE(srvc_memnoc, SDM670_SLAVE_SERVICE_MEM_NOC, 1, 4);
121
+
DEFINE_QNODE(qns2_mem_noc, SDM670_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM670_MASTER_MNOC_SF_MEM_NOC);
122
+
DEFINE_QNODE(qns_mem_noc_hf, SDM670_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM670_MASTER_MNOC_HF_MEM_NOC);
123
+
DEFINE_QNODE(srvc_mnoc, SDM670_SLAVE_SERVICE_MNOC, 1, 4);
124
+
DEFINE_QNODE(qhs_apss, SDM670_SLAVE_APPSS, 1, 8);
125
+
DEFINE_QNODE(qns_cnoc, SDM670_SLAVE_SNOC_CNOC, 1, 8, SDM670_MASTER_SNOC_CNOC);
126
+
DEFINE_QNODE(qns_memnoc_gc, SDM670_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM670_MASTER_SNOC_GC_MEM_NOC);
127
+
DEFINE_QNODE(qns_memnoc_sf, SDM670_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM670_MASTER_SNOC_SF_MEM_NOC);
128
+
DEFINE_QNODE(qxs_imem, SDM670_SLAVE_OCIMEM, 1, 8);
129
+
DEFINE_QNODE(qxs_pimem, SDM670_SLAVE_PIMEM, 1, 8);
130
+
DEFINE_QNODE(srvc_snoc, SDM670_SLAVE_SERVICE_SNOC, 1, 4);
131
+
DEFINE_QNODE(xs_qdss_stm, SDM670_SLAVE_QDSS_STM, 1, 4);
132
+
DEFINE_QNODE(xs_sys_tcu_cfg, SDM670_SLAVE_TCU, 1, 8);
133
+
134
+
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
135
+
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
136
+
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
137
+
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
138
+
DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
139
+
DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
140
+
DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
141
+
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
142
+
DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
143
+
DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
144
+
DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
145
+
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
146
+
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
147
+
DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
148
+
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
149
+
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
150
+
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
151
+
DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
152
+
DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem);
153
+
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
154
+
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc);
155
+
DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc);
156
+
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic);
157
+
DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc);
158
+
159
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
160
+
&bcm_qup0,
161
+
&bcm_sn8,
162
+
};
163
+
164
+
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
165
+
[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
166
+
[MASTER_BLSP_1] = &qhm_qup1,
167
+
[MASTER_TSIF] = &qhm_tsif,
168
+
[MASTER_EMMC] = &xm_emmc,
169
+
[MASTER_SDCC_2] = &xm_sdc2,
170
+
[MASTER_SDCC_4] = &xm_sdc4,
171
+
[MASTER_UFS_MEM] = &xm_ufs_mem,
172
+
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
173
+
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
174
+
};
175
+
176
+
static const struct qcom_icc_desc sdm670_aggre1_noc = {
177
+
.nodes = aggre1_noc_nodes,
178
+
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
179
+
.bcms = aggre1_noc_bcms,
180
+
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
181
+
};
182
+
183
+
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
184
+
&bcm_ce0,
185
+
&bcm_qup0,
186
+
&bcm_sn10,
187
+
};
188
+
189
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
190
+
[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
191
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
192
+
[MASTER_BLSP_2] = &qhm_qup2,
193
+
[MASTER_CNOC_A2NOC] = &qnm_cnoc,
194
+
[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
195
+
[MASTER_IPA] = &qxm_ipa,
196
+
[MASTER_QDSS_ETR] = &xm_qdss_etr,
197
+
[MASTER_USB3] = &xm_usb3_0,
198
+
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
199
+
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
200
+
};
201
+
202
+
static const struct qcom_icc_desc sdm670_aggre2_noc = {
203
+
.nodes = aggre2_noc_nodes,
204
+
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
205
+
.bcms = aggre2_noc_bcms,
206
+
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
207
+
};
208
+
209
+
static struct qcom_icc_bcm * const config_noc_bcms[] = {
210
+
&bcm_cn0,
211
+
};
212
+
213
+
static struct qcom_icc_node * const config_noc_nodes[] = {
214
+
[MASTER_SPDM] = &qhm_spdm,
215
+
[MASTER_SNOC_CNOC] = &qnm_snoc,
216
+
[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
217
+
[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
218
+
[SLAVE_AOP] = &qhs_aop,
219
+
[SLAVE_AOSS] = &qhs_aoss,
220
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
221
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
222
+
[SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
223
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
224
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
225
+
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
226
+
[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
227
+
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
228
+
[SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
229
+
[SLAVE_GLM] = &qhs_glm,
230
+
[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
231
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
232
+
[SLAVE_IPA_CFG] = &qhs_ipa,
233
+
[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
234
+
[SLAVE_PDM] = &qhs_pdm,
235
+
[SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
236
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
237
+
[SLAVE_PRNG] = &qhs_prng,
238
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
239
+
[SLAVE_BLSP_2] = &qhs_qupv3_north,
240
+
[SLAVE_BLSP_1] = &qhs_qupv3_south,
241
+
[SLAVE_SDCC_2] = &qhs_sdc2,
242
+
[SLAVE_SDCC_4] = &qhs_sdc4,
243
+
[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
244
+
[SLAVE_SPDM_WRAPPER] = &qhs_spdm,
245
+
[SLAVE_TCSR] = &qhs_tcsr,
246
+
[SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
247
+
[SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
248
+
[SLAVE_TSIF] = &qhs_tsif,
249
+
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
250
+
[SLAVE_USB3] = &qhs_usb3_0,
251
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
252
+
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
253
+
[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
254
+
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
255
+
};
256
+
257
+
static const struct qcom_icc_desc sdm670_config_noc = {
258
+
.nodes = config_noc_nodes,
259
+
.num_nodes = ARRAY_SIZE(config_noc_nodes),
260
+
.bcms = config_noc_bcms,
261
+
.num_bcms = ARRAY_SIZE(config_noc_bcms),
262
+
};
263
+
264
+
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
265
+
};
266
+
267
+
static struct qcom_icc_node * const dc_noc_nodes[] = {
268
+
[MASTER_CNOC_DC_NOC] = &qhm_cnoc,
269
+
[SLAVE_LLCC_CFG] = &qhs_llcc,
270
+
[SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
271
+
};
272
+
273
+
static const struct qcom_icc_desc sdm670_dc_noc = {
274
+
.nodes = dc_noc_nodes,
275
+
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
276
+
.bcms = dc_noc_bcms,
277
+
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
278
+
};
279
+
280
+
static struct qcom_icc_bcm * const gladiator_noc_bcms[] = {
281
+
};
282
+
283
+
static struct qcom_icc_node * const gladiator_noc_nodes[] = {
284
+
[MASTER_AMPSS_M0] = &acm_l3,
285
+
[MASTER_GNOC_CFG] = &pm_gnoc_cfg,
286
+
[SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
287
+
[SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
288
+
[SLAVE_SERVICE_GNOC] = &srvc_gnoc,
289
+
};
290
+
291
+
static const struct qcom_icc_desc sdm670_gladiator_noc = {
292
+
.nodes = gladiator_noc_nodes,
293
+
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
294
+
.bcms = gladiator_noc_bcms,
295
+
.num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
296
+
};
297
+
298
+
static struct qcom_icc_bcm * const mem_noc_bcms[] = {
299
+
&bcm_acv,
300
+
&bcm_mc0,
301
+
&bcm_sh0,
302
+
&bcm_sh1,
303
+
&bcm_sh2,
304
+
&bcm_sh3,
305
+
&bcm_sh5,
306
+
};
307
+
308
+
static struct qcom_icc_node * const mem_noc_nodes[] = {
309
+
[MASTER_TCU_0] = &acm_tcu,
310
+
[MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
311
+
[MASTER_GNOC_MEM_NOC] = &qnm_apps,
312
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
313
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
314
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
315
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
316
+
[MASTER_GRAPHICS_3D] = &qxm_gpu,
317
+
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
318
+
[SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
319
+
[SLAVE_LLCC] = &qns_llcc,
320
+
[SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
321
+
[SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
322
+
[MASTER_LLCC] = &llcc_mc,
323
+
[SLAVE_EBI_CH0] = &ebi,
324
+
};
325
+
326
+
static const struct qcom_icc_desc sdm670_mem_noc = {
327
+
.nodes = mem_noc_nodes,
328
+
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
329
+
.bcms = mem_noc_bcms,
330
+
.num_bcms = ARRAY_SIZE(mem_noc_bcms),
331
+
};
332
+
333
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
334
+
&bcm_mm0,
335
+
&bcm_mm1,
336
+
&bcm_mm2,
337
+
&bcm_mm3,
338
+
};
339
+
340
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
341
+
[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
342
+
[MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
343
+
[MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
344
+
[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
345
+
[MASTER_MDP_PORT0] = &qxm_mdp0,
346
+
[MASTER_MDP_PORT1] = &qxm_mdp1,
347
+
[MASTER_ROTATOR] = &qxm_rot,
348
+
[MASTER_VIDEO_P0] = &qxm_venus0,
349
+
[MASTER_VIDEO_P1] = &qxm_venus1,
350
+
[MASTER_VIDEO_PROC] = &qxm_venus_arm9,
351
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
352
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
353
+
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
354
+
};
355
+
356
+
static const struct qcom_icc_desc sdm670_mmss_noc = {
357
+
.nodes = mmss_noc_nodes,
358
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
359
+
.bcms = mmss_noc_bcms,
360
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
361
+
};
362
+
363
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
364
+
&bcm_mm1,
365
+
&bcm_sn0,
366
+
&bcm_sn1,
367
+
&bcm_sn10,
368
+
&bcm_sn11,
369
+
&bcm_sn13,
370
+
&bcm_sn2,
371
+
&bcm_sn3,
372
+
&bcm_sn4,
373
+
&bcm_sn5,
374
+
&bcm_sn8,
375
+
};
376
+
377
+
static struct qcom_icc_node * const system_noc_nodes[] = {
378
+
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
379
+
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
380
+
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
381
+
[MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
382
+
[MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
383
+
[MASTER_PIMEM] = &qxm_pimem,
384
+
[MASTER_GIC] = &xm_gic,
385
+
[SLAVE_APPSS] = &qhs_apss,
386
+
[SLAVE_SNOC_CNOC] = &qns_cnoc,
387
+
[SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
388
+
[SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
389
+
[SLAVE_OCIMEM] = &qxs_imem,
390
+
[SLAVE_PIMEM] = &qxs_pimem,
391
+
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
392
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
393
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
394
+
[MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
395
+
[MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
396
+
[MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
397
+
[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
398
+
};
399
+
400
+
static const struct qcom_icc_desc sdm670_system_noc = {
401
+
.nodes = system_noc_nodes,
402
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
403
+
.bcms = system_noc_bcms,
404
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
405
+
};
406
+
407
+
static const struct of_device_id qnoc_of_match[] = {
408
+
{ .compatible = "qcom,sdm670-aggre1-noc",
409
+
.data = &sdm670_aggre1_noc},
410
+
{ .compatible = "qcom,sdm670-aggre2-noc",
411
+
.data = &sdm670_aggre2_noc},
412
+
{ .compatible = "qcom,sdm670-config-noc",
413
+
.data = &sdm670_config_noc},
414
+
{ .compatible = "qcom,sdm670-dc-noc",
415
+
.data = &sdm670_dc_noc},
416
+
{ .compatible = "qcom,sdm670-gladiator-noc",
417
+
.data = &sdm670_gladiator_noc},
418
+
{ .compatible = "qcom,sdm670-mem-noc",
419
+
.data = &sdm670_mem_noc},
420
+
{ .compatible = "qcom,sdm670-mmss-noc",
421
+
.data = &sdm670_mmss_noc},
422
+
{ .compatible = "qcom,sdm670-system-noc",
423
+
.data = &sdm670_system_noc},
424
+
{ }
425
+
};
426
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
427
+
428
+
static struct platform_driver qnoc_driver = {
429
+
.probe = qcom_icc_rpmh_probe,
430
+
.remove = qcom_icc_rpmh_remove,
431
+
.driver = {
432
+
.name = "qnoc-sdm670",
433
+
.of_match_table = qnoc_of_match,
434
+
.sync_state = icc_sync_state,
435
+
},
436
+
};
437
+
module_platform_driver(qnoc_driver);
438
+
439
+
MODULE_DESCRIPTION("Qualcomm SDM670 NoC driver");
440
+
MODULE_LICENSE("GPL");
+128
drivers/interconnect/qcom/sdm670.h
+128
drivers/interconnect/qcom/sdm670.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Qualcomm #define SDM670 interconnect IDs
4
+
*
5
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
6
+
*/
7
+
8
+
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H
9
+
#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H
10
+
11
+
#define SDM670_MASTER_A1NOC_CFG 0
12
+
#define SDM670_MASTER_A1NOC_SNOC 1
13
+
#define SDM670_MASTER_A2NOC_CFG 2
14
+
#define SDM670_MASTER_A2NOC_SNOC 3
15
+
#define SDM670_MASTER_AMPSS_M0 4
16
+
#define SDM670_MASTER_BLSP_1 5
17
+
#define SDM670_MASTER_BLSP_2 6
18
+
#define SDM670_MASTER_CAMNOC_HF0 7
19
+
#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8
20
+
#define SDM670_MASTER_CAMNOC_HF1 9
21
+
#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10
22
+
#define SDM670_MASTER_CAMNOC_SF 11
23
+
#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12
24
+
#define SDM670_MASTER_CNOC_A2NOC 13
25
+
#define SDM670_MASTER_CNOC_DC_NOC 14
26
+
#define SDM670_MASTER_CNOC_MNOC_CFG 15
27
+
#define SDM670_MASTER_CRYPTO_CORE_0 16
28
+
#define SDM670_MASTER_EMMC 17
29
+
#define SDM670_MASTER_GIC 18
30
+
#define SDM670_MASTER_GNOC_CFG 19
31
+
#define SDM670_MASTER_GNOC_MEM_NOC 20
32
+
#define SDM670_MASTER_GNOC_SNOC 21
33
+
#define SDM670_MASTER_GRAPHICS_3D 22
34
+
#define SDM670_MASTER_IPA 23
35
+
#define SDM670_MASTER_LLCC 24
36
+
#define SDM670_MASTER_MDP_PORT0 25
37
+
#define SDM670_MASTER_MDP_PORT1 26
38
+
#define SDM670_MASTER_MEM_NOC_CFG 27
39
+
#define SDM670_MASTER_MEM_NOC_SNOC 28
40
+
#define SDM670_MASTER_MNOC_HF_MEM_NOC 29
41
+
#define SDM670_MASTER_MNOC_SF_MEM_NOC 30
42
+
#define SDM670_MASTER_PIMEM 31
43
+
#define SDM670_MASTER_QDSS_BAM 32
44
+
#define SDM670_MASTER_QDSS_ETR 33
45
+
#define SDM670_MASTER_ROTATOR 34
46
+
#define SDM670_MASTER_SDCC_2 35
47
+
#define SDM670_MASTER_SDCC_4 36
48
+
#define SDM670_MASTER_SNOC_CFG 37
49
+
#define SDM670_MASTER_SNOC_CNOC 38
50
+
#define SDM670_MASTER_SNOC_GC_MEM_NOC 39
51
+
#define SDM670_MASTER_SNOC_SF_MEM_NOC 40
52
+
#define SDM670_MASTER_SPDM 41
53
+
#define SDM670_MASTER_TCU_0 42
54
+
#define SDM670_MASTER_TSIF 43
55
+
#define SDM670_MASTER_UFS_MEM 44
56
+
#define SDM670_MASTER_USB3 45
57
+
#define SDM670_MASTER_VIDEO_P0 46
58
+
#define SDM670_MASTER_VIDEO_P1 47
59
+
#define SDM670_MASTER_VIDEO_PROC 48
60
+
#define SDM670_SLAVE_A1NOC_CFG 49
61
+
#define SDM670_SLAVE_A1NOC_SNOC 50
62
+
#define SDM670_SLAVE_A2NOC_CFG 51
63
+
#define SDM670_SLAVE_A2NOC_SNOC 52
64
+
#define SDM670_SLAVE_AOP 53
65
+
#define SDM670_SLAVE_AOSS 54
66
+
#define SDM670_SLAVE_APPSS 55
67
+
#define SDM670_SLAVE_BLSP_1 56
68
+
#define SDM670_SLAVE_BLSP_2 57
69
+
#define SDM670_SLAVE_CAMERA_CFG 58
70
+
#define SDM670_SLAVE_CAMNOC_UNCOMP 59
71
+
#define SDM670_SLAVE_CDSP_CFG 60
72
+
#define SDM670_SLAVE_CLK_CTL 61
73
+
#define SDM670_SLAVE_CNOC_A2NOC 62
74
+
#define SDM670_SLAVE_CNOC_DDRSS 63
75
+
#define SDM670_SLAVE_CNOC_MNOC_CFG 64
76
+
#define SDM670_SLAVE_CRYPTO_0_CFG 65
77
+
#define SDM670_SLAVE_DCC_CFG 66
78
+
#define SDM670_SLAVE_DISPLAY_CFG 67
79
+
#define SDM670_SLAVE_EBI_CH0 68
80
+
#define SDM670_SLAVE_EMMC_CFG 69
81
+
#define SDM670_SLAVE_GLM 70
82
+
#define SDM670_SLAVE_GNOC_MEM_NOC 71
83
+
#define SDM670_SLAVE_GNOC_SNOC 72
84
+
#define SDM670_SLAVE_GRAPHICS_3D_CFG 73
85
+
#define SDM670_SLAVE_IMEM_CFG 74
86
+
#define SDM670_SLAVE_IPA_CFG 75
87
+
#define SDM670_SLAVE_LLCC 76
88
+
#define SDM670_SLAVE_LLCC_CFG 77
89
+
#define SDM670_SLAVE_MEM_NOC_CFG 78
90
+
#define SDM670_SLAVE_MEM_NOC_GNOC 79
91
+
#define SDM670_SLAVE_MEM_NOC_SNOC 80
92
+
#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81
93
+
#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82
94
+
#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83
95
+
#define SDM670_SLAVE_OCIMEM 84
96
+
#define SDM670_SLAVE_PDM 85
97
+
#define SDM670_SLAVE_PIMEM 86
98
+
#define SDM670_SLAVE_PIMEM_CFG 87
99
+
#define SDM670_SLAVE_PRNG 88
100
+
#define SDM670_SLAVE_QDSS_CFG 89
101
+
#define SDM670_SLAVE_QDSS_STM 90
102
+
#define SDM670_SLAVE_RBCPR_CX_CFG 91
103
+
#define SDM670_SLAVE_SDCC_2 92
104
+
#define SDM670_SLAVE_SDCC_4 93
105
+
#define SDM670_SLAVE_SERVICE_A1NOC 94
106
+
#define SDM670_SLAVE_SERVICE_A2NOC 95
107
+
#define SDM670_SLAVE_SERVICE_CNOC 96
108
+
#define SDM670_SLAVE_SERVICE_GNOC 97
109
+
#define SDM670_SLAVE_SERVICE_MEM_NOC 98
110
+
#define SDM670_SLAVE_SERVICE_MNOC 99
111
+
#define SDM670_SLAVE_SERVICE_SNOC 100
112
+
#define SDM670_SLAVE_SNOC_CFG 101
113
+
#define SDM670_SLAVE_SNOC_CNOC 102
114
+
#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103
115
+
#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104
116
+
#define SDM670_SLAVE_SOUTH_PHY_CFG 105
117
+
#define SDM670_SLAVE_SPDM_WRAPPER 106
118
+
#define SDM670_SLAVE_TCSR 107
119
+
#define SDM670_SLAVE_TCU 108
120
+
#define SDM670_SLAVE_TLMM_NORTH 109
121
+
#define SDM670_SLAVE_TLMM_SOUTH 110
122
+
#define SDM670_SLAVE_TSIF 111
123
+
#define SDM670_SLAVE_UFS_MEM_CFG 112
124
+
#define SDM670_SLAVE_USB3 113
125
+
#define SDM670_SLAVE_VENUS_CFG 114
126
+
#define SDM670_SLAVE_VSENSE_CTRL_CFG 115
127
+
128
+
#endif
+136
include/dt-bindings/interconnect/qcom,sdm670-rpmh.h
+136
include/dt-bindings/interconnect/qcom,sdm670-rpmh.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Qualcomm SDM670 interconnect IDs
4
+
*
5
+
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H
9
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H
10
+
11
+
#define MASTER_A1NOC_CFG 0
12
+
#define MASTER_BLSP_1 1
13
+
#define MASTER_TSIF 2
14
+
#define MASTER_EMMC 3
15
+
#define MASTER_SDCC_2 4
16
+
#define MASTER_SDCC_4 5
17
+
#define MASTER_UFS_MEM 6
18
+
#define SLAVE_A1NOC_SNOC 7
19
+
#define SLAVE_SERVICE_A1NOC 8
20
+
21
+
#define MASTER_A2NOC_CFG 0
22
+
#define MASTER_QDSS_BAM 1
23
+
#define MASTER_BLSP_2 2
24
+
#define MASTER_CNOC_A2NOC 3
25
+
#define MASTER_CRYPTO_CORE_0 4
26
+
#define MASTER_IPA 5
27
+
#define MASTER_QDSS_ETR 6
28
+
#define MASTER_USB3 7
29
+
#define SLAVE_A2NOC_SNOC 8
30
+
#define SLAVE_SERVICE_A2NOC 9
31
+
32
+
33
+
#define MASTER_SPDM 0
34
+
#define MASTER_SNOC_CNOC 1
35
+
#define SLAVE_A1NOC_CFG 2
36
+
#define SLAVE_A2NOC_CFG 3
37
+
#define SLAVE_AOP 4
38
+
#define SLAVE_AOSS 5
39
+
#define SLAVE_CAMERA_CFG 6
40
+
#define SLAVE_CLK_CTL 7
41
+
#define SLAVE_CDSP_CFG 8
42
+
#define SLAVE_RBCPR_CX_CFG 9
43
+
#define SLAVE_CRYPTO_0_CFG 10
44
+
#define SLAVE_DCC_CFG 11
45
+
#define SLAVE_CNOC_DDRSS 12
46
+
#define SLAVE_DISPLAY_CFG 13
47
+
#define SLAVE_EMMC_CFG 14
48
+
#define SLAVE_GLM 15
49
+
#define SLAVE_GRAPHICS_3D_CFG 16
50
+
#define SLAVE_IMEM_CFG 17
51
+
#define SLAVE_IPA_CFG 18
52
+
#define SLAVE_CNOC_MNOC_CFG 19
53
+
#define SLAVE_PDM 20
54
+
#define SLAVE_SOUTH_PHY_CFG 21
55
+
#define SLAVE_PIMEM_CFG 22
56
+
#define SLAVE_PRNG 23
57
+
#define SLAVE_QDSS_CFG 24
58
+
#define SLAVE_BLSP_2 25
59
+
#define SLAVE_BLSP_1 26
60
+
#define SLAVE_SDCC_2 27
61
+
#define SLAVE_SDCC_4 28
62
+
#define SLAVE_SNOC_CFG 29
63
+
#define SLAVE_SPDM_WRAPPER 30
64
+
#define SLAVE_TCSR 31
65
+
#define SLAVE_TLMM_NORTH 32
66
+
#define SLAVE_TLMM_SOUTH 33
67
+
#define SLAVE_TSIF 34
68
+
#define SLAVE_UFS_MEM_CFG 35
69
+
#define SLAVE_USB3 36
70
+
#define SLAVE_VENUS_CFG 37
71
+
#define SLAVE_VSENSE_CTRL_CFG 38
72
+
#define SLAVE_CNOC_A2NOC 39
73
+
#define SLAVE_SERVICE_CNOC 40
74
+
75
+
#define MASTER_CNOC_DC_NOC 0
76
+
#define SLAVE_LLCC_CFG 1
77
+
#define SLAVE_MEM_NOC_CFG 2
78
+
79
+
#define MASTER_AMPSS_M0 0
80
+
#define MASTER_GNOC_CFG 1
81
+
#define SLAVE_GNOC_SNOC 2
82
+
#define SLAVE_GNOC_MEM_NOC 3
83
+
#define SLAVE_SERVICE_GNOC 4
84
+
85
+
#define MASTER_TCU_0 0
86
+
#define MASTER_MEM_NOC_CFG 1
87
+
#define MASTER_GNOC_MEM_NOC 2
88
+
#define MASTER_MNOC_HF_MEM_NOC 3
89
+
#define MASTER_MNOC_SF_MEM_NOC 4
90
+
#define MASTER_SNOC_GC_MEM_NOC 5
91
+
#define MASTER_SNOC_SF_MEM_NOC 6
92
+
#define MASTER_GRAPHICS_3D 7
93
+
#define SLAVE_MSS_PROC_MS_MPU_CFG 8
94
+
#define SLAVE_MEM_NOC_GNOC 9
95
+
#define SLAVE_LLCC 10
96
+
#define SLAVE_MEM_NOC_SNOC 11
97
+
#define SLAVE_SERVICE_MEM_NOC 12
98
+
#define MASTER_LLCC 13
99
+
#define SLAVE_EBI_CH0 14
100
+
101
+
#define MASTER_CNOC_MNOC_CFG 0
102
+
#define MASTER_CAMNOC_HF0 1
103
+
#define MASTER_CAMNOC_HF1 2
104
+
#define MASTER_CAMNOC_SF 3
105
+
#define MASTER_MDP_PORT0 4
106
+
#define MASTER_MDP_PORT1 5
107
+
#define MASTER_ROTATOR 6
108
+
#define MASTER_VIDEO_P0 7
109
+
#define MASTER_VIDEO_P1 8
110
+
#define MASTER_VIDEO_PROC 9
111
+
#define SLAVE_MNOC_SF_MEM_NOC 10
112
+
#define SLAVE_MNOC_HF_MEM_NOC 11
113
+
#define SLAVE_SERVICE_MNOC 12
114
+
115
+
#define MASTER_SNOC_CFG 0
116
+
#define MASTER_A1NOC_SNOC 1
117
+
#define MASTER_A2NOC_SNOC 2
118
+
#define MASTER_GNOC_SNOC 3
119
+
#define MASTER_MEM_NOC_SNOC 4
120
+
#define MASTER_PIMEM 5
121
+
#define MASTER_GIC 6
122
+
#define SLAVE_APPSS 7
123
+
#define SLAVE_SNOC_CNOC 8
124
+
#define SLAVE_SNOC_MEM_NOC_GC 9
125
+
#define SLAVE_SNOC_MEM_NOC_SF 10
126
+
#define SLAVE_OCIMEM 11
127
+
#define SLAVE_PIMEM 12
128
+
#define SLAVE_SERVICE_SNOC 13
129
+
#define SLAVE_QDSS_STM 14
130
+
#define SLAVE_TCU 15
131
+
#define MASTER_CAMNOC_HF0_UNCOMP 16
132
+
#define MASTER_CAMNOC_HF1_UNCOMP 17
133
+
#define MASTER_CAMNOC_SF_UNCOMP 18
134
+
#define SLAVE_CAMNOC_UNCOMP 19
135
+
136
+
#endif