tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5

Update the SM8650 UFS PHY init tables to support Gear 4 and Gear 5
using the overlays setup (only supported Gear 5 before), and sync
back with the latest Qualcomm recommended values.

The new recommended values allow a solid 50% bump in sequential
read/write benchmarks on the SM8650 QRD & HDK reference boards.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240410-topic-sm8650-upstream-ufs-g5-v1-1-5527c44b37e6@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Neil Armstrong and committed by
Vinod Koul b9251e64 6f9d713f

+68 -15
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
··· 30 30 #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4 31 31 #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc 32 32 #define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220 33 + #define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4 0x240 34 + #define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5 0x244 35 + #define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6 0x248 36 + #define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7 0x24c 33 37 34 38 #endif
+6
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
··· 25 25 #define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0 26 26 #define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4 27 27 #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 28 + #define QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0x1ac 28 29 #define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc 29 30 #define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0 30 31 #define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4 31 32 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 32 33 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c 34 + #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2 0x210 33 35 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 36 + #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4 0x218 34 37 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220 35 38 #define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238 36 39 #define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244 ··· 41 38 #define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260 42 39 #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264 43 40 #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270 41 + #define QSERDES_UFS_V6_RX_MODE_RATE4_B0 0x274 42 + #define QSERDES_UFS_V6_RX_MODE_RATE4_B1 0x278 43 + #define QSERDES_UFS_V6_RX_MODE_RATE4_B2 0x27c 44 44 #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280 45 45 #define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284 46 46 #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
+58 -15
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 862 862 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 863 863 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 864 864 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 865 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 866 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), 865 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 866 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), 867 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a), 868 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17), 869 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 867 870 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 868 871 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 869 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 872 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 870 873 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 871 874 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 872 875 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 873 876 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 874 877 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 875 - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), 878 + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 876 879 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 877 880 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 878 881 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), ··· 883 880 }; 884 881 885 882 static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = { 886 - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), 883 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01), 887 884 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 885 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 888 886 }; 889 887 890 888 static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = { 891 889 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 892 - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f), 893 - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), 894 - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), 895 - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), 890 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 891 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 892 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 893 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 894 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 895 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 896 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 897 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 898 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e), 899 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 900 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce), 901 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce), 902 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18), 896 903 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 904 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f), 897 905 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 898 906 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 899 907 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), ··· 912 898 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 913 899 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 914 900 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 901 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24), 902 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24), 903 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20), 915 904 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 916 - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff), 905 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 917 906 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f), 918 907 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94), 919 908 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa), 909 + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 920 910 }; 921 911 922 912 static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = { 923 - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x00), 913 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 924 914 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 925 915 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1), 926 - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 916 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 917 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 918 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), 919 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), 920 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), 921 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), 922 + }; 923 + 924 + static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = { 925 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x13), 927 926 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 928 927 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 929 - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 930 - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), 931 - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 928 + }; 929 + 930 + static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = { 931 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 932 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05), 933 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05), 934 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d), 935 + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 932 936 }; 933 937 934 938 struct qmp_ufs_offsets { ··· 1507 1475 .pcs = sm8650_ufsphy_pcs, 1508 1476 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs), 1509 1477 }, 1478 + .tbls_hs_overlay[0] = { 1479 + .pcs = sm8650_ufsphy_g4_pcs, 1480 + .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g4_pcs), 1481 + .max_gear = UFS_HS_G4, 1482 + }, 1483 + .tbls_hs_overlay[1] = { 1484 + .pcs = sm8650_ufsphy_g5_pcs, 1485 + .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), 1486 + .max_gear = UFS_HS_G5, 1487 + }, 1488 + 1510 1489 .vreg_list = qmp_phy_vreg_l, 1511 1490 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1512 1491 .regs = ufsphy_v6_regs_layout,