Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Revert "crypto: spacc - Add SPAcc Skcipher support"

This reverts the following commits:

87a3fcf5fec5fb59ec8f23d12a56bcf2b2ee6db7
58bf99100a6dfcc53ba4ab547f1394bb6873b2ac
3b1c9df662915a18a86f1a88364ee70875ed3b44
8bc1bfa02e37d63632f0cb65543e3e71acdccafb
c32f08d024e275059474b3c11c1fc2bc7f2de990
f036dd566453176d4eafb9701ebd69e7e59d6707
c76c9ec333432088a1c6f52650c149530fc5df5d
5d22d37aa8b93efaad797faf80db40ea59453481
b63483b37e813299445d2719488acab2b3f20544
2d6213bd592b4731b53ece3492f9d1d18e97eb5e
fc61c658c94cb7405ca6946d8f2a2b71cef49845
cb67c924b2a7b561bd7f4f2bd66766337c1007b7
06af76b46c78f4729fe2f9712a74502c90d87554
9f1a7ab4d31ef30fbf8adb0985300049469f2270
8ebb14deef0f374f7ca0d34a1ad720ba0a7b79f3
c8981d9230d808e62c65349d0b255c7f4b9087d6

They were submitted with no device tree bindings.

Reported-by: Rob Herring <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

-8343
-1
drivers/crypto/Kconfig
··· 696 696 ahash, and aead algorithms with the kernel cryptographic API. 697 697 698 698 source "drivers/crypto/stm32/Kconfig" 699 - source "drivers/crypto/dwc-spacc/Kconfig" 700 699 701 700 config CRYPTO_DEV_SAFEXCEL 702 701 tristate "Inside Secure's SafeXcel cryptographic engine driver"
-1
drivers/crypto/Makefile
··· 48 48 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/ 49 49 obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/ 50 50 obj-y += xilinx/ 51 - obj-y += dwc-spacc/ 52 51 obj-y += hisilicon/ 53 52 obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/ 54 53 obj-y += intel/
-95
drivers/crypto/dwc-spacc/Kconfig
··· 1 - # SPDX-License-Identifier: GPL-2.0-only 2 - 3 - config CRYPTO_DEV_SPACC 4 - tristate "Support for dw_spacc Security protocol accelerators" 5 - depends on HAS_DMA 6 - default m 7 - 8 - help 9 - This enables support for the HASH/CRYP/AEAD hw accelerator which can be found 10 - on dw_spacc IP. 11 - 12 - config CRYPTO_DEV_SPACC_CIPHER 13 - bool "Enable CIPHER functionality" 14 - depends on CRYPTO_DEV_SPACC 15 - default y 16 - select CRYPTO_SKCIPHER 17 - select CRYPTO_LIB_DES 18 - select CRYPTO_AES 19 - select CRYPTO_CBC 20 - select CRYPTO_ECB 21 - select CRYPTO_CTR 22 - select CRYPTO_XTS 23 - select CRYPTO_CTS 24 - select CRYPTO_OFB 25 - select CRYPTO_CFB 26 - select CRYPTO_SM4_GENERIC 27 - select CRYPTO_CHACHA20 28 - 29 - help 30 - Say y to enable Cipher functionality of SPACC. 31 - 32 - config CRYPTO_DEV_SPACC_HASH 33 - bool "Enable HASH functionality" 34 - depends on CRYPTO_DEV_SPACC 35 - default y 36 - select CRYPTO_HASH 37 - select CRYPTO_SHA1 38 - select CRYPTO_MD5 39 - select CRYPTO_SHA256 40 - select CRYPTO_SHA512 41 - select CRYPTO_HMAC 42 - select CRYPTO_SM3 43 - select CRYPTO_CMAC 44 - select CRYPTO_MICHAEL_MIC 45 - select CRYPTO_XCBC 46 - select CRYPTO_AES 47 - select CRYPTO_SM4_GENERIC 48 - 49 - help 50 - Say y to enable Hash functionality of SPACC. 51 - 52 - config CRYPTO_DEV_SPACC_AEAD 53 - bool "Enable AEAD functionality" 54 - depends on CRYPTO_DEV_SPACC 55 - default y 56 - select CRYPTO_AEAD 57 - select CRYPTO_AUTHENC 58 - select CRYPTO_AES 59 - select CRYPTO_SM4_GENERIC 60 - select CRYPTO_CHACHAPOLY1305 61 - select CRYPTO_GCM 62 - select CRYPTO_CCM 63 - 64 - help 65 - Say y to enable AEAD functionality of SPACC. 66 - 67 - config CRYPTO_DEV_SPACC_AUTODETECT 68 - bool "Enable Autodetect functionality" 69 - depends on CRYPTO_DEV_SPACC 70 - default y 71 - help 72 - Say y to enable Autodetect functionality 73 - 74 - config CRYPTO_DEV_SPACC_DEBUG_TRACE_IO 75 - bool "Enable Trace MMIO reads/writes stats" 76 - depends on CRYPTO_DEV_SPACC 77 - default n 78 - help 79 - Say y to enable Trace MMIO reads/writes stats. 80 - To Debug and trace IO register read/write opration 81 - 82 - config CRYPTO_DEV_SPACC_DEBUG_TRACE_DDT 83 - bool "Enable Trace DDT entries stats" 84 - default n 85 - depends on CRYPTO_DEV_SPACC 86 - help 87 - Say y to enable Enable Trace DDT entries stats. 88 - To Debug and trace DDT opration 89 - 90 - config CRYPTO_DEV_SPACC_SECURE_MODE 91 - bool "Enable Spacc secure mode stats" 92 - default n 93 - depends on CRYPTO_DEV_SPACC 94 - help 95 - Say y to enable Spacc secure modes stats.
-16
drivers/crypto/dwc-spacc/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0-only 2 - obj-$(CONFIG_CRYPTO_DEV_SPACC) += snps-spacc.o 3 - snps-spacc-objs = spacc_hal.o spacc_core.o \ 4 - spacc_manager.o spacc_interrupt.o spacc_device.o 5 - 6 - ifeq ($(CONFIG_CRYPTO_DEV_SPACC_HASH),y) 7 - snps-spacc-objs += spacc_ahash.o 8 - endif 9 - 10 - ifeq ($(CONFIG_CRYPTO_DEV_SPACC_CIPHER),y) 11 - snps-spacc-objs += spacc_skcipher.o 12 - endif 13 - 14 - ifeq ($(CONFIG_CRYPTO_DEV_SPACC_AEAD),y) 15 - snps-spacc-objs += spacc_aead.o 16 - endif
-1243
drivers/crypto/dwc-spacc/spacc_aead.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - 3 - #include <crypto/aes.h> 4 - #include <crypto/sm4.h> 5 - #include <crypto/gcm.h> 6 - #include <crypto/aead.h> 7 - #include <crypto/authenc.h> 8 - #include <crypto/scatterwalk.h> 9 - #include <crypto/internal/aead.h> 10 - #include <linux/platform_device.h> 11 - 12 - #include "spacc_device.h" 13 - #include "spacc_core.h" 14 - 15 - static LIST_HEAD(spacc_aead_alg_list); 16 - static DEFINE_MUTEX(spacc_aead_alg_mutex); 17 - 18 - #define SPACC_B0_SIZE 16 19 - #define SET_IV_IN_SRCBUF 0x80000000 20 - #define SET_IV_IN_CONTEXT 0x0 21 - #define AAD_BUF_SIZE 4096 22 - #define ADATA_BUF_SIZE (AAD_BUF_SIZE + SPACC_B0_SIZE +\ 23 - SPACC_MAX_IV_SIZE) 24 - 25 - struct spacc_iv_buf { 26 - unsigned char iv[SPACC_MAX_IV_SIZE]; 27 - unsigned char spacc_adata[ADATA_BUF_SIZE]; 28 - struct scatterlist sg[2], spacc_adata_sg[2]; 29 - struct scatterlist *spacc_ptextsg, temp_aad[2]; 30 - }; 31 - 32 - static struct kmem_cache *spacc_iv_pool; 33 - 34 - static struct mode_tab possible_aeads[] = { 35 - { MODE_TAB_AEAD("rfc7539(chacha20,poly1305)", 36 - CRYPTO_MODE_CHACHA20_POLY1305, CRYPTO_MODE_NULL, 37 - 16, 12, 1), .keylen = { 16, 24, 32 } 38 - }, 39 - { MODE_TAB_AEAD("gcm(aes)", 40 - CRYPTO_MODE_AES_GCM, CRYPTO_MODE_NULL, 41 - 16, 12, 1), .keylen = { 16, 24, 32 } 42 - }, 43 - { MODE_TAB_AEAD("gcm(sm4)", 44 - CRYPTO_MODE_SM4_GCM, CRYPTO_MODE_NULL, 45 - 16, 12, 1), .keylen = { 16 } 46 - }, 47 - { MODE_TAB_AEAD("ccm(aes)", 48 - CRYPTO_MODE_AES_CCM, CRYPTO_MODE_NULL, 49 - 16, 16, 1), .keylen = { 16, 24, 32 } 50 - }, 51 - { MODE_TAB_AEAD("ccm(sm4)", 52 - CRYPTO_MODE_SM4_CCM, CRYPTO_MODE_NULL, 53 - 16, 16, 1), .keylen = { 16, 24, 32 } 54 - }, 55 - }; 56 - 57 - static void spacc_init_aead_alg(struct crypto_alg *calg, 58 - const struct mode_tab *mode) 59 - { 60 - strscpy(calg->cra_name, mode->name, sizeof(mode->name) - 1); 61 - calg->cra_name[sizeof(mode->name) - 1] = '\0'; 62 - 63 - strscpy(calg->cra_driver_name, "spacc-"); 64 - strcat(calg->cra_driver_name, mode->name); 65 - calg->cra_driver_name[sizeof(calg->cra_driver_name) - 1] = '\0'; 66 - 67 - calg->cra_blocksize = mode->blocklen; 68 - } 69 - 70 - static int ccm_16byte_aligned_len(int in_len) 71 - { 72 - int len; 73 - int computed_mod; 74 - 75 - if (in_len > 0) { 76 - computed_mod = in_len % 16; 77 - if (computed_mod) 78 - len = in_len - computed_mod + 16; 79 - else 80 - len = in_len; 81 - } else { 82 - len = in_len; 83 - } 84 - 85 - return len; 86 - } 87 - 88 - /* taken from crypto/ccm.c */ 89 - static int spacc_aead_format_adata(u8 *adata, unsigned int a) 90 - { 91 - int len = 0; 92 - 93 - /* add control info for associated data 94 - * RFC 3610 and NIST Special Publication 800-38C 95 - */ 96 - if (a < 65280) { 97 - *(__be16 *)adata = cpu_to_be16(a); 98 - len = 2; 99 - } else { 100 - *(__be16 *)adata = cpu_to_be16(0xfffe); 101 - *(__be32 *)&adata[2] = cpu_to_be32(a); 102 - len = 6; 103 - } 104 - 105 - return len; 106 - } 107 - 108 - 109 - /* taken from crypto/ccm.c */ 110 - static int spacc_aead_set_msg_len(u8 *block, unsigned int msglen, int csize) 111 - { 112 - __be32 data; 113 - 114 - memset(block, 0, csize); 115 - block += csize; 116 - 117 - if (csize >= 4) 118 - csize = 4; 119 - else if (msglen > (unsigned int)(1 << (8 * csize))) 120 - return -EOVERFLOW; 121 - 122 - data = cpu_to_be32(msglen); 123 - memcpy(block - csize, (u8 *)&data + 4 - csize, csize); 124 - 125 - return 0; 126 - } 127 - 128 - static int spacc_aead_init_dma(struct device *dev, struct aead_request *req, 129 - u64 seq, uint32_t icvlen, int encrypt, int *alen) 130 - { 131 - struct crypto_aead *reqtfm = crypto_aead_reqtfm(req); 132 - struct spacc_crypto_ctx *tctx = crypto_aead_ctx(reqtfm); 133 - struct spacc_crypto_reqctx *ctx = aead_request_ctx(req); 134 - 135 - gfp_t mflags = GFP_ATOMIC; 136 - struct spacc_iv_buf *iv; 137 - int ccm_aad_16b_len = 0; 138 - int rc, B0len; 139 - int payload_len, spacc_adata_sg_buf_len; 140 - unsigned int ivsize = crypto_aead_ivsize(reqtfm); 141 - 142 - /* always have 1 byte of IV */ 143 - if (!ivsize) 144 - ivsize = 1; 145 - 146 - if (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) 147 - mflags = GFP_KERNEL; 148 - 149 - ctx->iv_buf = kmem_cache_alloc(spacc_iv_pool, mflags); 150 - if (!ctx->iv_buf) 151 - return -ENOMEM; 152 - iv = ctx->iv_buf; 153 - 154 - sg_init_table(iv->sg, ARRAY_SIZE(iv->sg)); 155 - sg_init_table(iv->spacc_adata_sg, ARRAY_SIZE(iv->spacc_adata_sg)); 156 - 157 - B0len = 0; 158 - ctx->aead_nents = 0; 159 - 160 - memset(iv->iv, 0, SPACC_MAX_IV_SIZE); 161 - memset(iv->spacc_adata, 0, ADATA_BUF_SIZE); 162 - 163 - /* copy the IV out for AAD */ 164 - memcpy(iv->iv, req->iv, ivsize); 165 - memset(iv->spacc_adata, 0, 144); 166 - 167 - /* now we need to figure out the cipher IV which may or 168 - * may not be "req->iv" depending on the mode we are in 169 - */ 170 - if (tctx->mode & SPACC_MANGLE_IV_FLAG) { 171 - switch (tctx->mode & 0x7F00) { 172 - case SPACC_MANGLE_IV_RFC3686: 173 - case SPACC_MANGLE_IV_RFC4106: 174 - case SPACC_MANGLE_IV_RFC4543: 175 - { 176 - unsigned char *p = iv->spacc_adata; 177 - /* we're in RFC3686 mode so the last 178 - * 4 bytes of the key are the SALT 179 - */ 180 - memcpy(p, tctx->csalt, 4); 181 - memcpy(p + 4, req->iv, ivsize); 182 - 183 - p[12] = 0; 184 - p[13] = 0; 185 - p[14] = 0; 186 - p[15] = 1; 187 - } 188 - break; 189 - case SPACC_MANGLE_IV_RFC4309: 190 - { 191 - unsigned char *p = iv->spacc_adata; 192 - int L, M; 193 - u32 lm = req->cryptlen; 194 - 195 - /* CCM mode */ 196 - /* p[0..15] is the CTR IV */ 197 - /* p[16..31] is the CBC-MAC B0 block*/ 198 - B0len = SPACC_B0_SIZE; 199 - /* IPsec requires L=4*/ 200 - L = 4; 201 - M = tctx->auth_size; 202 - 203 - /* CTR block */ 204 - p[0] = L - 1; 205 - memcpy(p + 1, tctx->csalt, 3); 206 - memcpy(p + 4, req->iv, ivsize); 207 - p[12] = 0; 208 - p[13] = 0; 209 - p[14] = 0; 210 - p[15] = 1; 211 - 212 - /* store B0 block at p[16..31] */ 213 - p[16] = (1 << 6) | (((M - 2) >> 1) << 3) 214 - | (L - 1); 215 - memcpy(p + 1 + 16, tctx->csalt, 3); 216 - memcpy(p + 4 + 16, req->iv, ivsize); 217 - 218 - /* now store length */ 219 - p[16 + 12 + 0] = (lm >> 24) & 0xFF; 220 - p[16 + 12 + 1] = (lm >> 16) & 0xFF; 221 - p[16 + 12 + 2] = (lm >> 8) & 0xFF; 222 - p[16 + 12 + 3] = (lm) & 0xFF; 223 - 224 - /*now store the pre-formatted AAD */ 225 - p[32] = (req->assoclen >> 8) & 0xFF; 226 - p[33] = (req->assoclen) & 0xFF; 227 - /* we added 2 byte header to the AAD */ 228 - B0len += 2; 229 - } 230 - break; 231 - } 232 - } else if (tctx->mode == CRYPTO_MODE_AES_CCM || 233 - tctx->mode == CRYPTO_MODE_SM4_CCM) { 234 - unsigned char *p = iv->spacc_adata; 235 - u8 *orig_iv = req->iv; 236 - int L, M; 237 - 238 - u32 lm = (encrypt) ? 239 - req->cryptlen : 240 - req->cryptlen - tctx->auth_size; 241 - 242 - memset(iv->spacc_adata, 0, 144); 243 - iv->spacc_ptextsg = req->src; 244 - /* CCM mode */ 245 - /* p[0..15] is the CTR IV */ 246 - /* p[16..31] is the CBC-MAC B0 block*/ 247 - B0len = SPACC_B0_SIZE; 248 - 249 - /* IPsec requires L=4 */ 250 - L = req->iv[0] + 1; 251 - M = tctx->auth_size; 252 - 253 - /* Note: rfc 3610 and NIST 800-38C require counter of 254 - * zero to encrypt auth tag. 255 - */ 256 - memset(orig_iv + 15 - orig_iv[0], 0, orig_iv[0] + 1); 257 - 258 - /* CTR block */ 259 - memcpy(p, req->iv, ivsize); 260 - memcpy(p + 16, req->iv, ivsize); 261 - 262 - /* Taken from ccm.c 263 - * Note: rfc 3610 and NIST 800-38C require counter of 264 - * zero to encrypt auth tag. 265 - */ 266 - 267 - /* Store B0 block at p[16..31] */ 268 - p[16] |= (8 * ((M - 2) / 2)); 269 - 270 - /* set adata if assoclen > 0 */ 271 - if (req->assoclen) 272 - p[16] |= 64; 273 - 274 - /* now store length, this is L size starts from 16-L 275 - * to 16 of B0 276 - */ 277 - spacc_aead_set_msg_len(p + 16 + 16 - L, lm, L); 278 - 279 - if (req->assoclen) { 280 - 281 - /* store pre-formatted AAD: 282 - * AAD_LEN + AAD + PAD 283 - */ 284 - *alen = spacc_aead_format_adata(&p[32], req->assoclen); 285 - 286 - ccm_aad_16b_len = 287 - ccm_16byte_aligned_len(req->assoclen + *alen); 288 - 289 - /* Adding the rest of AAD from req->src */ 290 - scatterwalk_map_and_copy(p + 32 + *alen, 291 - req->src, 0, 292 - req->assoclen, 0); 293 - 294 - /* Copy AAD to req->dst */ 295 - scatterwalk_map_and_copy(p + 32 + *alen, req->dst, 296 - 0, req->assoclen, 1); 297 - 298 - iv->spacc_ptextsg = scatterwalk_ffwd(iv->temp_aad, 299 - req->src, req->assoclen); 300 - } 301 - /* default is to copy the iv over since the 302 - * cipher and protocol IV are the same 303 - */ 304 - memcpy(iv->spacc_adata, req->iv, ivsize); 305 - } 306 - 307 - /* this is part of the AAD */ 308 - sg_set_buf(iv->sg, iv->iv, ivsize); 309 - 310 - /* GCM and CCM don't include the IV in the AAD */ 311 - switch (tctx->mode) { 312 - case CRYPTO_MODE_AES_GCM_RFC4106: 313 - case CRYPTO_MODE_AES_GCM: 314 - case CRYPTO_MODE_SM4_GCM_RFC8998: 315 - case CRYPTO_MODE_CHACHA20_POLY1305: 316 - case CRYPTO_MODE_NULL: 317 - 318 - payload_len = req->cryptlen + icvlen + req->assoclen; 319 - spacc_adata_sg_buf_len = SPACC_MAX_IV_SIZE + B0len; 320 - 321 - /* this is the actual IV getting fed to the core 322 - * (via IV IMPORT) 323 - */ 324 - 325 - sg_set_buf(iv->spacc_adata_sg, iv->spacc_adata, 326 - spacc_adata_sg_buf_len); 327 - 328 - sg_chain(iv->spacc_adata_sg, 329 - sg_nents_for_len(iv->spacc_adata_sg, 330 - spacc_adata_sg_buf_len) + 1, req->src); 331 - 332 - rc = spacc_sg_to_ddt(dev, iv->spacc_adata_sg, 333 - spacc_adata_sg_buf_len + payload_len, 334 - &ctx->src, DMA_TO_DEVICE); 335 - 336 - if (rc < 0) 337 - goto err_free_iv; 338 - ctx->aead_nents = rc; 339 - break; 340 - case CRYPTO_MODE_AES_CCM: 341 - case CRYPTO_MODE_AES_CCM_RFC4309: 342 - case CRYPTO_MODE_SM4_CCM: 343 - 344 - 345 - if (encrypt) 346 - payload_len = 347 - ccm_16byte_aligned_len(req->cryptlen + icvlen); 348 - else 349 - payload_len = 350 - ccm_16byte_aligned_len(req->cryptlen); 351 - 352 - spacc_adata_sg_buf_len = SPACC_MAX_IV_SIZE + B0len + 353 - ccm_aad_16b_len; 354 - 355 - /* this is the actual IV getting fed to the core (via IV IMPORT) 356 - * This has CTR IV + B0 + AAD(B1, B2, ...) 357 - */ 358 - sg_set_buf(iv->spacc_adata_sg, iv->spacc_adata, 359 - spacc_adata_sg_buf_len); 360 - sg_chain(iv->spacc_adata_sg, 361 - sg_nents_for_len(iv->spacc_adata_sg, 362 - spacc_adata_sg_buf_len) + 1, 363 - iv->spacc_ptextsg); 364 - 365 - rc = spacc_sg_to_ddt(dev, iv->spacc_adata_sg, 366 - spacc_adata_sg_buf_len + payload_len, 367 - &ctx->src, DMA_TO_DEVICE); 368 - if (rc < 0) 369 - goto err_free_iv; 370 - ctx->aead_nents = rc; 371 - break; 372 - default: 373 - 374 - /* this is the actual IV getting fed to the core (via IV IMPORT) 375 - * This has CTR IV + B0 + AAD(B1, B2, ...) 376 - */ 377 - payload_len = req->cryptlen + icvlen + req->assoclen; 378 - spacc_adata_sg_buf_len = SPACC_MAX_IV_SIZE + B0len; 379 - sg_set_buf(iv->spacc_adata_sg, iv->spacc_adata, 380 - spacc_adata_sg_buf_len); 381 - 382 - sg_chain(iv->spacc_adata_sg, 383 - sg_nents_for_len(iv->spacc_adata_sg, 384 - spacc_adata_sg_buf_len) + 1, 385 - req->src); 386 - 387 - rc = spacc_sg_to_ddt(dev, iv->spacc_adata_sg, 388 - spacc_adata_sg_buf_len + payload_len, 389 - &ctx->src, DMA_TO_DEVICE); 390 - 391 - if (rc < 0) 392 - goto err_free_iv; 393 - ctx->aead_nents = rc; 394 - } 395 - 396 - /* Putting in req->dst is good since it won't overwrite anything 397 - * even in case of CCM this is fine condition 398 - */ 399 - if (req->dst != req->src) { 400 - switch (tctx->mode) { 401 - case CRYPTO_MODE_AES_CCM: 402 - case CRYPTO_MODE_AES_CCM_RFC4309: 403 - case CRYPTO_MODE_SM4_CCM: 404 - /* If req->dst buffer len is not-positive, 405 - * then skip setting up of DMA 406 - */ 407 - if (req->dst->length <= 0) { 408 - ctx->dst_nents = 0; 409 - return 0; 410 - } 411 - 412 - if (encrypt) 413 - payload_len = req->cryptlen + icvlen + 414 - req->assoclen; 415 - else 416 - payload_len = req->cryptlen - tctx->auth_size + 417 - req->assoclen; 418 - 419 - /* For corner cases where PTlen=AADlen=0, we set default 420 - * to 16 421 - */ 422 - rc = spacc_sg_to_ddt(dev, req->dst, 423 - payload_len > 0 ? payload_len : 16, 424 - &ctx->dst, DMA_FROM_DEVICE); 425 - if (rc < 0) 426 - goto err_free_src; 427 - ctx->dst_nents = rc; 428 - break; 429 - default: 430 - 431 - /* If req->dst buffer len is not-positive, 432 - * then skip setting up of DMA 433 - */ 434 - if (req->dst->length <= 0) { 435 - ctx->dst_nents = 0; 436 - return 0; 437 - } 438 - 439 - if (encrypt) 440 - payload_len = SPACC_MAX_IV_SIZE + req->cryptlen 441 - + icvlen + req->assoclen; 442 - else { 443 - payload_len = req->cryptlen - tctx->auth_size + 444 - req->assoclen; 445 - if (payload_len <= 0) 446 - return -EBADMSG; 447 - } 448 - 449 - 450 - rc = spacc_sg_to_ddt(dev, req->dst, 451 - payload_len > 0 ? payload_len : 16, 452 - &ctx->dst, DMA_FROM_DEVICE); 453 - if (rc < 0) 454 - goto err_free_src; 455 - ctx->dst_nents = rc; 456 - } 457 - } 458 - 459 - return 0; 460 - 461 - err_free_src: 462 - if (ctx->aead_nents) { 463 - dma_unmap_sg(dev, iv->spacc_adata_sg, ctx->aead_nents, 464 - DMA_TO_DEVICE); 465 - 466 - pdu_ddt_free(&ctx->src); 467 - } 468 - 469 - err_free_iv: 470 - kmem_cache_free(spacc_iv_pool, ctx->iv_buf); 471 - 472 - return rc; 473 - } 474 - 475 - static void spacc_aead_cleanup_dma(struct device *dev, struct aead_request *req) 476 - { 477 - struct spacc_crypto_reqctx *ctx = aead_request_ctx(req); 478 - struct spacc_iv_buf *iv = ctx->iv_buf; 479 - 480 - if (req->src != req->dst && ctx->dst_nents > 0) { 481 - dma_unmap_sg(dev, req->dst, ctx->dst_nents, 482 - DMA_FROM_DEVICE); 483 - pdu_ddt_free(&ctx->dst); 484 - } 485 - 486 - if (ctx->aead_nents) { 487 - dma_unmap_sg(dev, iv->spacc_adata_sg, ctx->aead_nents, 488 - DMA_TO_DEVICE); 489 - 490 - pdu_ddt_free(&ctx->src); 491 - } 492 - 493 - kmem_cache_free(spacc_iv_pool, ctx->iv_buf); 494 - } 495 - 496 - static bool spacc_check_keylen(const struct spacc_alg *salg, 497 - unsigned int keylen) 498 - { 499 - unsigned int i, mask = salg->keylen_mask; 500 - 501 - if (mask > (1ul << ARRAY_SIZE(salg->mode->keylen)) - 1) 502 - return false; 503 - 504 - for (i = 0; mask; i++, mask >>= 1) { 505 - if (mask & 1 && salg->mode->keylen[i] == keylen) 506 - return true; 507 - } 508 - 509 - return false; 510 - } 511 - 512 - static void spacc_aead_cb(void *spacc, void *tfm) 513 - { 514 - struct aead_cb_data *cb = tfm; 515 - int err = -1; 516 - u32 status_reg = readl(cb->spacc->regmap + SPACC_REG_STATUS); 517 - u32 status_ret = (status_reg >> 24) & 0x3; 518 - 519 - dma_sync_sg_for_cpu(cb->tctx->dev, cb->req->dst, 520 - cb->ctx->dst_nents, DMA_FROM_DEVICE); 521 - 522 - /* ICV mismatch send bad msg */ 523 - if (status_ret == 0x1) { 524 - err = -EBADMSG; 525 - goto REQ_DST_CP_SKIP; 526 - } 527 - err = cb->spacc->job[cb->new_handle].job_err; 528 - 529 - REQ_DST_CP_SKIP: 530 - spacc_aead_cleanup_dma(cb->tctx->dev, cb->req); 531 - spacc_close(cb->spacc, cb->new_handle); 532 - 533 - /* call complete */ 534 - aead_request_complete(cb->req, err); 535 - } 536 - 537 - static int spacc_aead_setkey(struct crypto_aead *tfm, const u8 *key, 538 - unsigned int keylen) 539 - { 540 - struct spacc_crypto_ctx *ctx = crypto_aead_ctx(tfm); 541 - const struct spacc_alg *salg = spacc_tfm_aead(&tfm->base); 542 - struct crypto_authenc_keys authenc_keys; 543 - struct spacc_priv *priv; 544 - unsigned int authkeylen, enckeylen; 545 - const unsigned char *authkey, *enckey; 546 - unsigned char xcbc[64]; 547 - int singlekey = 0; 548 - int err; 549 - 550 - /* are keylens valid? */ 551 - ctx->ctx_valid = false; 552 - 553 - switch (ctx->mode & 0xFF) { 554 - case CRYPTO_MODE_SM4_GCM: 555 - case CRYPTO_MODE_SM4_CCM: 556 - case CRYPTO_MODE_NULL: 557 - case CRYPTO_MODE_AES_GCM: 558 - case CRYPTO_MODE_AES_CCM: 559 - case CRYPTO_MODE_CHACHA20_POLY1305: 560 - authkey = key; 561 - authkeylen = 0; 562 - enckey = key; 563 - enckeylen = keylen; 564 - ctx->keylen = keylen; 565 - singlekey = 1; 566 - goto skipover; 567 - } 568 - 569 - err = crypto_authenc_extractkeys(&authenc_keys, key, keylen); 570 - if (err) 571 - return err; 572 - 573 - authkeylen = authenc_keys.authkeylen; 574 - authkey = authenc_keys.authkey; 575 - enckeylen = authenc_keys.enckeylen; 576 - enckey = authenc_keys.enckey; 577 - 578 - skipover: 579 - /* detect RFC3686/4106 and trim from enckeylen(and copy salt..) */ 580 - if (ctx->mode & SPACC_MANGLE_IV_FLAG) { 581 - switch (ctx->mode & 0x7F00) { 582 - case SPACC_MANGLE_IV_RFC3686: 583 - case SPACC_MANGLE_IV_RFC4106: 584 - case SPACC_MANGLE_IV_RFC4543: 585 - memcpy(ctx->csalt, enckey + enckeylen - 4, 4); 586 - enckeylen -= 4; 587 - break; 588 - case SPACC_MANGLE_IV_RFC4309: 589 - memcpy(ctx->csalt, enckey + enckeylen - 3, 3); 590 - enckeylen -= 3; 591 - break; 592 - } 593 - } 594 - 595 - if (!singlekey) { 596 - if (authkeylen > salg->mode->hashlen) { 597 - dev_warn(ctx->dev, "Auth key size of %u is not valid\n", 598 - authkeylen); 599 - return -EINVAL; 600 - } 601 - } 602 - 603 - if (!spacc_check_keylen(salg, enckeylen)) { 604 - dev_warn(ctx->dev, "Enc key size of %u is not valid\n", 605 - enckeylen); 606 - return -EINVAL; 607 - } 608 - 609 - /* if we're already open close the handle since 610 - * the size may have changed 611 - */ 612 - if (ctx->handle != -1) { 613 - priv = dev_get_drvdata(ctx->dev); 614 - spacc_close(&priv->spacc, ctx->handle); 615 - put_device(ctx->dev); 616 - ctx->handle = -1; 617 - } 618 - 619 - /* Open a handle and 620 - * search all devices for an open handle 621 - */ 622 - priv = NULL; 623 - priv = dev_get_drvdata(salg->dev[0]); 624 - 625 - /* increase reference */ 626 - ctx->dev = get_device(salg->dev[0]); 627 - 628 - /* check if its a valid mode ... */ 629 - if (spacc_isenabled(&priv->spacc, salg->mode->aead.ciph & 0xFF, 630 - enckeylen) && 631 - spacc_isenabled(&priv->spacc, 632 - salg->mode->aead.hash & 0xFF, authkeylen)) { 633 - /* try to open spacc handle */ 634 - ctx->handle = spacc_open(&priv->spacc, 635 - salg->mode->aead.ciph & 0xFF, 636 - salg->mode->aead.hash & 0xFF, 637 - -1, 0, spacc_aead_cb, tfm); 638 - } 639 - 640 - if (ctx->handle < 0) { 641 - put_device(salg->dev[0]); 642 - pr_debug("Failed to open SPAcc context\n"); 643 - return -EIO; 644 - } 645 - 646 - /* setup XCBC key */ 647 - if (salg->mode->aead.hash == CRYPTO_MODE_MAC_XCBC) { 648 - err = spacc_compute_xcbc_key(&priv->spacc, 649 - salg->mode->aead.hash, 650 - ctx->handle, authkey, 651 - authkeylen, xcbc); 652 - if (err < 0) { 653 - dev_warn(ctx->dev, "Failed to compute XCBC key: %d\n", 654 - err); 655 - return -EIO; 656 - } 657 - authkey = xcbc; 658 - authkeylen = 48; 659 - } 660 - 661 - /* handle zero key/zero len DEC condition for SM4/AES GCM mode */ 662 - ctx->zero_key = 0; 663 - if (!key[0]) { 664 - int i, val = 0; 665 - 666 - for (i = 0; i < keylen ; i++) 667 - val += key[i]; 668 - 669 - if (val == 0) 670 - ctx->zero_key = 1; 671 - } 672 - 673 - err = spacc_write_context(&priv->spacc, ctx->handle, 674 - SPACC_CRYPTO_OPERATION, enckey, 675 - enckeylen, NULL, 0); 676 - 677 - if (err) { 678 - dev_warn(ctx->dev, 679 - "Could not write ciphering context: %d\n", err); 680 - return -EIO; 681 - } 682 - 683 - if (!singlekey) { 684 - err = spacc_write_context(&priv->spacc, ctx->handle, 685 - SPACC_HASH_OPERATION, authkey, 686 - authkeylen, NULL, 0); 687 - if (err) { 688 - dev_warn(ctx->dev, 689 - "Could not write hashing context: %d\n", err); 690 - return -EIO; 691 - } 692 - } 693 - 694 - /* set expand key */ 695 - spacc_set_key_exp(&priv->spacc, ctx->handle); 696 - ctx->ctx_valid = true; 697 - 698 - memset(xcbc, 0, sizeof(xcbc)); 699 - 700 - /* copy key to ctx for fallback */ 701 - memcpy(ctx->key, key, keylen); 702 - 703 - return 0; 704 - } 705 - 706 - static int spacc_aead_setauthsize(struct crypto_aead *tfm, 707 - unsigned int authsize) 708 - { 709 - struct spacc_crypto_ctx *ctx = crypto_aead_ctx(tfm); 710 - 711 - ctx->auth_size = authsize; 712 - 713 - /* taken from crypto/ccm.c */ 714 - switch (ctx->mode) { 715 - case CRYPTO_MODE_SM4_GCM: 716 - case CRYPTO_MODE_AES_GCM: 717 - switch (authsize) { 718 - case 4: 719 - case 8: 720 - case 12: 721 - case 13: 722 - case 14: 723 - case 15: 724 - case 16: 725 - break; 726 - default: 727 - return -EINVAL; 728 - } 729 - break; 730 - 731 - case CRYPTO_MODE_AES_CCM: 732 - case CRYPTO_MODE_SM4_CCM: 733 - switch (authsize) { 734 - case 4: 735 - case 6: 736 - case 8: 737 - case 10: 738 - case 12: 739 - case 14: 740 - case 16: 741 - break; 742 - default: 743 - return -EINVAL; 744 - } 745 - break; 746 - 747 - case CRYPTO_MODE_CHACHA20_POLY1305: 748 - switch (authsize) { 749 - case 16: 750 - break; 751 - default: 752 - return -EINVAL; 753 - } 754 - break; 755 - } 756 - 757 - return 0; 758 - } 759 - 760 - static int spacc_aead_fallback(struct aead_request *req, 761 - struct spacc_crypto_ctx *ctx, int encrypt) 762 - { 763 - int ret; 764 - struct aead_request *subreq = aead_request_ctx(req); 765 - struct crypto_aead *reqtfm = crypto_aead_reqtfm(req); 766 - struct aead_alg *alg = crypto_aead_alg(reqtfm); 767 - const char *aead_name = alg->base.cra_name; 768 - 769 - ctx->fb.aead = crypto_alloc_aead(aead_name, 0, 770 - CRYPTO_ALG_NEED_FALLBACK | 771 - CRYPTO_ALG_ASYNC); 772 - if (IS_ERR(ctx->fb.aead)) { 773 - pr_err("Spacc aead fallback tfm is NULL!\n"); 774 - return PTR_ERR(ctx->fb.aead); 775 - } 776 - 777 - subreq = aead_request_alloc(ctx->fb.aead, GFP_KERNEL); 778 - if (!subreq) 779 - return -ENOMEM; 780 - 781 - crypto_aead_setkey(ctx->fb.aead, ctx->key, ctx->keylen); 782 - crypto_aead_setauthsize(ctx->fb.aead, ctx->auth_size); 783 - 784 - aead_request_set_tfm(subreq, ctx->fb.aead); 785 - aead_request_set_callback(subreq, req->base.flags, 786 - req->base.complete, req->base.data); 787 - aead_request_set_crypt(subreq, req->src, req->dst, req->cryptlen, 788 - req->iv); 789 - aead_request_set_ad(subreq, req->assoclen); 790 - 791 - if (encrypt) 792 - ret = crypto_aead_encrypt(subreq); 793 - else 794 - ret = crypto_aead_decrypt(subreq); 795 - 796 - aead_request_free(subreq); 797 - crypto_free_aead(ctx->fb.aead); 798 - ctx->fb.aead = NULL; 799 - 800 - return ret; 801 - } 802 - 803 - static int spacc_aead_process(struct aead_request *req, u64 seq, int encrypt) 804 - { 805 - int rc; 806 - int B0len; 807 - int alen; 808 - u32 dstoff; 809 - int icvremove; 810 - int ivaadsize; 811 - int ptaadsize = 0; 812 - int iv_to_context; 813 - int spacc_proc_len; 814 - u32 spacc_icv_offset = 0; 815 - int spacc_pre_aad_size; 816 - int ccm_aad_16b_len; 817 - struct crypto_aead *reqtfm = crypto_aead_reqtfm(req); 818 - int ivsize = crypto_aead_ivsize(reqtfm); 819 - struct spacc_crypto_ctx *tctx = crypto_aead_ctx(reqtfm); 820 - struct spacc_crypto_reqctx *ctx = aead_request_ctx(req); 821 - struct spacc_priv *priv = dev_get_drvdata(tctx->dev); 822 - 823 - ctx->encrypt_op = encrypt; 824 - alen = 0; 825 - ccm_aad_16b_len = 0; 826 - 827 - if (tctx->handle < 0 || !tctx->ctx_valid || (req->cryptlen + 828 - req->assoclen) > priv->max_msg_len) 829 - return -EINVAL; 830 - 831 - /* IV is programmed to context by default */ 832 - iv_to_context = SET_IV_IN_CONTEXT; 833 - 834 - if (encrypt) { 835 - switch (tctx->mode & 0xFF) { 836 - case CRYPTO_MODE_AES_GCM: 837 - case CRYPTO_MODE_SM4_GCM: 838 - case CRYPTO_MODE_CHACHA20_POLY1305: 839 - /* For cryptlen = 0 */ 840 - if (req->cryptlen + req->assoclen == 0) 841 - return spacc_aead_fallback(req, tctx, encrypt); 842 - break; 843 - case CRYPTO_MODE_AES_CCM: 844 - case CRYPTO_MODE_SM4_CCM: 845 - 846 - if (req->cryptlen + req->assoclen == 0) 847 - return spacc_aead_fallback(req, tctx, encrypt); 848 - 849 - /* verify that msglen can in fact be represented 850 - * in L bytes 851 - */ 852 - /* 2 <= L <= 8, so 1 <= L' <= 7. */ 853 - if (req->iv[0] < 1 || req->iv[0] > 7) 854 - return -EINVAL; 855 - 856 - break; 857 - default: 858 - pr_debug("Unsupported algo"); 859 - return -EINVAL; 860 - } 861 - } else { 862 - /* Handle the decryption */ 863 - switch (tctx->mode & 0xFF) { 864 - case CRYPTO_MODE_AES_GCM: 865 - case CRYPTO_MODE_SM4_GCM: 866 - case CRYPTO_MODE_CHACHA20_POLY1305: 867 - /* For assoclen = 0 */ 868 - if (req->assoclen == 0 && 869 - (req->cryptlen - tctx->auth_size == 0)) 870 - return spacc_aead_fallback(req, tctx, encrypt); 871 - break; 872 - case CRYPTO_MODE_AES_CCM: 873 - case CRYPTO_MODE_SM4_CCM: 874 - 875 - if (req->assoclen == 0 && 876 - (req->cryptlen - tctx->auth_size == 0)) 877 - return spacc_aead_fallback(req, tctx, encrypt); 878 - /* 2 <= L <= 8, so 1 <= L' <= 7. */ 879 - if (req->iv[0] < 1 || req->iv[0] > 7) 880 - return -EINVAL; 881 - break; 882 - default: 883 - pr_debug("Unsupported algo"); 884 - return -EINVAL; 885 - } 886 - } 887 - 888 - icvremove = (encrypt) ? 0 : tctx->auth_size; 889 - 890 - rc = spacc_aead_init_dma(tctx->dev, req, seq, (encrypt) ? 891 - tctx->auth_size : 0, encrypt, &alen); 892 - if (rc < 0) 893 - return -EINVAL; 894 - 895 - if (req->assoclen) 896 - ccm_aad_16b_len = ccm_16byte_aligned_len(req->assoclen + alen); 897 - 898 - /* Note: This won't work if IV_IMPORT has been disabled */ 899 - ctx->cb.new_handle = spacc_clone_handle(&priv->spacc, tctx->handle, 900 - &ctx->cb); 901 - if (ctx->cb.new_handle < 0) { 902 - spacc_aead_cleanup_dma(tctx->dev, req); 903 - return -EINVAL; 904 - } 905 - 906 - ctx->cb.tctx = tctx; 907 - ctx->cb.ctx = ctx; 908 - ctx->cb.req = req; 909 - ctx->cb.spacc = &priv->spacc; 910 - 911 - /* Write IV to the spacc-context 912 - * IV can be written to context or as part of the input src buffer 913 - * IV in case of CCM is going in the input src buff. 914 - * IV for GCM is written to the context. 915 - */ 916 - if (tctx->mode == CRYPTO_MODE_AES_GCM_RFC4106 || 917 - tctx->mode == CRYPTO_MODE_AES_GCM || 918 - tctx->mode == CRYPTO_MODE_SM4_GCM_RFC8998 || 919 - tctx->mode == CRYPTO_MODE_CHACHA20_POLY1305 || 920 - tctx->mode == CRYPTO_MODE_NULL) { 921 - iv_to_context = SET_IV_IN_CONTEXT; 922 - rc = spacc_write_context(&priv->spacc, ctx->cb.new_handle, 923 - SPACC_CRYPTO_OPERATION, NULL, 0, 924 - req->iv, ivsize); 925 - 926 - if (rc < 0) { 927 - spacc_aead_cleanup_dma(tctx->dev, req); 928 - spacc_close(&priv->spacc, ctx->cb.new_handle); 929 - return -EINVAL; 930 - } 931 - } 932 - 933 - /* CCM and GCM don't include the IV in the AAD */ 934 - if (tctx->mode == CRYPTO_MODE_AES_GCM_RFC4106 || 935 - tctx->mode == CRYPTO_MODE_AES_CCM_RFC4309 || 936 - tctx->mode == CRYPTO_MODE_AES_GCM || 937 - tctx->mode == CRYPTO_MODE_AES_CCM || 938 - tctx->mode == CRYPTO_MODE_SM4_CCM || 939 - tctx->mode == CRYPTO_MODE_SM4_GCM_RFC8998 || 940 - tctx->mode == CRYPTO_MODE_CHACHA20_POLY1305 || 941 - tctx->mode == CRYPTO_MODE_NULL) { 942 - ivaadsize = 0; 943 - } else { 944 - ivaadsize = ivsize; 945 - } 946 - 947 - /* CCM requires an extra block of AAD */ 948 - if (tctx->mode == CRYPTO_MODE_AES_CCM_RFC4309 || 949 - tctx->mode == CRYPTO_MODE_AES_CCM || 950 - tctx->mode == CRYPTO_MODE_SM4_CCM) 951 - B0len = SPACC_B0_SIZE; 952 - else 953 - B0len = 0; 954 - 955 - /* GMAC mode uses AAD for the entire message. 956 - * So does NULL cipher 957 - */ 958 - if (tctx->mode == CRYPTO_MODE_AES_GCM_RFC4543 || 959 - tctx->mode == CRYPTO_MODE_NULL) { 960 - if (req->cryptlen >= icvremove) 961 - ptaadsize = req->cryptlen - icvremove; 962 - } 963 - 964 - /* Calculate and set the below, important parameters 965 - * spacc icv offset - spacc_icv_offset 966 - * destination offset - dstoff 967 - * IV to context - This is set for CCM, not set for GCM 968 - */ 969 - if (req->dst == req->src) { 970 - dstoff = ((uint32_t)(SPACC_MAX_IV_SIZE + B0len + 971 - req->assoclen + ivaadsize)); 972 - 973 - /* CCM case */ 974 - if (tctx->mode == CRYPTO_MODE_AES_CCM_RFC4309 || 975 - tctx->mode == CRYPTO_MODE_AES_CCM || 976 - tctx->mode == CRYPTO_MODE_SM4_CCM) { 977 - iv_to_context = SET_IV_IN_SRCBUF; 978 - dstoff = ((uint32_t)(SPACC_MAX_IV_SIZE + B0len + 979 - ccm_aad_16b_len + ivaadsize)); 980 - } 981 - 982 - } else { 983 - dstoff = ((uint32_t)(req->assoclen + ivaadsize)); 984 - 985 - /* CCM case */ 986 - if (tctx->mode == CRYPTO_MODE_AES_CCM_RFC4309 || 987 - tctx->mode == CRYPTO_MODE_AES_CCM || 988 - tctx->mode == CRYPTO_MODE_SM4_CCM) { 989 - iv_to_context = SET_IV_IN_SRCBUF; 990 - dstoff = ((uint32_t)(req->assoclen + ivaadsize)); 991 - 992 - } 993 - } 994 - 995 - /* Calculate and set the below, important parameters 996 - * spacc proc_len - spacc_proc_len 997 - * pre-AAD size - spacc_pre_aad_size 998 - */ 999 - if (tctx->mode == CRYPTO_MODE_AES_CCM || 1000 - tctx->mode == CRYPTO_MODE_SM4_CCM || 1001 - tctx->mode == CRYPTO_MODE_AES_CCM_RFC4309 || 1002 - tctx->mode == CRYPTO_MODE_SM4_CCM_RFC8998) { 1003 - spacc_proc_len = B0len + ccm_aad_16b_len 1004 - + req->cryptlen + ivaadsize 1005 - - icvremove; 1006 - spacc_pre_aad_size = B0len + ccm_aad_16b_len 1007 - + ivaadsize + ptaadsize; 1008 - 1009 - } else { 1010 - spacc_proc_len = B0len + req->assoclen 1011 - + req->cryptlen - icvremove 1012 - + ivaadsize; 1013 - spacc_pre_aad_size = B0len + req->assoclen 1014 - + ivaadsize + ptaadsize; 1015 - } 1016 - 1017 - rc = spacc_set_operation(&priv->spacc, 1018 - ctx->cb.new_handle, 1019 - encrypt ? OP_ENCRYPT : OP_DECRYPT, 1020 - ICV_ENCRYPT_HASH, IP_ICV_APPEND, 1021 - spacc_icv_offset, 1022 - tctx->auth_size, 0); 1023 - 1024 - rc = spacc_packet_enqueue_ddt(&priv->spacc, ctx->cb.new_handle, 1025 - &ctx->src, 1026 - (req->dst == req->src) ? &ctx->src : 1027 - &ctx->dst, spacc_proc_len, 1028 - (dstoff << SPACC_OFFSET_DST_O) | 1029 - SPACC_MAX_IV_SIZE, 1030 - spacc_pre_aad_size, 1031 - 0, iv_to_context, 0); 1032 - 1033 - if (rc < 0) { 1034 - spacc_aead_cleanup_dma(tctx->dev, req); 1035 - spacc_close(&priv->spacc, ctx->cb.new_handle); 1036 - 1037 - if (rc != -EBUSY) { 1038 - dev_err(tctx->dev, " failed to enqueue job, ERR: %d\n", 1039 - rc); 1040 - } 1041 - 1042 - if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) 1043 - return -EBUSY; 1044 - 1045 - return -EINVAL; 1046 - } 1047 - 1048 - /* At this point the job is in flight to the engine ... remove first use 1049 - * so subsequent calls don't expand the key again... ideally we would 1050 - * pump a dummy job through the engine to pre-expand the key so that by 1051 - * the time setkey was done we wouldn't have to do this 1052 - */ 1053 - priv->spacc.job[tctx->handle].first_use = 0; 1054 - priv->spacc.job[tctx->handle].ctrl &= ~(1UL 1055 - << priv->spacc.config.ctrl_map[SPACC_CTRL_KEY_EXP]); 1056 - 1057 - return -EINPROGRESS; 1058 - } 1059 - 1060 - static int spacc_aead_encrypt(struct aead_request *req) 1061 - { 1062 - return spacc_aead_process(req, 0ULL, 1); 1063 - } 1064 - 1065 - static int spacc_aead_decrypt(struct aead_request *req) 1066 - { 1067 - return spacc_aead_process(req, 0ULL, 0); 1068 - } 1069 - 1070 - static int spacc_aead_init(struct crypto_aead *tfm) 1071 - { 1072 - struct spacc_crypto_ctx *ctx = crypto_aead_ctx(tfm); 1073 - const struct spacc_alg *salg = spacc_tfm_aead(&tfm->base); 1074 - 1075 - crypto_aead_set_reqsize(tfm, sizeof(struct spacc_crypto_reqctx)); 1076 - 1077 - ctx->zero_key = 0; 1078 - ctx->fb.aead = NULL; 1079 - ctx->handle = -1; 1080 - ctx->mode = salg->mode->aead.ciph; 1081 - ctx->dev = get_device(salg->dev[0]); 1082 - 1083 - return 0; 1084 - } 1085 - 1086 - static void spacc_aead_exit(struct crypto_aead *tfm) 1087 - { 1088 - struct spacc_crypto_ctx *ctx = crypto_aead_ctx(tfm); 1089 - struct spacc_priv *priv = dev_get_drvdata(ctx->dev); 1090 - 1091 - ctx->fb.aead = NULL; 1092 - /* close spacc handle */ 1093 - if (ctx->handle >= 0) { 1094 - spacc_close(&priv->spacc, ctx->handle); 1095 - ctx->handle = -1; 1096 - } 1097 - 1098 - put_device(ctx->dev); 1099 - } 1100 - 1101 - static struct aead_alg spacc_aead_algs = { 1102 - .setkey = spacc_aead_setkey, 1103 - .setauthsize = spacc_aead_setauthsize, 1104 - .encrypt = spacc_aead_encrypt, 1105 - .decrypt = spacc_aead_decrypt, 1106 - .init = spacc_aead_init, 1107 - .exit = spacc_aead_exit, 1108 - 1109 - .base.cra_priority = 300, 1110 - .base.cra_module = THIS_MODULE, 1111 - .base.cra_ctxsize = sizeof(struct spacc_crypto_ctx), 1112 - .base.cra_flags = CRYPTO_ALG_TYPE_AEAD 1113 - | CRYPTO_ALG_ASYNC 1114 - | CRYPTO_ALG_NEED_FALLBACK 1115 - | CRYPTO_ALG_KERN_DRIVER_ONLY 1116 - | CRYPTO_ALG_OPTIONAL_KEY 1117 - }; 1118 - 1119 - static int spacc_register_aead(unsigned int aead_mode, 1120 - struct platform_device *spacc_pdev) 1121 - { 1122 - int rc; 1123 - struct spacc_alg *salg; 1124 - 1125 - salg = kmalloc(sizeof(*salg), GFP_KERNEL); 1126 - if (!salg) 1127 - return -ENOMEM; 1128 - 1129 - salg->mode = &possible_aeads[aead_mode]; 1130 - salg->dev[0] = &spacc_pdev->dev; 1131 - salg->dev[1] = NULL; 1132 - salg->calg = &salg->alg.aead.base; 1133 - salg->alg.aead = spacc_aead_algs; 1134 - 1135 - spacc_init_aead_alg(salg->calg, salg->mode); 1136 - 1137 - salg->alg.aead.ivsize = salg->mode->ivlen; 1138 - salg->alg.aead.maxauthsize = salg->mode->hashlen; 1139 - salg->alg.aead.base.cra_blocksize = salg->mode->blocklen; 1140 - 1141 - salg->keylen_mask = possible_aeads[aead_mode].keylen_mask; 1142 - 1143 - if (salg->mode->aead.ciph & SPACC_MANGLE_IV_FLAG) { 1144 - switch (salg->mode->aead.ciph & 0x7F00) { 1145 - case SPACC_MANGLE_IV_RFC3686: /*CTR*/ 1146 - case SPACC_MANGLE_IV_RFC4106: /*GCM*/ 1147 - case SPACC_MANGLE_IV_RFC4543: /*GMAC*/ 1148 - case SPACC_MANGLE_IV_RFC4309: /*CCM*/ 1149 - case SPACC_MANGLE_IV_RFC8998: /*GCM/CCM*/ 1150 - salg->alg.aead.ivsize = 12; 1151 - break; 1152 - } 1153 - } 1154 - 1155 - rc = crypto_register_aead(&salg->alg.aead); 1156 - if (rc < 0) { 1157 - kfree(salg); 1158 - return rc; 1159 - } 1160 - 1161 - dev_dbg(salg->dev[0], "Registered %s\n", salg->mode->name); 1162 - 1163 - mutex_lock(&spacc_aead_alg_mutex); 1164 - list_add(&salg->list, &spacc_aead_alg_list); 1165 - mutex_unlock(&spacc_aead_alg_mutex); 1166 - 1167 - return 0; 1168 - } 1169 - 1170 - int probe_aeads(struct platform_device *spacc_pdev) 1171 - { 1172 - int err; 1173 - unsigned int x, y; 1174 - struct spacc_priv *priv = NULL; 1175 - 1176 - size_t alloc_size = max_t(unsigned long, 1177 - roundup_pow_of_two(sizeof(struct spacc_iv_buf)), 1178 - dma_get_cache_alignment()); 1179 - 1180 - spacc_iv_pool = kmem_cache_create("spacc-aead-iv", alloc_size, 1181 - alloc_size, 0, NULL); 1182 - 1183 - if (!spacc_iv_pool) 1184 - return -ENOMEM; 1185 - 1186 - for (x = 0; x < ARRAY_SIZE(possible_aeads); x++) { 1187 - possible_aeads[x].keylen_mask = 0; 1188 - possible_aeads[x].valid = 0; 1189 - } 1190 - 1191 - /* compute cipher key masks (over all devices) */ 1192 - priv = dev_get_drvdata(&spacc_pdev->dev); 1193 - 1194 - for (x = 0; x < ARRAY_SIZE(possible_aeads); x++) { 1195 - for (y = 0; y < ARRAY_SIZE(possible_aeads[x].keylen); y++) { 1196 - if (spacc_isenabled(&priv->spacc, 1197 - possible_aeads[x].aead.ciph & 0xFF, 1198 - possible_aeads[x].keylen[y])) 1199 - possible_aeads[x].keylen_mask |= 1u << y; 1200 - } 1201 - } 1202 - 1203 - /* scan for combined modes */ 1204 - priv = dev_get_drvdata(&spacc_pdev->dev); 1205 - 1206 - for (x = 0; x < ARRAY_SIZE(possible_aeads); x++) { 1207 - if (!possible_aeads[x].valid && possible_aeads[x].keylen_mask) { 1208 - if (spacc_isenabled(&priv->spacc, 1209 - possible_aeads[x].aead.hash & 0xFF, 1210 - possible_aeads[x].hashlen)) { 1211 - 1212 - possible_aeads[x].valid = 1; 1213 - err = spacc_register_aead(x, spacc_pdev); 1214 - if (err < 0) 1215 - goto error; 1216 - } 1217 - } 1218 - } 1219 - 1220 - return 0; 1221 - 1222 - error: 1223 - return err; 1224 - } 1225 - 1226 - int spacc_unregister_aead_algs(void) 1227 - { 1228 - struct spacc_alg *salg, *tmp; 1229 - 1230 - mutex_lock(&spacc_aead_alg_mutex); 1231 - 1232 - list_for_each_entry_safe(salg, tmp, &spacc_aead_alg_list, list) { 1233 - crypto_unregister_alg(salg->calg); 1234 - list_del(&salg->list); 1235 - kfree(salg); 1236 - } 1237 - 1238 - mutex_unlock(&spacc_aead_alg_mutex); 1239 - 1240 - kmem_cache_destroy(spacc_iv_pool); 1241 - 1242 - return 0; 1243 - }
-914
drivers/crypto/dwc-spacc/spacc_ahash.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - 3 - #include <linux/dmapool.h> 4 - #include <crypto/sm3.h> 5 - #include <crypto/sha1.h> 6 - #include <crypto/sm4.h> 7 - #include <crypto/sha2.h> 8 - #include <crypto/sha3.h> 9 - #include <crypto/md5.h> 10 - #include <crypto/aes.h> 11 - #include <linux/dma-mapping.h> 12 - #include <linux/platform_device.h> 13 - #include <crypto/internal/hash.h> 14 - 15 - #include "spacc_device.h" 16 - #include "spacc_core.h" 17 - 18 - #define PPP_BUF_SIZE 128 19 - 20 - struct sdesc { 21 - struct shash_desc shash; 22 - char ctx[]; 23 - }; 24 - 25 - static struct dma_pool *spacc_hash_pool; 26 - static LIST_HEAD(spacc_hash_alg_list); 27 - static LIST_HEAD(head_sglbuf); 28 - static DEFINE_MUTEX(spacc_hash_alg_mutex); 29 - 30 - static struct mode_tab possible_hashes[] = { 31 - { .keylen[0] = 16, MODE_TAB_HASH("cmac(aes)", MAC_CMAC, 16, 16), 32 - .sw_fb = true }, 33 - { .keylen[0] = 48 | MODE_TAB_HASH_XCBC, MODE_TAB_HASH("xcbc(aes)", 34 - MAC_XCBC, 16, 16), .sw_fb = true }, 35 - 36 - { MODE_TAB_HASH("cmac(sm4)", MAC_SM4_CMAC, 16, 16), .sw_fb = true }, 37 - { .keylen[0] = 32 | MODE_TAB_HASH_XCBC, MODE_TAB_HASH("xcbc(sm4)", 38 - MAC_SM4_XCBC, 16, 16), .sw_fb = true }, 39 - 40 - { MODE_TAB_HASH("hmac(md5)", HMAC_MD5, MD5_DIGEST_SIZE, 41 - MD5_HMAC_BLOCK_SIZE), .sw_fb = true }, 42 - { MODE_TAB_HASH("md5", HASH_MD5, MD5_DIGEST_SIZE, 43 - MD5_HMAC_BLOCK_SIZE), .sw_fb = true }, 44 - 45 - { MODE_TAB_HASH("hmac(sha1)", HMAC_SHA1, SHA1_DIGEST_SIZE, 46 - SHA1_BLOCK_SIZE), .sw_fb = true }, 47 - { MODE_TAB_HASH("sha1", HASH_SHA1, SHA1_DIGEST_SIZE, 48 - SHA1_BLOCK_SIZE), .sw_fb = true }, 49 - 50 - { MODE_TAB_HASH("sha224", HASH_SHA224, SHA224_DIGEST_SIZE, 51 - SHA224_BLOCK_SIZE), .sw_fb = true }, 52 - { MODE_TAB_HASH("sha256", HASH_SHA256, SHA256_DIGEST_SIZE, 53 - SHA256_BLOCK_SIZE), .sw_fb = true }, 54 - { MODE_TAB_HASH("sha384", HASH_SHA384, SHA384_DIGEST_SIZE, 55 - SHA384_BLOCK_SIZE), .sw_fb = true }, 56 - { MODE_TAB_HASH("sha512", HASH_SHA512, SHA512_DIGEST_SIZE, 57 - SHA512_BLOCK_SIZE), .sw_fb = true }, 58 - 59 - { MODE_TAB_HASH("hmac(sha512)", HMAC_SHA512, SHA512_DIGEST_SIZE, 60 - SHA512_BLOCK_SIZE), .sw_fb = true }, 61 - { MODE_TAB_HASH("hmac(sha224)", HMAC_SHA224, SHA224_DIGEST_SIZE, 62 - SHA224_BLOCK_SIZE), .sw_fb = true }, 63 - { MODE_TAB_HASH("hmac(sha256)", HMAC_SHA256, SHA256_DIGEST_SIZE, 64 - SHA256_BLOCK_SIZE), .sw_fb = true }, 65 - { MODE_TAB_HASH("hmac(sha384)", HMAC_SHA384, SHA384_DIGEST_SIZE, 66 - SHA384_BLOCK_SIZE), .sw_fb = true }, 67 - 68 - { MODE_TAB_HASH("sha3-224", HASH_SHA3_224, SHA3_224_DIGEST_SIZE, 69 - SHA3_224_BLOCK_SIZE), .sw_fb = true }, 70 - { MODE_TAB_HASH("sha3-256", HASH_SHA3_256, SHA3_256_DIGEST_SIZE, 71 - SHA3_256_BLOCK_SIZE), .sw_fb = true }, 72 - { MODE_TAB_HASH("sha3-384", HASH_SHA3_384, SHA3_384_DIGEST_SIZE, 73 - SHA3_384_BLOCK_SIZE), .sw_fb = true }, 74 - { MODE_TAB_HASH("sha3-512", HASH_SHA3_512, SHA3_512_DIGEST_SIZE, 75 - SHA3_512_BLOCK_SIZE), .sw_fb = true }, 76 - 77 - { MODE_TAB_HASH("hmac(sm3)", HMAC_SM3, SM3_DIGEST_SIZE, 78 - SM3_BLOCK_SIZE), .sw_fb = true }, 79 - { MODE_TAB_HASH("sm3", HASH_SM3, SM3_DIGEST_SIZE, 80 - SM3_BLOCK_SIZE), .sw_fb = true }, 81 - { MODE_TAB_HASH("michael_mic", MAC_MICHAEL, 8, 8), .sw_fb = true }, 82 - }; 83 - 84 - static void spacc_hash_cleanup_dma_dst(struct spacc_crypto_ctx *tctx, 85 - struct ahash_request *req) 86 - { 87 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 88 - 89 - pdu_ddt_free(&ctx->dst); 90 - } 91 - 92 - static void spacc_hash_cleanup_dma_src(struct spacc_crypto_ctx *tctx, 93 - struct ahash_request *req) 94 - { 95 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 96 - 97 - if (tctx->tmp_sgl && tctx->tmp_sgl[0].length != 0) { 98 - dma_unmap_sg(tctx->dev, tctx->tmp_sgl, ctx->src_nents, 99 - DMA_TO_DEVICE); 100 - kfree(tctx->tmp_sgl_buff); 101 - tctx->tmp_sgl_buff = NULL; 102 - tctx->tmp_sgl[0].length = 0; 103 - } else { 104 - dma_unmap_sg(tctx->dev, req->src, ctx->src_nents, 105 - DMA_TO_DEVICE); 106 - } 107 - 108 - pdu_ddt_free(&ctx->src); 109 - } 110 - 111 - static void spacc_hash_cleanup_dma(struct device *dev, 112 - struct ahash_request *req) 113 - { 114 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 115 - 116 - dma_unmap_sg(dev, req->src, ctx->src_nents, DMA_TO_DEVICE); 117 - pdu_ddt_free(&ctx->src); 118 - 119 - dma_pool_free(spacc_hash_pool, ctx->digest_buf, ctx->digest_dma); 120 - pdu_ddt_free(&ctx->dst); 121 - } 122 - 123 - static void spacc_init_calg(struct crypto_alg *calg, 124 - const struct mode_tab *mode) 125 - { 126 - 127 - strscpy(calg->cra_name, mode->name); 128 - calg->cra_name[sizeof(mode->name) - 1] = '\0'; 129 - 130 - strscpy(calg->cra_driver_name, "spacc-"); 131 - strcat(calg->cra_driver_name, mode->name); 132 - calg->cra_driver_name[sizeof(calg->cra_driver_name) - 1] = '\0'; 133 - 134 - calg->cra_blocksize = mode->blocklen; 135 - } 136 - 137 - static int spacc_ctx_clone_handle(struct ahash_request *req) 138 - { 139 - struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 140 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(tfm); 141 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 142 - struct spacc_priv *priv = dev_get_drvdata(tctx->dev); 143 - 144 - if (tctx->handle < 0) 145 - return -ENXIO; 146 - 147 - ctx->acb.new_handle = spacc_clone_handle(&priv->spacc, tctx->handle, 148 - &ctx->acb); 149 - 150 - if (ctx->acb.new_handle < 0) { 151 - spacc_hash_cleanup_dma(tctx->dev, req); 152 - return -ENOMEM; 153 - } 154 - 155 - ctx->acb.tctx = tctx; 156 - ctx->acb.ctx = ctx; 157 - ctx->acb.req = req; 158 - ctx->acb.spacc = &priv->spacc; 159 - 160 - return 0; 161 - } 162 - 163 - static int spacc_hash_init_dma(struct device *dev, struct ahash_request *req, 164 - int final) 165 - { 166 - int rc = -1; 167 - struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 168 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(tfm); 169 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 170 - 171 - gfp_t mflags = GFP_ATOMIC; 172 - 173 - if (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) 174 - mflags = GFP_KERNEL; 175 - 176 - ctx->digest_buf = dma_pool_alloc(spacc_hash_pool, mflags, 177 - &ctx->digest_dma); 178 - 179 - if (!ctx->digest_buf) 180 - return -ENOMEM; 181 - 182 - rc = pdu_ddt_init(&ctx->dst, 1 | 0x80000000); 183 - if (rc < 0) { 184 - pr_err("ERR: PDU DDT init error\n"); 185 - rc = -EIO; 186 - goto err_free_digest; 187 - } 188 - 189 - pdu_ddt_add(&ctx->dst, ctx->digest_dma, SPACC_MAX_DIGEST_SIZE); 190 - 191 - if (ctx->total_nents > 0 && ctx->single_shot) { 192 - /* single shot */ 193 - spacc_ctx_clone_handle(req); 194 - 195 - if (req->nbytes) { 196 - rc = spacc_sg_to_ddt(dev, req->src, req->nbytes, 197 - &ctx->src, DMA_TO_DEVICE); 198 - } else { 199 - memset(tctx->tmp_buffer, '\0', PPP_BUF_SIZE); 200 - sg_set_buf(&(tctx->tmp_sgl[0]), tctx->tmp_buffer, 201 - PPP_BUF_SIZE); 202 - rc = spacc_sg_to_ddt(dev, &(tctx->tmp_sgl[0]), 203 - tctx->tmp_sgl[0].length, 204 - &ctx->src, DMA_TO_DEVICE); 205 - 206 - } 207 - } else if (ctx->total_nents == 0 && req->nbytes == 0) { 208 - spacc_ctx_clone_handle(req); 209 - 210 - /* zero length case */ 211 - memset(tctx->tmp_buffer, '\0', PPP_BUF_SIZE); 212 - sg_set_buf(&(tctx->tmp_sgl[0]), tctx->tmp_buffer, PPP_BUF_SIZE); 213 - rc = spacc_sg_to_ddt(dev, &(tctx->tmp_sgl[0]), 214 - tctx->tmp_sgl[0].length, 215 - &ctx->src, DMA_TO_DEVICE); 216 - 217 - } 218 - 219 - if (rc < 0) 220 - goto err_free_dst; 221 - 222 - ctx->src_nents = rc; 223 - 224 - return rc; 225 - 226 - err_free_dst: 227 - pdu_ddt_free(&ctx->dst); 228 - err_free_digest: 229 - dma_pool_free(spacc_hash_pool, ctx->digest_buf, ctx->digest_dma); 230 - 231 - return rc; 232 - } 233 - 234 - static void spacc_free_mems(struct spacc_crypto_reqctx *ctx, 235 - struct spacc_crypto_ctx *tctx, 236 - struct ahash_request *req) 237 - { 238 - spacc_hash_cleanup_dma_dst(tctx, req); 239 - spacc_hash_cleanup_dma_src(tctx, req); 240 - 241 - if (ctx->single_shot) { 242 - kfree(tctx->tmp_sgl); 243 - tctx->tmp_sgl = NULL; 244 - 245 - ctx->single_shot = 0; 246 - if (ctx->total_nents) 247 - ctx->total_nents = 0; 248 - } 249 - } 250 - 251 - static void spacc_digest_cb(void *spacc, void *tfm) 252 - { 253 - struct ahash_cb_data *cb = tfm; 254 - int err = -1; 255 - int dig_sz; 256 - 257 - dig_sz = crypto_ahash_digestsize(crypto_ahash_reqtfm(cb->req)); 258 - 259 - if (cb->ctx->single_shot) 260 - memcpy(cb->req->result, cb->ctx->digest_buf, dig_sz); 261 - else 262 - memcpy(cb->tctx->digest_ctx_buf, cb->ctx->digest_buf, dig_sz); 263 - 264 - err = cb->spacc->job[cb->new_handle].job_err; 265 - 266 - dma_pool_free(spacc_hash_pool, cb->ctx->digest_buf, 267 - cb->ctx->digest_dma); 268 - spacc_free_mems(cb->ctx, cb->tctx, cb->req); 269 - spacc_close(cb->spacc, cb->new_handle); 270 - 271 - if (cb->req->base.complete) 272 - ahash_request_complete(cb->req, err); 273 - } 274 - 275 - static int do_shash(unsigned char *name, unsigned char *result, 276 - const u8 *data1, unsigned int data1_len, 277 - const u8 *data2, unsigned int data2_len, 278 - const u8 *key, unsigned int key_len) 279 - { 280 - int rc; 281 - unsigned int size; 282 - struct crypto_shash *hash; 283 - struct sdesc *sdesc; 284 - 285 - hash = crypto_alloc_shash(name, 0, 0); 286 - if (IS_ERR(hash)) { 287 - rc = PTR_ERR(hash); 288 - pr_err("ERR: Crypto %s allocation error %d\n", name, rc); 289 - return rc; 290 - } 291 - 292 - size = sizeof(struct shash_desc) + crypto_shash_descsize(hash); 293 - sdesc = kmalloc(size, GFP_KERNEL); 294 - if (!sdesc) { 295 - rc = -ENOMEM; 296 - goto do_shash_err; 297 - } 298 - sdesc->shash.tfm = hash; 299 - 300 - if (key_len > 0) { 301 - rc = crypto_shash_setkey(hash, key, key_len); 302 - if (rc) { 303 - pr_err("ERR: Could not setkey %s shash\n", name); 304 - goto do_shash_err; 305 - } 306 - } 307 - 308 - rc = crypto_shash_init(&sdesc->shash); 309 - if (rc) { 310 - pr_err("ERR: Could not init %s shash\n", name); 311 - goto do_shash_err; 312 - } 313 - 314 - rc = crypto_shash_update(&sdesc->shash, data1, data1_len); 315 - if (rc) { 316 - pr_err("ERR: Could not update1\n"); 317 - goto do_shash_err; 318 - } 319 - 320 - if (data2 && data2_len) { 321 - rc = crypto_shash_update(&sdesc->shash, data2, data2_len); 322 - if (rc) { 323 - pr_err("ERR: Could not update2\n"); 324 - goto do_shash_err; 325 - } 326 - } 327 - 328 - rc = crypto_shash_final(&sdesc->shash, result); 329 - if (rc) 330 - pr_err("ERR: Could not generate %s hash\n", name); 331 - 332 - do_shash_err: 333 - crypto_free_shash(hash); 334 - kfree(sdesc); 335 - 336 - return rc; 337 - } 338 - 339 - static int spacc_hash_setkey(struct crypto_ahash *tfm, const u8 *key, 340 - unsigned int keylen) 341 - { 342 - int rc; 343 - const struct spacc_alg *salg = spacc_tfm_ahash(&tfm->base); 344 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(tfm); 345 - struct spacc_priv *priv = dev_get_drvdata(tctx->dev); 346 - unsigned int digest_size, block_size; 347 - char hash_alg[CRYPTO_MAX_ALG_NAME]; 348 - 349 - block_size = crypto_tfm_alg_blocksize(&tfm->base); 350 - digest_size = crypto_ahash_digestsize(tfm); 351 - 352 - /* 353 - * We will not use the hardware in case of HMACs 354 - * This was meant for hashes but it works for cmac/xcbc since we 355 - * only intend to support 128-bit keys... 356 - */ 357 - if (keylen > block_size && salg->mode->id != CRYPTO_MODE_MAC_CMAC) { 358 - pr_debug("Exceeds keylen: %u\n", keylen); 359 - pr_debug("Req. keylen hashing %s\n", 360 - salg->calg->cra_name); 361 - 362 - memset(hash_alg, 0x00, CRYPTO_MAX_ALG_NAME); 363 - switch (salg->mode->id) { 364 - case CRYPTO_MODE_HMAC_SHA224: 365 - rc = do_shash("sha224", tctx->ipad, key, keylen, 366 - NULL, 0, NULL, 0); 367 - break; 368 - 369 - case CRYPTO_MODE_HMAC_SHA256: 370 - rc = do_shash("sha256", tctx->ipad, key, keylen, 371 - NULL, 0, NULL, 0); 372 - break; 373 - 374 - case CRYPTO_MODE_HMAC_SHA384: 375 - rc = do_shash("sha384", tctx->ipad, key, keylen, 376 - NULL, 0, NULL, 0); 377 - break; 378 - 379 - case CRYPTO_MODE_HMAC_SHA512: 380 - rc = do_shash("sha512", tctx->ipad, key, keylen, 381 - NULL, 0, NULL, 0); 382 - break; 383 - 384 - case CRYPTO_MODE_HMAC_MD5: 385 - rc = do_shash("md5", tctx->ipad, key, keylen, 386 - NULL, 0, NULL, 0); 387 - break; 388 - 389 - case CRYPTO_MODE_HMAC_SHA1: 390 - rc = do_shash("sha1", tctx->ipad, key, keylen, 391 - NULL, 0, NULL, 0); 392 - break; 393 - 394 - default: 395 - return -EINVAL; 396 - } 397 - 398 - if (rc < 0) { 399 - pr_err("ERR: %d computing shash for %s\n", 400 - rc, hash_alg); 401 - return -EIO; 402 - } 403 - 404 - keylen = digest_size; 405 - pr_debug("updated keylen: %u\n", keylen); 406 - 407 - tctx->ctx_valid = false; 408 - 409 - if (salg->mode->sw_fb) { 410 - rc = crypto_ahash_setkey(tctx->fb.hash, 411 - tctx->ipad, keylen); 412 - if (rc < 0) 413 - return rc; 414 - } 415 - } else { 416 - memcpy(tctx->ipad, key, keylen); 417 - tctx->ctx_valid = false; 418 - 419 - if (salg->mode->sw_fb) { 420 - rc = crypto_ahash_setkey(tctx->fb.hash, key, keylen); 421 - if (rc < 0) 422 - return rc; 423 - } 424 - } 425 - 426 - /* close handle since key size may have changed */ 427 - if (tctx->handle >= 0) { 428 - spacc_close(&priv->spacc, tctx->handle); 429 - put_device(tctx->dev); 430 - tctx->handle = -1; 431 - tctx->dev = NULL; 432 - } 433 - 434 - priv = NULL; 435 - priv = dev_get_drvdata(salg->dev[0]); 436 - tctx->dev = get_device(salg->dev[0]); 437 - if (spacc_isenabled(&priv->spacc, salg->mode->id, keylen)) { 438 - tctx->handle = spacc_open(&priv->spacc, 439 - CRYPTO_MODE_NULL, 440 - salg->mode->id, -1, 441 - 0, spacc_digest_cb, tfm); 442 - 443 - } else 444 - pr_debug(" Keylen: %d not enabled for algo: %d", 445 - keylen, salg->mode->id); 446 - 447 - if (tctx->handle < 0) { 448 - pr_err("ERR: Failed to open SPAcc context\n"); 449 - put_device(salg->dev[0]); 450 - return -EIO; 451 - } 452 - 453 - rc = spacc_set_operation(&priv->spacc, tctx->handle, OP_ENCRYPT, 454 - ICV_HASH, IP_ICV_OFFSET, 0, 0, 0); 455 - if (rc < 0) { 456 - spacc_close(&priv->spacc, tctx->handle); 457 - tctx->handle = -1; 458 - put_device(tctx->dev); 459 - return -EIO; 460 - } 461 - 462 - if (salg->mode->id == CRYPTO_MODE_MAC_XCBC || 463 - salg->mode->id == CRYPTO_MODE_MAC_SM4_XCBC) { 464 - rc = spacc_compute_xcbc_key(&priv->spacc, salg->mode->id, 465 - tctx->handle, tctx->ipad, 466 - keylen, tctx->ipad); 467 - if (rc < 0) { 468 - dev_warn(tctx->dev, 469 - "Failed to compute XCBC key: %d\n", rc); 470 - return -EIO; 471 - } 472 - rc = spacc_write_context(&priv->spacc, tctx->handle, 473 - SPACC_HASH_OPERATION, tctx->ipad, 474 - 32 + keylen, NULL, 0); 475 - } else { 476 - rc = spacc_write_context(&priv->spacc, tctx->handle, 477 - SPACC_HASH_OPERATION, tctx->ipad, 478 - keylen, NULL, 0); 479 - } 480 - 481 - memset(tctx->ipad, 0, sizeof(tctx->ipad)); 482 - if (rc < 0) { 483 - pr_err("ERR: Failed to write SPAcc context\n"); 484 - /* Non-fatal; we continue with the software fallback. */ 485 - return 0; 486 - } 487 - 488 - tctx->ctx_valid = true; 489 - 490 - return 0; 491 - } 492 - 493 - static int spacc_set_statesize(struct spacc_alg *salg) 494 - { 495 - unsigned int statesize = 0; 496 - 497 - switch (salg->mode->id) { 498 - case CRYPTO_MODE_HMAC_SHA1: 499 - case CRYPTO_MODE_HASH_SHA1: 500 - statesize = sizeof(struct sha1_state); 501 - break; 502 - case CRYPTO_MODE_MAC_CMAC: 503 - case CRYPTO_MODE_MAC_XCBC: 504 - statesize = sizeof(struct crypto_aes_ctx); 505 - break; 506 - case CRYPTO_MODE_MAC_SM4_CMAC: 507 - case CRYPTO_MODE_MAC_SM4_XCBC: 508 - statesize = sizeof(struct sm4_ctx); 509 - break; 510 - case CRYPTO_MODE_HMAC_MD5: 511 - case CRYPTO_MODE_HASH_MD5: 512 - statesize = sizeof(struct md5_state); 513 - break; 514 - case CRYPTO_MODE_HASH_SHA224: 515 - case CRYPTO_MODE_HASH_SHA256: 516 - case CRYPTO_MODE_HMAC_SHA224: 517 - case CRYPTO_MODE_HMAC_SHA256: 518 - statesize = sizeof(struct sha256_state); 519 - break; 520 - case CRYPTO_MODE_HMAC_SHA512: 521 - case CRYPTO_MODE_HASH_SHA512: 522 - statesize = sizeof(struct sha512_state); 523 - break; 524 - case CRYPTO_MODE_HMAC_SHA384: 525 - case CRYPTO_MODE_HASH_SHA384: 526 - statesize = sizeof(struct spacc_crypto_reqctx); 527 - break; 528 - case CRYPTO_MODE_HASH_SHA3_224: 529 - case CRYPTO_MODE_HASH_SHA3_256: 530 - case CRYPTO_MODE_HASH_SHA3_384: 531 - case CRYPTO_MODE_HASH_SHA3_512: 532 - statesize = sizeof(struct sha3_state); 533 - break; 534 - case CRYPTO_MODE_HMAC_SM3: 535 - case CRYPTO_MODE_MAC_MICHAEL: 536 - statesize = sizeof(struct spacc_crypto_reqctx); 537 - break; 538 - default: 539 - break; 540 - } 541 - 542 - return statesize; 543 - } 544 - 545 - static int spacc_hash_cra_init(struct crypto_tfm *tfm) 546 - { 547 - const struct spacc_alg *salg = spacc_tfm_ahash(tfm); 548 - struct spacc_crypto_ctx *tctx = crypto_tfm_ctx(tfm); 549 - struct spacc_priv *priv = NULL; 550 - 551 - tctx->handle = -1; 552 - tctx->ctx_valid = false; 553 - tctx->dev = get_device(salg->dev[0]); 554 - 555 - if (salg->mode->sw_fb) { 556 - tctx->fb.hash = crypto_alloc_ahash(salg->calg->cra_name, 0, 557 - CRYPTO_ALG_NEED_FALLBACK); 558 - 559 - if (IS_ERR(tctx->fb.hash)) { 560 - if (tctx->handle >= 0) 561 - spacc_close(&priv->spacc, tctx->handle); 562 - put_device(tctx->dev); 563 - return PTR_ERR(tctx->fb.hash); 564 - } 565 - 566 - crypto_ahash_set_statesize(__crypto_ahash_cast(tfm), 567 - crypto_ahash_statesize(tctx->fb.hash)); 568 - 569 - crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 570 - sizeof(struct spacc_crypto_reqctx) + 571 - crypto_ahash_reqsize(tctx->fb.hash)); 572 - 573 - } else { 574 - crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 575 - sizeof(struct spacc_crypto_reqctx)); 576 - } 577 - 578 - return 0; 579 - } 580 - 581 - static void spacc_hash_cra_exit(struct crypto_tfm *tfm) 582 - { 583 - struct spacc_crypto_ctx *tctx = crypto_tfm_ctx(tfm); 584 - struct spacc_priv *priv = dev_get_drvdata(tctx->dev); 585 - 586 - crypto_free_ahash(tctx->fb.hash); 587 - 588 - if (tctx->handle >= 0) 589 - spacc_close(&priv->spacc, tctx->handle); 590 - 591 - put_device(tctx->dev); 592 - } 593 - 594 - static int spacc_hash_init(struct ahash_request *req) 595 - { 596 - int rc = 0; 597 - struct crypto_ahash *reqtfm = crypto_ahash_reqtfm(req); 598 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(reqtfm); 599 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 600 - 601 - ctx->digest_buf = NULL; 602 - ctx->single_shot = 0; 603 - ctx->total_nents = 0; 604 - tctx->tmp_sgl = NULL; 605 - 606 - ahash_request_set_tfm(&ctx->fb.hash_req, tctx->fb.hash); 607 - ctx->fb.hash_req.base.flags = req->base.flags & 608 - CRYPTO_TFM_REQ_MAY_SLEEP; 609 - rc = crypto_ahash_init(&ctx->fb.hash_req); 610 - 611 - return rc; 612 - } 613 - 614 - static int spacc_hash_update(struct ahash_request *req) 615 - { 616 - int rc; 617 - int nbytes = req->nbytes; 618 - 619 - struct crypto_ahash *reqtfm = crypto_ahash_reqtfm(req); 620 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(reqtfm); 621 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 622 - 623 - if (!nbytes) 624 - return 0; 625 - 626 - pr_debug("%s Using SW fallback\n", __func__); 627 - 628 - 629 - ahash_request_set_tfm(&ctx->fb.hash_req, tctx->fb.hash); 630 - ctx->fb.hash_req.base.flags = req->base.flags & 631 - CRYPTO_TFM_REQ_MAY_SLEEP; 632 - ctx->fb.hash_req.nbytes = req->nbytes; 633 - ctx->fb.hash_req.src = req->src; 634 - 635 - rc = crypto_ahash_update(&ctx->fb.hash_req); 636 - return rc; 637 - } 638 - 639 - static int spacc_hash_final(struct ahash_request *req) 640 - { 641 - struct crypto_ahash *reqtfm = crypto_ahash_reqtfm(req); 642 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(reqtfm); 643 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 644 - int rc; 645 - 646 - 647 - ahash_request_set_tfm(&ctx->fb.hash_req, tctx->fb.hash); 648 - ctx->fb.hash_req.base.flags = req->base.flags & 649 - CRYPTO_TFM_REQ_MAY_SLEEP; 650 - ctx->fb.hash_req.result = req->result; 651 - 652 - rc = crypto_ahash_final(&ctx->fb.hash_req); 653 - return rc; 654 - } 655 - 656 - static int spacc_hash_digest(struct ahash_request *req) 657 - { 658 - int ret, final = 0; 659 - int rc; 660 - struct crypto_ahash *reqtfm = crypto_ahash_reqtfm(req); 661 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(reqtfm); 662 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 663 - struct spacc_priv *priv = dev_get_drvdata(tctx->dev); 664 - const struct spacc_alg *salg = spacc_tfm_ahash(&reqtfm->base); 665 - 666 - 667 - /* direct single shot digest call */ 668 - ctx->single_shot = 1; 669 - ctx->total_nents = sg_nents(req->src); 670 - 671 - /* alloc tmp_sgl */ 672 - tctx->tmp_sgl = kmalloc(sizeof(*(tctx->tmp_sgl)) * 2, GFP_KERNEL); 673 - 674 - if (!tctx->tmp_sgl) 675 - return -ENOMEM; 676 - 677 - sg_init_table(tctx->tmp_sgl, 2); 678 - tctx->tmp_sgl[0].length = 0; 679 - 680 - 681 - if (tctx->handle < 0 || !tctx->ctx_valid) { 682 - priv = NULL; 683 - pr_debug("%s: open SPAcc context\n", __func__); 684 - 685 - priv = dev_get_drvdata(salg->dev[0]); 686 - tctx->dev = get_device(salg->dev[0]); 687 - ret = spacc_isenabled(&priv->spacc, salg->mode->id, 0); 688 - if (ret) 689 - tctx->handle = spacc_open(&priv->spacc, 690 - CRYPTO_MODE_NULL, 691 - salg->mode->id, -1, 0, 692 - spacc_digest_cb, 693 - reqtfm); 694 - 695 - if (tctx->handle < 0) { 696 - put_device(salg->dev[0]); 697 - pr_debug("Failed to open SPAcc context\n"); 698 - goto fallback; 699 - } 700 - 701 - rc = spacc_set_operation(&priv->spacc, tctx->handle, 702 - OP_ENCRYPT, ICV_HASH, IP_ICV_OFFSET, 703 - 0, 0, 0); 704 - if (rc < 0) { 705 - spacc_close(&priv->spacc, tctx->handle); 706 - pr_debug("Failed to open SPAcc context\n"); 707 - tctx->handle = -1; 708 - put_device(tctx->dev); 709 - goto fallback; 710 - } 711 - tctx->ctx_valid = true; 712 - } 713 - 714 - rc = spacc_hash_init_dma(tctx->dev, req, final); 715 - if (rc < 0) 716 - goto fallback; 717 - 718 - if (rc == 0) 719 - return 0; 720 - 721 - rc = spacc_packet_enqueue_ddt(&priv->spacc, ctx->acb.new_handle, 722 - &ctx->src, &ctx->dst, req->nbytes, 723 - 0, req->nbytes, 0, 0, 0); 724 - 725 - if (rc < 0) { 726 - spacc_hash_cleanup_dma(tctx->dev, req); 727 - spacc_close(&priv->spacc, ctx->acb.new_handle); 728 - 729 - if (rc != -EBUSY) { 730 - pr_debug("Failed to enqueue job, ERR: %d\n", rc); 731 - return rc; 732 - } 733 - 734 - if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) 735 - return -EBUSY; 736 - 737 - goto fallback; 738 - } 739 - 740 - return -EINPROGRESS; 741 - 742 - fallback: 743 - /* Start from scratch as init is not called before digest */ 744 - ahash_request_set_tfm(&ctx->fb.hash_req, tctx->fb.hash); 745 - ctx->fb.hash_req.base.flags = req->base.flags & 746 - CRYPTO_TFM_REQ_MAY_SLEEP; 747 - 748 - ctx->fb.hash_req.nbytes = req->nbytes; 749 - ctx->fb.hash_req.src = req->src; 750 - ctx->fb.hash_req.result = req->result; 751 - 752 - return crypto_ahash_digest(&ctx->fb.hash_req); 753 - } 754 - 755 - static int spacc_hash_finup(struct ahash_request *req) 756 - { 757 - struct crypto_ahash *reqtfm = crypto_ahash_reqtfm(req); 758 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(reqtfm); 759 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 760 - int rc; 761 - 762 - ahash_request_set_tfm(&ctx->fb.hash_req, tctx->fb.hash); 763 - ctx->fb.hash_req.base.flags = req->base.flags & 764 - CRYPTO_TFM_REQ_MAY_SLEEP; 765 - ctx->fb.hash_req.nbytes = req->nbytes; 766 - ctx->fb.hash_req.src = req->src; 767 - ctx->fb.hash_req.result = req->result; 768 - 769 - rc = crypto_ahash_finup(&ctx->fb.hash_req); 770 - return rc; 771 - } 772 - 773 - static int spacc_hash_import(struct ahash_request *req, const void *in) 774 - { 775 - int rc; 776 - struct crypto_ahash *reqtfm = crypto_ahash_reqtfm(req); 777 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(reqtfm); 778 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 779 - 780 - ahash_request_set_tfm(&ctx->fb.hash_req, tctx->fb.hash); 781 - ctx->fb.hash_req.base.flags = req->base.flags & 782 - CRYPTO_TFM_REQ_MAY_SLEEP; 783 - 784 - rc = crypto_ahash_import(&ctx->fb.hash_req, in); 785 - return rc; 786 - } 787 - 788 - static int spacc_hash_export(struct ahash_request *req, void *out) 789 - { 790 - int rc; 791 - struct crypto_ahash *reqtfm = crypto_ahash_reqtfm(req); 792 - struct spacc_crypto_ctx *tctx = crypto_ahash_ctx(reqtfm); 793 - struct spacc_crypto_reqctx *ctx = ahash_request_ctx(req); 794 - 795 - ahash_request_set_tfm(&ctx->fb.hash_req, tctx->fb.hash); 796 - ctx->fb.hash_req.base.flags = req->base.flags & 797 - CRYPTO_TFM_REQ_MAY_SLEEP; 798 - 799 - rc = crypto_ahash_export(&ctx->fb.hash_req, out); 800 - return rc; 801 - } 802 - 803 - static const struct ahash_alg spacc_hash_template = { 804 - .init = spacc_hash_init, 805 - .update = spacc_hash_update, 806 - .final = spacc_hash_final, 807 - .finup = spacc_hash_finup, 808 - .digest = spacc_hash_digest, 809 - .setkey = spacc_hash_setkey, 810 - .export = spacc_hash_export, 811 - .import = spacc_hash_import, 812 - 813 - .halg.base = { 814 - .cra_priority = 300, 815 - .cra_module = THIS_MODULE, 816 - .cra_init = spacc_hash_cra_init, 817 - .cra_exit = spacc_hash_cra_exit, 818 - .cra_ctxsize = sizeof(struct spacc_crypto_ctx), 819 - .cra_flags = CRYPTO_ALG_TYPE_AHASH | 820 - CRYPTO_ALG_ASYNC | 821 - CRYPTO_ALG_NEED_FALLBACK | 822 - CRYPTO_ALG_OPTIONAL_KEY 823 - }, 824 - }; 825 - 826 - static int spacc_register_hash(struct spacc_alg *salg) 827 - { 828 - int rc; 829 - 830 - salg->calg = &salg->alg.hash.halg.base; 831 - salg->alg.hash = spacc_hash_template; 832 - 833 - spacc_init_calg(salg->calg, salg->mode); 834 - salg->alg.hash.halg.digestsize = salg->mode->hashlen; 835 - salg->alg.hash.halg.statesize = spacc_set_statesize(salg); 836 - 837 - rc = crypto_register_ahash(&salg->alg.hash); 838 - if (rc < 0) 839 - return rc; 840 - 841 - mutex_lock(&spacc_hash_alg_mutex); 842 - list_add(&salg->list, &spacc_hash_alg_list); 843 - mutex_unlock(&spacc_hash_alg_mutex); 844 - 845 - return 0; 846 - } 847 - 848 - 849 - int probe_hashes(struct platform_device *spacc_pdev) 850 - { 851 - int rc; 852 - unsigned int i; 853 - int registered = 0; 854 - struct spacc_alg *salg; 855 - struct spacc_priv *priv = dev_get_drvdata(&spacc_pdev->dev); 856 - 857 - spacc_hash_pool = dma_pool_create("spacc-digest", &spacc_pdev->dev, 858 - SPACC_MAX_DIGEST_SIZE, 859 - SPACC_DMA_ALIGN, SPACC_DMA_BOUNDARY); 860 - 861 - if (!spacc_hash_pool) 862 - return -ENOMEM; 863 - 864 - for (i = 0; i < ARRAY_SIZE(possible_hashes); i++) 865 - possible_hashes[i].valid = 0; 866 - 867 - for (i = 0; i < ARRAY_SIZE(possible_hashes); i++) { 868 - if (possible_hashes[i].valid == 0 && 869 - spacc_isenabled(&priv->spacc, 870 - possible_hashes[i].id & 0xFF, 871 - possible_hashes[i].hashlen)) { 872 - 873 - salg = kmalloc(sizeof(*salg), GFP_KERNEL); 874 - if (!salg) 875 - return -ENOMEM; 876 - 877 - salg->mode = &possible_hashes[i]; 878 - 879 - /* Copy all dev's over to the salg */ 880 - salg->dev[0] = &spacc_pdev->dev; 881 - salg->dev[1] = NULL; 882 - 883 - rc = spacc_register_hash(salg); 884 - if (rc < 0) { 885 - kfree(salg); 886 - continue; 887 - } 888 - pr_debug("registered %s\n", 889 - possible_hashes[i].name); 890 - 891 - registered++; 892 - possible_hashes[i].valid = 1; 893 - } 894 - } 895 - 896 - return registered; 897 - } 898 - 899 - int spacc_unregister_hash_algs(void) 900 - { 901 - struct spacc_alg *salg, *tmp; 902 - 903 - mutex_lock(&spacc_hash_alg_mutex); 904 - list_for_each_entry_safe(salg, tmp, &spacc_hash_alg_list, list) { 905 - crypto_unregister_alg(salg->calg); 906 - list_del(&salg->list); 907 - kfree(salg); 908 - } 909 - mutex_unlock(&spacc_hash_alg_mutex); 910 - 911 - dma_pool_destroy(spacc_hash_pool); 912 - 913 - return 0; 914 - }
-2513
drivers/crypto/dwc-spacc/spacc_core.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - 3 - #include <linux/of_device.h> 4 - #include <linux/vmalloc.h> 5 - #include <linux/platform_device.h> 6 - #include <linux/interrupt.h> 7 - #include "spacc_hal.h" 8 - #include "spacc_core.h" 9 - 10 - static const u8 spacc_ctrl_map[SPACC_CTRL_VER_SIZE][SPACC_CTRL_MAPSIZE] = { 11 - { 0, 8, 4, 12, 24, 16, 31, 25, 26, 27, 28, 29, 14, 15 }, 12 - { 0, 8, 3, 12, 24, 16, 31, 25, 26, 27, 28, 29, 14, 15 }, 13 - { 0, 4, 8, 13, 15, 16, 24, 25, 26, 27, 28, 29, 30, 31 } 14 - }; 15 - 16 - static const int keysizes[2][7] = { 17 - /* 1 2 4 8 16 32 64 */ 18 - { 5, 8, 16, 24, 32, 0, 0 }, /* cipher key sizes*/ 19 - { 8, 16, 20, 24, 32, 64, 128 }, /* hash key sizes*/ 20 - }; 21 - 22 - 23 - /* bits are 40, 64, 128, 192, 256, and top bit for hash */ 24 - static const unsigned char template[] = { 25 - [CRYPTO_MODE_NULL] = 0, 26 - [CRYPTO_MODE_AES_ECB] = 28, /* AESECB 128/224/256 */ 27 - [CRYPTO_MODE_AES_CBC] = 28, /* AESCBC 128/224/256 */ 28 - [CRYPTO_MODE_AES_CTR] = 28, /* AESCTR 128/224/256 */ 29 - [CRYPTO_MODE_AES_CCM] = 28, /* AESCCM 128/224/256 */ 30 - [CRYPTO_MODE_AES_GCM] = 28, /* AESGCM 128/224/256 */ 31 - [CRYPTO_MODE_AES_F8] = 28, /* AESF8 128/224/256 */ 32 - [CRYPTO_MODE_AES_XTS] = 20, /* AESXTS 128/256 */ 33 - [CRYPTO_MODE_AES_CFB] = 28, /* AESCFB 128/224/256 */ 34 - [CRYPTO_MODE_AES_OFB] = 28, /* AESOFB 128/224/256 */ 35 - [CRYPTO_MODE_AES_CS1] = 28, /* AESCS1 128/224/256 */ 36 - [CRYPTO_MODE_AES_CS2] = 28, /* AESCS2 128/224/256 */ 37 - [CRYPTO_MODE_AES_CS3] = 28, /* AESCS3 128/224/256 */ 38 - [CRYPTO_MODE_MULTI2_ECB] = 0, /* MULTI2 */ 39 - [CRYPTO_MODE_MULTI2_CBC] = 0, /* MULTI2 */ 40 - [CRYPTO_MODE_MULTI2_OFB] = 0, /* MULTI2 */ 41 - [CRYPTO_MODE_MULTI2_CFB] = 0, /* MULTI2 */ 42 - [CRYPTO_MODE_3DES_CBC] = 8, /* 3DES CBC */ 43 - [CRYPTO_MODE_3DES_ECB] = 8, /* 3DES ECB */ 44 - [CRYPTO_MODE_DES_CBC] = 2, /* DES CBC */ 45 - [CRYPTO_MODE_DES_ECB] = 2, /* DES ECB */ 46 - [CRYPTO_MODE_KASUMI_ECB] = 4, /* KASUMI ECB */ 47 - [CRYPTO_MODE_KASUMI_F8] = 4, /* KASUMI F8 */ 48 - [CRYPTO_MODE_SNOW3G_UEA2] = 4, /* SNOW3G */ 49 - [CRYPTO_MODE_ZUC_UEA3] = 4, /* ZUC */ 50 - [CRYPTO_MODE_CHACHA20_STREAM] = 16, /* CHACHA20 */ 51 - [CRYPTO_MODE_CHACHA20_POLY1305] = 16, /* CHACHA20 */ 52 - [CRYPTO_MODE_SM4_ECB] = 4, /* SM4ECB 128 */ 53 - [CRYPTO_MODE_SM4_CBC] = 4, /* SM4CBC 128 */ 54 - [CRYPTO_MODE_SM4_CFB] = 4, /* SM4CFB 128 */ 55 - [CRYPTO_MODE_SM4_OFB] = 4, /* SM4OFB 128 */ 56 - [CRYPTO_MODE_SM4_CTR] = 4, /* SM4CTR 128 */ 57 - [CRYPTO_MODE_SM4_CCM] = 4, /* SM4CCM 128 */ 58 - [CRYPTO_MODE_SM4_GCM] = 4, /* SM4GCM 128 */ 59 - [CRYPTO_MODE_SM4_F8] = 4, /* SM4F8 128 */ 60 - [CRYPTO_MODE_SM4_XTS] = 4, /* SM4XTS 128 */ 61 - [CRYPTO_MODE_SM4_CS1] = 4, /* SM4CS1 128 */ 62 - [CRYPTO_MODE_SM4_CS2] = 4, /* SM4CS2 128 */ 63 - [CRYPTO_MODE_SM4_CS3] = 4, /* SM4CS3 128 */ 64 - 65 - [CRYPTO_MODE_HASH_MD5] = 242, 66 - [CRYPTO_MODE_HMAC_MD5] = 242, 67 - [CRYPTO_MODE_HASH_SHA1] = 242, 68 - [CRYPTO_MODE_HMAC_SHA1] = 242, 69 - [CRYPTO_MODE_HASH_SHA224] = 242, 70 - [CRYPTO_MODE_HMAC_SHA224] = 242, 71 - [CRYPTO_MODE_HASH_SHA256] = 242, 72 - [CRYPTO_MODE_HMAC_SHA256] = 242, 73 - [CRYPTO_MODE_HASH_SHA384] = 242, 74 - [CRYPTO_MODE_HMAC_SHA384] = 242, 75 - [CRYPTO_MODE_HASH_SHA512] = 242, 76 - [CRYPTO_MODE_HMAC_SHA512] = 242, 77 - [CRYPTO_MODE_HASH_SHA512_224] = 242, 78 - [CRYPTO_MODE_HMAC_SHA512_224] = 242, 79 - [CRYPTO_MODE_HASH_SHA512_256] = 242, 80 - [CRYPTO_MODE_HMAC_SHA512_256] = 242, 81 - [CRYPTO_MODE_MAC_XCBC] = 154, /* XaCBC */ 82 - [CRYPTO_MODE_MAC_CMAC] = 154, /* CMAC */ 83 - [CRYPTO_MODE_MAC_KASUMI_F9] = 130, /* KASUMI */ 84 - [CRYPTO_MODE_MAC_SNOW3G_UIA2] = 130, /* SNOW */ 85 - [CRYPTO_MODE_MAC_ZUC_UIA3] = 130, /* ZUC */ 86 - [CRYPTO_MODE_MAC_POLY1305] = 144, 87 - [CRYPTO_MODE_SSLMAC_MD5] = 130, 88 - [CRYPTO_MODE_SSLMAC_SHA1] = 132, 89 - [CRYPTO_MODE_HASH_CRC32] = 0, 90 - [CRYPTO_MODE_MAC_MICHAEL] = 129, 91 - 92 - [CRYPTO_MODE_HASH_SHA3_224] = 242, 93 - [CRYPTO_MODE_HASH_SHA3_256] = 242, 94 - [CRYPTO_MODE_HASH_SHA3_384] = 242, 95 - [CRYPTO_MODE_HASH_SHA3_512] = 242, 96 - [CRYPTO_MODE_HASH_SHAKE128] = 242, 97 - [CRYPTO_MODE_HASH_SHAKE256] = 242, 98 - [CRYPTO_MODE_HASH_CSHAKE128] = 130, 99 - [CRYPTO_MODE_HASH_CSHAKE256] = 130, 100 - [CRYPTO_MODE_MAC_KMAC128] = 242, 101 - [CRYPTO_MODE_MAC_KMAC256] = 242, 102 - [CRYPTO_MODE_MAC_KMACXOF128] = 242, 103 - [CRYPTO_MODE_MAC_KMACXOF256] = 242, 104 - [CRYPTO_MODE_HASH_SM3] = 242, 105 - [CRYPTO_MODE_HMAC_SM3] = 242, 106 - [CRYPTO_MODE_MAC_SM4_XCBC] = 242, 107 - [CRYPTO_MODE_MAC_SM4_CMAC] = 242, 108 - }; 109 - 110 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_AUTODETECT) 111 - static const struct { 112 - unsigned int min_version; 113 - struct { 114 - int outlen; 115 - unsigned char data[64]; 116 - } test[7]; 117 - } testdata[CRYPTO_MODE_LAST] = { 118 - /* NULL*/ 119 - { .min_version = 0x65, 120 - .test[0].outlen = 0 121 - }, 122 - 123 - /* AES_ECB*/ 124 - { .min_version = 0x65, 125 - .test[2].outlen = 16, .test[2].data = { 0xc6, 0xa1, 0x3b, 0x37, 126 - 0x87, 0x8f, 0x5b, 0x82, 0x6f, 0x4f, 0x81, 0x62, 0xa1, 127 - 0xc8, 0xd8, 0x79, }, 128 - .test[3].outlen = 16, .test[3].data = { 0x91, 0x62, 0x51, 0x82, 129 - 0x1c, 0x73, 0xa5, 0x22, 0xc3, 0x96, 0xd6, 0x27, 0x38, 130 - 0x01, 0x96, 0x07, }, 131 - .test[4].outlen = 16, .test[4].data = { 0xf2, 0x90, 0x00, 0xb6, 132 - 0x2a, 0x49, 0x9f, 0xd0, 0xa9, 0xf3, 0x9a, 0x6a, 0xdd, 133 - 0x2e, 0x77, 0x80, }, 134 - }, 135 - 136 - /* AES_CBC*/ 137 - { .min_version = 0x65, 138 - .test[2].outlen = 16, .test[2].data = { 0x0a, 0x94, 0x0b, 0xb5, 139 - 0x41, 0x6e, 0xf0, 0x45, 0xf1, 0xc3, 0x94, 0x58, 0xc6, 140 - 0x53, 0xea, 0x5a, }, 141 - .test[3].outlen = 16, .test[3].data = { 0x00, 0x60, 0xbf, 0xfe, 142 - 0x46, 0x83, 0x4b, 0xb8, 0xda, 0x5c, 0xf9, 0xa6, 0x1f, 143 - 0xf2, 0x20, 0xae, }, 144 - .test[4].outlen = 16, .test[4].data = { 0x5a, 0x6e, 0x04, 0x57, 145 - 0x08, 0xfb, 0x71, 0x96, 0xf0, 0x2e, 0x55, 0x3d, 0x02, 146 - 0xc3, 0xa6, 0x92, }, 147 - }, 148 - 149 - /* AES_CTR*/ 150 - { .min_version = 0x65, 151 - .test[2].outlen = 16, .test[2].data = { 0x0a, 0x94, 0x0b, 0xb5, 152 - 0x41, 0x6e, 0xf0, 0x45, 0xf1, 0xc3, 0x94, 0x58, 0xc6, 153 - 0x53, 0xea, 0x5a, }, 154 - .test[3].outlen = 16, .test[3].data = { 0x00, 0x60, 0xbf, 0xfe, 155 - 0x46, 0x83, 0x4b, 0xb8, 0xda, 0x5c, 0xf9, 0xa6, 0x1f, 156 - 0xf2, 0x20, 0xae, }, 157 - .test[4].outlen = 16, .test[4].data = { 0x5a, 0x6e, 0x04, 0x57, 158 - 0x08, 0xfb, 0x71, 0x96, 0xf0, 0x2e, 0x55, 0x3d, 0x02, 159 - 0xc3, 0xa6, 0x92, }, 160 - }, 161 - 162 - /* AES_CCM*/ 163 - { .min_version = 0x65, 164 - .test[2].outlen = 32, .test[2].data = { 0x02, 0x63, 0xec, 0x94, 165 - 0x66, 0x18, 0x72, 0x96, 0x9a, 0xda, 0xfd, 0x0f, 0x4b, 166 - 0xa4, 0x0f, 0xdc, 0xa5, 0x09, 0x92, 0x93, 0xb6, 0xb4, 167 - 0x38, 0x34, 0x63, 0x72, 0x50, 0x4c, 0xfc, 0x8a, 0x63, 168 - 0x02, }, 169 - .test[3].outlen = 32, .test[3].data = { 0x29, 0xf7, 0x63, 0xe8, 170 - 0xa1, 0x75, 0xc6, 0xbf, 0xa5, 0x54, 0x94, 0x89, 0x12, 171 - 0x84, 0x45, 0xf5, 0x9b, 0x27, 0xeb, 0xb1, 0xa4, 0x65, 172 - 0x93, 0x6e, 0x5a, 0xc0, 0xa2, 0xa3, 0xe2, 0x6c, 0x46, 173 - 0x29, }, 174 - .test[4].outlen = 32, .test[4].data = { 0x60, 0xf3, 0x10, 0xd5, 175 - 0xc3, 0x85, 0x58, 0x5d, 0x55, 0x16, 0xfb, 0x51, 0x72, 176 - 0xe5, 0x20, 0xcf, 0x8e, 0x87, 0x6d, 0x72, 0xc8, 0x44, 177 - 0xbe, 0x6d, 0xa2, 0xd6, 0xf4, 0xba, 0xec, 0xb4, 0xec, 178 - 0x39, }, 179 - }, 180 - 181 - /* AES_GCM*/ 182 - { .min_version = 0x65, 183 - .test[2].outlen = 32, .test[2].data = { 0x93, 0x6c, 0xa7, 0xce, 184 - 0x66, 0x1b, 0xf7, 0x54, 0x4b, 0xd2, 0x61, 0x8a, 0x36, 185 - 0xa3, 0x70, 0x08, 0xc0, 0xd7, 0xd0, 0x77, 0xc5, 0x64, 186 - 0x76, 0xdb, 0x48, 0x4a, 0x53, 0xe3, 0x6c, 0x93, 0x34, 187 - 0x0f, }, 188 - .test[3].outlen = 32, .test[3].data = { 0xe6, 0xf9, 0x22, 0x9b, 189 - 0x99, 0xb9, 0xc9, 0x0e, 0xd0, 0x33, 0xdc, 0x82, 0xff, 190 - 0xa9, 0xdc, 0x70, 0x4c, 0xcd, 0xc4, 0x1b, 0xa3, 0x5a, 191 - 0x87, 0x5d, 0xd8, 0xef, 0xb6, 0x48, 0xbb, 0x0c, 0x92, 192 - 0x60, }, 193 - .test[4].outlen = 32, .test[4].data = { 0x47, 0x02, 0xd6, 0x1b, 194 - 0xc5, 0xe5, 0xc2, 0x1b, 0x8d, 0x41, 0x97, 0x8b, 0xb1, 195 - 0xe9, 0x78, 0x6d, 0x48, 0x6f, 0x78, 0x81, 0xc7, 0x98, 196 - 0xcc, 0xf5, 0x28, 0xf1, 0x01, 0x7c, 0xe8, 0xf6, 0x09, 197 - 0x78, }, 198 - }, 199 - 200 - /* AES-F8*/ 201 - { .min_version = 0x65, 202 - .test[0].outlen = 0 203 - }, 204 - 205 - /* AES-XTS*/ 206 - { .min_version = 0x65, 207 - .test[2].outlen = 32, .test[2].data = { 0xa0, 0x1a, 0x6f, 0x09, 208 - 0xfa, 0xef, 0xd2, 0x72, 0xc3, 0x9b, 0xad, 0x35, 0x52, 209 - 0xfc, 0xa1, 0xcb, 0x33, 0x69, 0x51, 0xc5, 0x23, 0xbe, 210 - 0xac, 0xa5, 0x4a, 0xf2, 0xfc, 0x77, 0x71, 0x6f, 0x9a, 211 - 0x86, }, 212 - .test[4].outlen = 32, .test[4].data = { 0x05, 0x45, 0x91, 0x86, 213 - 0xf2, 0x2d, 0x97, 0x93, 0xf3, 0xa0, 0xbb, 0x29, 0xc7, 214 - 0x9c, 0xc1, 0x4c, 0x3b, 0x8f, 0xdd, 0x9d, 0xda, 0xc7, 215 - 0xb5, 0xaa, 0xc2, 0x7c, 0x2e, 0x71, 0xce, 0x7f, 0xce, 216 - 0x0e, }, 217 - }, 218 - 219 - /* AES-CFB*/ 220 - { .min_version = 0x65, 221 - .test[0].outlen = 0 222 - }, 223 - 224 - /* AES-OFB*/ 225 - { .min_version = 0x65, 226 - .test[0].outlen = 0 227 - }, 228 - 229 - /* AES-CS1*/ 230 - { .min_version = 0x65, 231 - .test[2].outlen = 31, .test[2].data = { 0x0a, 0x94, 0x0b, 0xb5, 232 - 0x41, 0x6e, 0xf0, 0x45, 0xf1, 0xc3, 0x94, 0x58, 0xc6, 233 - 0x53, 0xea, 0xae, 0xe7, 0x1e, 0xa5, 0x41, 0xd7, 0xae, 234 - 0x4b, 0xeb, 0x60, 0xbe, 0xcc, 0x59, 0x3f, 0xb6, 0x63, 235 - }, 236 - .test[3].outlen = 31, .test[3].data = { 0x00, 0x60, 0xbf, 0xfe, 237 - 0x46, 0x83, 0x4b, 0xb8, 0xda, 0x5c, 0xf9, 0xa6, 0x1f, 238 - 0xf2, 0x20, 0x2e, 0x84, 0xcb, 0x12, 0xa3, 0x59, 0x17, 239 - 0xb0, 0x9e, 0x25, 0xa2, 0xa2, 0x3d, 0xf1, 0x9f, 0xdc, 240 - }, 241 - .test[4].outlen = 31, .test[4].data = { 0x5a, 0x6e, 0x04, 0x57, 242 - 0x08, 0xfb, 0x71, 0x96, 0xf0, 0x2e, 0x55, 0x3d, 0x02, 243 - 0xc3, 0xa6, 0xcd, 0xfc, 0x25, 0x35, 0x31, 0x0b, 0xf5, 244 - 0x6b, 0x2e, 0xb7, 0x8a, 0xa2, 0x5a, 0xdd, 0x77, 0x51, 245 - }, 246 - }, 247 - 248 - /* AES-CS2*/ 249 - { .min_version = 0x65, 250 - .test[2].outlen = 31, .test[2].data = { 0xae, 0xe7, 0x1e, 0xa5, 251 - 0x41, 0xd7, 0xae, 0x4b, 0xeb, 0x60, 0xbe, 0xcc, 0x59, 252 - 0x3f, 0xb6, 0x63, 0x0a, 0x94, 0x0b, 0xb5, 0x41, 0x6e, 253 - 0xf0, 0x45, 0xf1, 0xc3, 0x94, 0x58, 0xc6, 0x53, 0xea, 254 - }, 255 - .test[3].outlen = 31, .test[3].data = { 0x2e, 0x84, 0xcb, 0x12, 256 - 0xa3, 0x59, 0x17, 0xb0, 0x9e, 0x25, 0xa2, 0xa2, 0x3d, 257 - 0xf1, 0x9f, 0xdc, 0x00, 0x60, 0xbf, 0xfe, 0x46, 0x83, 258 - 0x4b, 0xb8, 0xda, 0x5c, 0xf9, 0xa6, 0x1f, 0xf2, 0x20, 259 - }, 260 - .test[4].outlen = 31, .test[4].data = { 0xcd, 0xfc, 0x25, 0x35, 261 - 0x31, 0x0b, 0xf5, 0x6b, 0x2e, 0xb7, 0x8a, 0xa2, 0x5a, 262 - 0xdd, 0x77, 0x51, 0x5a, 0x6e, 0x04, 0x57, 0x08, 0xfb, 263 - 0x71, 0x96, 0xf0, 0x2e, 0x55, 0x3d, 0x02, 0xc3, 0xa6, 264 - }, 265 - }, 266 - 267 - /* AES-CS3*/ 268 - { .min_version = 0x65, 269 - .test[2].outlen = 31, .test[2].data = { 0xae, 0xe7, 0x1e, 0xa5, 270 - 0x41, 0xd7, 0xae, 0x4b, 0xeb, 0x60, 0xbe, 0xcc, 0x59, 271 - 0x3f, 0xb6, 0x63, 0x0a, 0x94, 0x0b, 0xb5, 0x41, 0x6e, 272 - 0xf0, 0x45, 0xf1, 0xc3, 0x94, 0x58, 0xc6, 0x53, 0xea, 273 - }, 274 - .test[3].outlen = 31, .test[3].data = { 0x2e, 0x84, 0xcb, 0x12, 275 - 0xa3, 0x59, 0x17, 0xb0, 0x9e, 0x25, 0xa2, 0xa2, 0x3d, 276 - 0xf1, 0x9f, 0xdc, 0x00, 0x60, 0xbf, 0xfe, 0x46, 0x83, 277 - 0x4b, 0xb8, 0xda, 0x5c, 0xf9, 0xa6, 0x1f, 0xf2, 0x20, 278 - }, 279 - .test[4].outlen = 31, .test[4].data = { 0xcd, 0xfc, 0x25, 0x35, 280 - 0x31, 0x0b, 0xf5, 0x6b, 0x2e, 0xb7, 0x8a, 0xa2, 0x5a, 281 - 0xdd, 0x77, 0x51, 0x5a, 0x6e, 0x04, 0x57, 0x08, 0xfb, 282 - 0x71, 0x96, 0xf0, 0x2e, 0x55, 0x3d, 0x02, 0xc3, 0xa6, 283 - }, 284 - }, 285 - 286 - /* MULTI2*/ 287 - { .min_version = 0x65, 288 - .test[0].outlen = 0 289 - }, 290 - { .min_version = 0x65, 291 - .test[0].outlen = 0 292 - }, 293 - { .min_version = 0x65, 294 - .test[0].outlen = 0 295 - }, 296 - { .min_version = 0x65, 297 - .test[0].outlen = 0 298 - }, 299 - 300 - /* 3DES_CBC*/ 301 - { .min_version = 0x65, 302 - .test[3].outlen = 16, .test[3].data = { 0x58, 0xed, 0x24, 0x8f, 303 - 0x77, 0xf6, 0xb1, 0x9e, 0x47, 0xd9, 0xb7, 0x4a, 0x4f, 304 - 0x5a, 0xe6, 0x6d, } 305 - }, 306 - 307 - /* 3DES_ECB*/ 308 - { .min_version = 0x65, 309 - .test[3].outlen = 16, .test[3].data = { 0x89, 0x4b, 0xc3, 0x08, 310 - 0x54, 0x26, 0xa4, 0x41, 0x89, 0x4b, 0xc3, 0x08, 0x54, 311 - 0x26, 0xa4, 0x41, } 312 - }, 313 - 314 - /* DES_CBC*/ 315 - { .min_version = 0x65, 316 - .test[1].outlen = 16, .test[1].data = { 0xe1, 0xb2, 0x46, 0xe5, 317 - 0xa7, 0xc7, 0x4c, 0xbc, 0xd5, 0xf0, 0x8e, 0x25, 0x3b, 318 - 0xfa, 0x23, 0x80, } 319 - }, 320 - 321 - /* DES_ECB*/ 322 - { .min_version = 0x65, 323 - .test[1].outlen = 16, .test[1].data = { 0xa5, 0x17, 0x3a, 324 - 0xd5, 0x95, 0x7b, 0x43, 0x70, 0xa5, 0x17, 0x3a, 0xd5, 325 - 0x95, 0x7b, 0x43, 0x70, } 326 - }, 327 - 328 - /* KASUMI_ECB*/ 329 - { .min_version = 0x65, 330 - .test[2].outlen = 16, .test[2].data = { 0x04, 0x7d, 0x5d, 331 - 0x2c, 0x8c, 0x2e, 0x91, 0xb3, 0x04, 0x7d, 0x5d, 0x2c, 332 - 0x8c, 0x2e, 0x91, 0xb3, } }, 333 - 334 - /* KASUMI_F8*/ 335 - { .min_version = 0x65, 336 - .test[2].outlen = 16, .test[2].data = { 0xfc, 0xf7, 0x45, 337 - 0xee, 0x1d, 0xbb, 0xa4, 0x57, 0xa7, 0x45, 0xdc, 0x6b, 338 - 0x2a, 0x1b, 0x50, 0x88, } 339 - }, 340 - 341 - /* SNOW3G UEA2*/ 342 - { .min_version = 0x65, 343 - .test[2].outlen = 16, .test[2].data = { 0x95, 0xd3, 0xc8, 344 - 0x13, 0xc0, 0x20, 0x24, 0xa3, 0x76, 0x24, 0xd1, 0x98, 345 - 0xb6, 0x67, 0x4d, 0x4c, } 346 - }, 347 - 348 - /* ZUC UEA3*/ 349 - { .min_version = 0x65, 350 - .test[2].outlen = 16, .test[2].data = { 0xda, 0xdf, 0xb6, 351 - 0xa2, 0xac, 0x9d, 0xba, 0xfe, 0x18, 0x9c, 0x0c, 0x75, 352 - 0x79, 0xc6, 0xe0, 0x4e, } 353 - }, 354 - 355 - /* CHACHA20_STREAM*/ 356 - { .min_version = 0x65, 357 - .test[4].outlen = 16, .test[4].data = { 0x55, 0xdf, 0x91, 358 - 0xe9, 0x27, 0x01, 0x37, 0x69, 0xdb, 0x38, 0xd4, 0x28, 359 - 0x01, 0x79, 0x76, 0x64 } 360 - }, 361 - 362 - /* CHACHA20_POLY1305 (AEAD)*/ 363 - { .min_version = 0x65, 364 - .test[4].outlen = 16, .test[4].data = { 0x89, 0xfb, 0x08, 365 - 0x00, 0x29, 0x17, 0xa5, 0x40, 0xb7, 0x83, 0x3f, 0xf3, 366 - 0x98, 0x1d, 0x0e, 0x63 } 367 - }, 368 - 369 - /* SM4_ECB 128*/ 370 - { .min_version = 0x65, 371 - .test[2].outlen = 16, .test[2].data = { 0x1e, 0x96, 0x34, 372 - 0xb7, 0x70, 0xf9, 0xae, 0xba, 0xa9, 0x34, 0x4f, 0x5a, 373 - 0xff, 0x9f, 0x82, 0xa3 } 374 - }, 375 - 376 - /* SM4_CBC 128*/ 377 - { .min_version = 0x65, 378 - .test[2].outlen = 16, .test[2].data = { 0x8f, 0x78, 0x76, 379 - 0x3e, 0xe0, 0x60, 0x13, 0xe0, 0xb7, 0x62, 0x2c, 0x42, 380 - 0x8f, 0xd0, 0x52, 0x8d } 381 - }, 382 - 383 - /* SM4_CFB 128*/ 384 - { .min_version = 0x65, 385 - .test[2].outlen = 16, .test[2].data = { 0x8f, 0x78, 0x76, 386 - 0x3e, 0xe0, 0x60, 0x13, 0xe0, 0xb7, 0x62, 0x2c, 0x42, 387 - 0x8f, 0xd0, 0x52, 0x8d } 388 - }, 389 - 390 - /* SM4_OFB 128*/ 391 - { .min_version = 0x65, 392 - .test[2].outlen = 16, .test[2].data = { 0x8f, 0x78, 0x76, 0x3e, 0xe0, 393 - 0x60, 0x13, 0xe0, 0xb7, 0x62, 0x2c, 0x42, 0x8f, 0xd0, 0x52, 394 - 0x8d } 395 - }, 396 - 397 - /* SM4_CTR 128*/ 398 - { .min_version = 0x65, 399 - .test[2].outlen = 16, .test[2].data = { 0x8f, 0x78, 0x76, 0x3e, 0xe0, 400 - 0x60, 0x13, 0xe0, 0xb7, 0x62, 0x2c, 0x42, 0x8f, 0xd0, 0x52, 401 - 0x8d } 402 - }, 403 - 404 - /* SM4_CCM 128*/ 405 - { .min_version = 0x65, 406 - .test[2].outlen = 16, .test[2].data = { 0x8e, 0x25, 0x5a, 407 - 0x13, 0xc7, 0x43, 0x4d, 0x95, 0xef, 0x14, 0x15, 0x11, 408 - 0xd0, 0xb9, 0x60, 0x5b } 409 - }, 410 - 411 - /* SM4_GCM 128*/ 412 - { .min_version = 0x65, 413 - .test[2].outlen = 16, .test[2].data = { 0x97, 0x46, 0xde, 414 - 0xfb, 0xc9, 0x6a, 0x85, 0x00, 0xff, 0x9c, 0x74, 0x4d, 415 - 0xd1, 0xbb, 0xf9, 0x66 } 416 - }, 417 - 418 - /* SM4_F8 128*/ 419 - { .min_version = 0x65, 420 - .test[2].outlen = 16, .test[2].data = { 0x77, 0x30, 0xff, 421 - 0x70, 0x46, 0xbc, 0xf4, 0xe3, 0x11, 0xf6, 0x27, 0xe2, 422 - 0xff, 0xd7, 0xc4, 0x2e } 423 - }, 424 - 425 - /* SM4_XTS 128*/ 426 - { .min_version = 0x65, 427 - .test[2].outlen = 16, .test[2].data = { 0x05, 0x3f, 0xb6, 428 - 0xe9, 0xb1, 0xff, 0x09, 0x4f, 0x9d, 0x69, 0x4d, 0xc2, 429 - 0xb6, 0xa1, 0x15, 0xde } 430 - }, 431 - 432 - /* SM4_CS1 128*/ 433 - { .min_version = 0x65, 434 - .test[2].outlen = 16, .test[2].data = { 0x8f, 0x78, 0x76, 435 - 0x3e, 0xe0, 0x60, 0x13, 0xe0, 0xb7, 0x62, 0x2c, 0x42, 436 - 0x8f, 0xd0, 0x52, 0xa0 } 437 - }, 438 - 439 - /* SM4_CS2 128*/ 440 - { .min_version = 0x65, 441 - .test[2].outlen = 16, .test[2].data = { 0xa0, 0x1c, 0xfe, 442 - 0x91, 0xaa, 0x7e, 0xf1, 0x75, 0x6a, 0xe8, 0xbc, 0xe1, 443 - 0x55, 0x08, 0xda, 0x71 } 444 - }, 445 - 446 - /* SM4_CS3 128*/ 447 - { .min_version = 0x65, 448 - .test[2].outlen = 16, .test[2].data = { 0xa0, 0x1c, 0xfe, 449 - 0x91, 0xaa, 0x7e, 0xf1, 0x75, 0x6a, 0xe8, 0xbc, 0xe1, 450 - 0x55, 0x08, 0xda, 0x71 } 451 - }, 452 - 453 - /* hashes ... note they use the 2nd keysize 454 - * array so the indecies mean different sizes!!! 455 - */ 456 - 457 - /* MD5 HASH/HMAC*/ 458 - { .min_version = 0x65, 459 - .test[1].outlen = 16, .test[1].data = { 0x70, 0xbc, 0x8f, 0x4b, 460 - 0x72, 0xa8, 0x69, 0x21, 0x46, 0x8b, 0xf8, 0xe8, 0x44, 461 - 0x1d, 0xce, 0x51, } 462 - }, 463 - { .min_version = 0x65, 464 - .test[1].outlen = 16, .test[1].data = { 0xb6, 0x39, 0xc8, 0x73, 465 - 0x16, 0x38, 0x61, 0x8b, 0x70, 0x79, 0x72, 0xaa, 0x6e, 466 - 0x96, 0xcf, 0x90, }, 467 - .test[4].outlen = 16, .test[4].data = { 0xb7, 0x79, 0x68, 0xea, 468 - 0x17, 0x32, 0x1e, 0x32, 0x13, 0x90, 0x6c, 0x2e, 0x9f, 469 - 0xd5, 0xc8, 0xb3, }, 470 - .test[5].outlen = 16, .test[5].data = { 0x80, 0x3e, 0x0a, 0x2f, 471 - 0x8a, 0xd8, 0x31, 0x8f, 0x8e, 0x12, 0x28, 0x86, 0x22, 472 - 0x59, 0x6b, 0x05, }, 473 - }, 474 - /* SHA1*/ 475 - { .min_version = 0x65, 476 - .test[1].outlen = 20, .test[1].data = { 0xde, 0x8a, 0x84, 0x7b, 477 - 0xff, 0x8c, 0x34, 0x3d, 0x69, 0xb8, 0x53, 0xa2, 0x15, 478 - 0xe6, 0xee, 0x77, 0x5e, 0xf2, 0xef, 0x96, } 479 - }, 480 - { .min_version = 0x65, 481 - .test[1].outlen = 20, .test[1].data = { 0xf8, 0x54, 0x60, 0x50, 482 - 0x49, 0x56, 0xd1, 0xcd, 0x55, 0x5c, 0x5d, 0xcd, 0x24, 483 - 0x33, 0xbf, 0xdc, 0x5c, 0x99, 0x54, 0xc8, }, 484 - .test[4].outlen = 20, .test[4].data = { 0x66, 0x3f, 0x3a, 0x3c, 485 - 0x08, 0xb6, 0x87, 0xb2, 0xd3, 0x0c, 0x5a, 0xa7, 0xcc, 486 - 0x5c, 0xc3, 0x99, 0xb2, 0xb4, 0x58, 0x55, }, 487 - .test[5].outlen = 20, .test[5].data = { 0x9a, 0x28, 0x54, 0x2f, 488 - 0xaf, 0xa7, 0x0b, 0x37, 0xbe, 0x2d, 0x3e, 0xd9, 0xd4, 489 - 0x70, 0xbc, 0xdc, 0x0b, 0x54, 0x20, 0x06, }, 490 - }, 491 - /* SHA224_HASH*/ 492 - { .min_version = 0x65, 493 - .test[1].outlen = 28, .test[1].data = { 0xb3, 0x38, 0xc7, 0x6b, 494 - 0xcf, 0xfa, 0x1a, 0x0b, 0x3e, 0xad, 0x8d, 0xe5, 0x8d, 495 - 0xfb, 0xff, 0x47, 0xb6, 0x3a, 0xb1, 0x15, 0x0e, 0x10, 496 - 0xd8, 0xf1, 0x7f, 0x2b, 0xaf, 0xdf, } 497 - }, 498 - { .min_version = 0x65, 499 - .test[1].outlen = 28, .test[1].data = { 0xf3, 0xb4, 0x33, 0x78, 500 - 0x53, 0x4c, 0x0c, 0x4a, 0x1e, 0x31, 0xc2, 0xce, 0xda, 501 - 0xc8, 0xfe, 0x74, 0x4a, 0xd2, 0x9b, 0x7c, 0x1d, 0x2f, 502 - 0x5e, 0xa1, 0xaa, 0x31, 0xb9, 0xf5, }, 503 - .test[4].outlen = 28, .test[4].data = { 0x4b, 0x6b, 0x3f, 0x9a, 504 - 0x66, 0x47, 0x45, 0xe2, 0x60, 0xc9, 0x53, 0x86, 0x7a, 505 - 0x34, 0x65, 0x7d, 0xe2, 0x24, 0x06, 0xcc, 0xf9, 0x17, 506 - 0x20, 0x5d, 0xc2, 0xb6, 0x97, 0x9a, }, 507 - .test[5].outlen = 28, .test[5].data = { 0x90, 0xb0, 0x6e, 0xee, 508 - 0x21, 0x57, 0x38, 0xc7, 0x65, 0xbb, 0x9a, 0xf5, 0xb4, 509 - 0x31, 0x0a, 0x0e, 0xe5, 0x64, 0xc4, 0x49, 0x9d, 0xbd, 510 - 0xe9, 0xf7, 0xac, 0x9f, 0xf8, 0x05, }, 511 - }, 512 - 513 - /* SHA256_HASH*/ 514 - { .min_version = 0x65, 515 - .test[1].outlen = 32, .test[1].data = { 0x66, 0x68, 0x7a, 0xad, 516 - 0xf8, 0x62, 0xbd, 0x77, 0x6c, 0x8f, 0xc1, 0x8b, 0x8e, 517 - 0x9f, 0x8e, 0x20, 0x08, 0x97, 0x14, 0x85, 0x6e, 0xe2, 518 - 0x33, 0xb3, 0x90, 0x2a, 0x59, 0x1d, 0x0d, 0x5f, 0x29, 519 - 0x25, } 520 - }, 521 - { .min_version = 0x65, 522 - .test[1].outlen = 32, .test[1].data = { 0x75, 0x40, 0x84, 0x49, 523 - 0x54, 0x0a, 0xf9, 0x80, 0x99, 0xeb, 0x93, 0x6b, 0xf6, 524 - 0xd3, 0xff, 0x41, 0x05, 0x47, 0xcc, 0x82, 0x62, 0x76, 525 - 0x32, 0xf3, 0x43, 0x74, 0x70, 0x54, 0xe2, 0x3b, 0xc0, 526 - 0x90, }, 527 - .test[4].outlen = 32, .test[4].data = { 0x41, 0x6c, 0x53, 0x92, 528 - 0xb9, 0xf3, 0x6d, 0xf1, 0x88, 0xe9, 0x0e, 0xb1, 0x4d, 529 - 0x17, 0xbf, 0x0d, 0xa1, 0x90, 0xbf, 0xdb, 0x7f, 0x1f, 530 - 0x49, 0x56, 0xe6, 0xe5, 0x66, 0xa5, 0x69, 0xc8, 0xb1, 531 - 0x5c, }, 532 - .test[5].outlen = 32, .test[5].data = { 0x49, 0x1f, 0x58, 0x3b, 533 - 0x05, 0xe2, 0x3a, 0x72, 0x1d, 0x11, 0x6d, 0xc1, 0x08, 534 - 0xa0, 0x3f, 0x30, 0x37, 0x98, 0x36, 0x8a, 0x49, 0x4c, 535 - 0x21, 0x1d, 0x56, 0xa5, 0x2a, 0xf3, 0x68, 0x28, 0xb7, 536 - 0x69, }, 537 - }, 538 - /* SHA384_HASH*/ 539 - { .min_version = 0x65, 540 - .test[1].outlen = 48, .test[1].data = { 0xa3, 0x8f, 0xff, 0x4b, 541 - 0xa2, 0x6c, 0x15, 0xe4, 0xac, 0x9c, 0xde, 0x8c, 0x03, 542 - 0x10, 0x3a, 0xc8, 0x90, 0x80, 0xfd, 0x47, 0x54, 0x5f, 543 - 0xde, 0x94, 0x46, 0xc8, 0xf1, 0x92, 0x72, 0x9e, 0xab, 544 - 0x7b, 0xd0, 0x3a, 0x4d, 0x5c, 0x31, 0x87, 0xf7, 0x5f, 545 - 0xe2, 0xa7, 0x1b, 0x0e, 0xe5, 0x0a, 0x4a, 0x40, } 546 - }, 547 - { .min_version = 0x65, 548 - .test[1].outlen = 48, .test[1].data = { 0x6c, 0xd8, 0x89, 0xa0, 549 - 0xca, 0x54, 0xa6, 0x1d, 0x24, 0xc4, 0x1d, 0xa1, 0x77, 550 - 0x50, 0xd6, 0xf2, 0xf3, 0x43, 0x23, 0x0d, 0xb1, 0xf5, 551 - 0xf7, 0xfc, 0xc0, 0x8c, 0xf6, 0xdf, 0x3c, 0x61, 0xfc, 552 - 0x8a, 0xb9, 0xda, 0x12, 0x75, 0x97, 0xac, 0x51, 0x88, 553 - 0x59, 0x19, 0x44, 0x13, 0xc0, 0x78, 0xa5, 0xa8, }, 554 - .test[4].outlen = 48, .test[4].data = { 0x0c, 0x91, 0x36, 0x46, 555 - 0xd9, 0x17, 0x81, 0x46, 0x1d, 0x42, 0xb1, 0x00, 0xaa, 556 - 0xfa, 0x26, 0x92, 0x9f, 0x05, 0xc0, 0x91, 0x8e, 0x20, 557 - 0xd7, 0x75, 0x9d, 0xd2, 0xc8, 0x9b, 0x02, 0x18, 0x20, 558 - 0x1f, 0xdd, 0xa3, 0x32, 0xe3, 0x1e, 0xa4, 0x2b, 0xc3, 559 - 0xc8, 0xb9, 0xb1, 0x53, 0x4e, 0x6a, 0x49, 0xd2, }, 560 - .test[5].outlen = 48, .test[5].data = { 0x84, 0x78, 0xd2, 0xf1, 561 - 0x44, 0x95, 0x6a, 0x22, 0x2d, 0x08, 0x19, 0xe8, 0xea, 562 - 0x61, 0xb4, 0x86, 0xe8, 0xc6, 0xb0, 0x40, 0x51, 0x28, 563 - 0x22, 0x54, 0x48, 0xc0, 0x70, 0x09, 0x81, 0xf9, 0xf5, 564 - 0x47, 0x9e, 0xb3, 0x2c, 0x69, 0x19, 0xd5, 0x8d, 0x03, 565 - 0x5d, 0x24, 0xca, 0x90, 0xa6, 0x9d, 0x80, 0x2a, }, 566 - .test[6].outlen = 48, .test[6].data = { 0x0e, 0x68, 0x17, 0x31, 567 - 0x01, 0xa8, 0x28, 0x0a, 0x4e, 0x47, 0x22, 0xa6, 0x89, 568 - 0xf0, 0xc6, 0xcd, 0x4e, 0x8c, 0x19, 0x4c, 0x44, 0x3d, 569 - 0xb5, 0xa5, 0xf9, 0xfe, 0xea, 0xc7, 0x84, 0x0b, 0x57, 570 - 0x0d, 0xd4, 0xe4, 0x8a, 0x3f, 0x68, 0x31, 0x20, 0xd9, 571 - 0x1f, 0xc4, 0xa3, 0x76, 0xcf, 0xdd, 0x07, 0xa6, }, 572 - }, 573 - /* SHA512_HASH */ 574 - { .min_version = 0x65, 575 - .test[1].outlen = 64, .test[1].data = { 0x50, 0x46, 0xad, 0xc1, 576 - 0xdb, 0xa8, 0x38, 0x86, 0x7b, 0x2b, 0xbb, 0xfd, 0xd0, 577 - 0xc3, 0x42, 0x3e, 0x58, 0xb5, 0x79, 0x70, 0xb5, 0x26, 578 - 0x7a, 0x90, 0xf5, 0x79, 0x60, 0x92, 0x4a, 0x87, 0xf1, 579 - 0x96, 0x0a, 0x6a, 0x85, 0xea, 0xa6, 0x42, 0xda, 0xc8, 580 - 0x35, 0x42, 0x4b, 0x5d, 0x7c, 0x8d, 0x63, 0x7c, 0x00, 581 - 0x40, 0x8c, 0x7a, 0x73, 0xda, 0x67, 0x2b, 0x7f, 0x49, 582 - 0x85, 0x21, 0x42, 0x0b, 0x6d, 0xd3, } 583 - }, 584 - { .min_version = 0x65, 585 - .test[1].outlen = 64, .test[1].data = { 0xec, 0xfd, 0x83, 0x74, 586 - 0xc8, 0xa9, 0x2f, 0xd7, 0x71, 0x94, 0xd1, 0x1e, 0xe7, 587 - 0x0f, 0x0f, 0x5e, 0x11, 0x29, 0x58, 0xb8, 0x36, 0xc6, 588 - 0x39, 0xbc, 0xd6, 0x88, 0x6e, 0xdb, 0xc8, 0x06, 0x09, 589 - 0x30, 0x27, 0xaa, 0x69, 0xb9, 0x2a, 0xd4, 0x67, 0x06, 590 - 0x5c, 0x82, 0x8e, 0x90, 0xe9, 0x3e, 0x55, 0x88, 0x7d, 591 - 0xb2, 0x2b, 0x48, 0xa2, 0x28, 0x92, 0x6c, 0x0f, 0xf1, 592 - 0x57, 0xb5, 0xd0, 0x06, 0x1d, 0xf3, }, 593 - .test[4].outlen = 64, .test[4].data = { 0x47, 0x88, 0x91, 0xe9, 594 - 0x12, 0x3e, 0xfd, 0xdc, 0x26, 0x29, 0x08, 0xd6, 0x30, 595 - 0x8f, 0xcc, 0xb6, 0x93, 0x30, 0x58, 0x69, 0x4e, 0x81, 596 - 0xee, 0x9d, 0xb6, 0x0f, 0xc5, 0x54, 0xe6, 0x7c, 0x84, 597 - 0xc5, 0xbc, 0x89, 0x99, 0xf0, 0xf3, 0x7f, 0x6f, 0x3f, 598 - 0xf5, 0x04, 0x2c, 0xdf, 0x76, 0x72, 0x6a, 0xbe, 0x28, 599 - 0x3b, 0xb8, 0x05, 0xb3, 0x47, 0x45, 0xf5, 0x7f, 0xb1, 600 - 0x21, 0x2d, 0xe0, 0x8d, 0x1e, 0x29, }, 601 - .test[5].outlen = 64, .test[5].data = { 0x7e, 0x55, 0xda, 0x88, 602 - 0x28, 0xc1, 0x6e, 0x9a, 0x6a, 0x99, 0xa0, 0x37, 0x68, 603 - 0xf0, 0x28, 0x5e, 0xe2, 0xbe, 0x00, 0xac, 0x76, 0x89, 604 - 0x76, 0xcc, 0x5d, 0x98, 0x1b, 0x32, 0x1a, 0x14, 0xc4, 605 - 0x2e, 0x9c, 0xe4, 0xf3, 0x3f, 0x5f, 0xa0, 0xae, 0x95, 606 - 0x16, 0x0b, 0x14, 0xf5, 0xf5, 0x45, 0x29, 0xd8, 0xc9, 607 - 0x43, 0xf2, 0xa9, 0xbc, 0xdc, 0x03, 0x81, 0x0d, 0x36, 608 - 0x2f, 0xb1, 0x22, 0xe8, 0x13, 0xf8, }, 609 - .test[6].outlen = 64, .test[6].data = { 0x5d, 0xc4, 0x80, 0x90, 610 - 0x6b, 0x00, 0x17, 0x04, 0x34, 0x63, 0x93, 0xf1, 0xad, 611 - 0x9a, 0x3e, 0x13, 0x37, 0x6b, 0x86, 0xd7, 0xc4, 0x2b, 612 - 0x22, 0x9c, 0x2e, 0xf2, 0x1d, 0xde, 0x35, 0x39, 0x03, 613 - 0x3f, 0x2b, 0x3a, 0xc3, 0x49, 0xb3, 0x32, 0x86, 0x63, 614 - 0x6b, 0x0f, 0x27, 0x95, 0x97, 0xe5, 0xe7, 0x2b, 0x9b, 615 - 0x80, 0xea, 0x94, 0x4d, 0x84, 0x2e, 0x39, 0x44, 0x8f, 616 - 0x56, 0xe3, 0xcd, 0xa7, 0x12, 0x3e, }, 617 - }, 618 - /* SHA512_224_HASH */ 619 - { .min_version = 0x65, 620 - .test[1].outlen = 28, .test[1].data = { 0x9e, 0x7d, 0x60, 0x80, 621 - 0xde, 0xf4, 0xe1, 0xcc, 0xf4, 0xae, 0xaa, 0xc6, 0xf7, 622 - 0xfa, 0xd0, 0x08, 0xd0, 0x60, 0xa6, 0xcf, 0x87, 0x06, 623 - 0x20, 0x38, 0xd6, 0x16, 0x67, 0x74, } 624 - }, 625 - { .min_version = 0x65, 626 - .test[1].outlen = 28, .test[1].data = { 0xff, 0xfb, 0x43, 0x27, 627 - 0xdd, 0x2e, 0x39, 0xa0, 0x18, 0xa8, 0xaf, 0xde, 0x84, 628 - 0x0b, 0x5d, 0x0f, 0x3d, 0xdc, 0xc6, 0x17, 0xd1, 0xb6, 629 - 0x2f, 0x8c, 0xf8, 0x7e, 0x34, 0x34, }, 630 - .test[4].outlen = 28, .test[4].data = { 0x00, 0x19, 0xe2, 0x2d, 631 - 0x44, 0x80, 0x2d, 0xd8, 0x1c, 0x57, 0xf5, 0x57, 0x92, 632 - 0x08, 0x13, 0xe7, 0x9d, 0xbb, 0x2b, 0xc2, 0x8d, 0x77, 633 - 0xc1, 0xff, 0x71, 0x4c, 0xf0, 0xa9, }, 634 - .test[5].outlen = 28, .test[5].data = { 0x6a, 0xc4, 0xa8, 0x73, 635 - 0x21, 0x54, 0xb2, 0x82, 0xee, 0x89, 0x8d, 0x45, 0xd4, 636 - 0xe3, 0x76, 0x3e, 0x04, 0x03, 0xc9, 0x71, 0xee, 0x01, 637 - 0x25, 0xd2, 0x7b, 0xa1, 0x20, 0xc4, }, 638 - .test[6].outlen = 28, .test[6].data = { 0x0f, 0x98, 0x15, 0x9b, 639 - 0x11, 0xca, 0x60, 0xc7, 0x82, 0x39, 0x1a, 0x50, 0x8c, 640 - 0xe4, 0x79, 0xfa, 0xa8, 0x0e, 0xc7, 0x12, 0xfd, 0x8c, 641 - 0x9c, 0x99, 0x7a, 0xe8, 0x7e, 0x92, }, 642 - }, 643 - /* SHA512_256_HASH*/ 644 - { .min_version = 0x65, 645 - .test[1].outlen = 32, .test[1].data = { 0xaf, 0x13, 0xc0, 0x48, 646 - 0x99, 0x12, 0x24, 0xa5, 0xe4, 0xc6, 0x64, 0x44, 0x6b, 647 - 0x68, 0x8a, 0xaf, 0x48, 0xfb, 0x54, 0x56, 0xdb, 0x36, 648 - 0x29, 0x60, 0x1b, 0x00, 0xec, 0x16, 0x0c, 0x74, 0xe5, 649 - 0x54, } 650 - }, 651 - { .min_version = 0x65, 652 - .test[1].outlen = 32, .test[1].data = { 0x3a, 0x2c, 0xd0, 0x2b, 653 - 0xfa, 0xa6, 0x72, 0xe4, 0xf1, 0xab, 0x0a, 0x3e, 0x70, 654 - 0xe4, 0x88, 0x1a, 0x92, 0xe1, 0x3b, 0x64, 0x5a, 0x9b, 655 - 0xed, 0xb3, 0x97, 0xc0, 0x17, 0x1f, 0xd4, 0x05, 0xf1, 656 - 0x72, }, 657 - .test[4].outlen = 32, .test[4].data = { 0x6f, 0x2d, 0xae, 0xc6, 658 - 0xe4, 0xa6, 0x5b, 0x52, 0x0f, 0x26, 0x16, 0xf6, 0xa9, 659 - 0xc1, 0x23, 0xc2, 0xb3, 0x67, 0xfc, 0x69, 0xac, 0x73, 660 - 0x87, 0xa2, 0x5b, 0x6c, 0x44, 0xad, 0xc5, 0x26, 0x2b, 661 - 0x10, }, 662 - .test[5].outlen = 32, .test[5].data = { 0x63, 0xe7, 0xb8, 0xd1, 663 - 0x76, 0x33, 0x56, 0x29, 0xba, 0x99, 0x86, 0x42, 0x0d, 664 - 0x4f, 0xf7, 0x54, 0x8c, 0xb9, 0x39, 0xf2, 0x72, 0x1d, 665 - 0x0e, 0x9d, 0x80, 0x67, 0xd9, 0xab, 0x15, 0xb0, 0x68, 666 - 0x18, }, 667 - .test[6].outlen = 32, .test[6].data = { 0x64, 0x78, 0x56, 0xd7, 668 - 0xaf, 0x5b, 0x56, 0x08, 0xf1, 0x44, 0xf7, 0x4f, 0xa1, 669 - 0xa1, 0x13, 0x79, 0x6c, 0xb1, 0x31, 0x11, 0xf3, 0x75, 670 - 0xf4, 0x8c, 0xb4, 0x9f, 0xbf, 0xb1, 0x60, 0x38, 0x3d, 671 - 0x28, }, 672 - }, 673 - 674 - /* AESXCBC*/ 675 - { .min_version = 0x65, 676 - .test[1].outlen = 16, .test[1].data = { 0x35, 0xd9, 0xdc, 0xdb, 677 - 0x82, 0x9f, 0xec, 0x33, 0x52, 0xe7, 0xbf, 0x10, 0xb8, 678 - 0x4b, 0xe4, 0xa5, }, 679 - .test[3].outlen = 16, .test[3].data = { 0x39, 0x6f, 0x99, 0xb5, 680 - 0x43, 0x33, 0x67, 0x4e, 0xd4, 0x45, 0x8f, 0x80, 0x77, 681 - 0xe4, 0xd4, 0x14, }, 682 - .test[4].outlen = 16, .test[4].data = { 0x73, 0xd4, 0x7c, 0x38, 683 - 0x37, 0x4f, 0x73, 0xd0, 0x78, 0xa8, 0xc6, 0xec, 0x05, 684 - 0x67, 0xca, 0x5e, }, 685 - }, 686 - 687 - /* AESCMAC*/ 688 - { .min_version = 0x65, 689 - .test[1].outlen = 16, .test[1].data = { 0x15, 0xbe, 0x1b, 0xfd, 690 - 0x8c, 0xbb, 0xaf, 0x8b, 0x51, 0x9a, 0x64, 0x3b, 0x1b, 691 - 0x46, 0xc1, 0x8f, }, 692 - .test[3].outlen = 16, .test[3].data = { 0x4e, 0x02, 0xd6, 0xec, 693 - 0x92, 0x75, 0x88, 0xb4, 0x3e, 0x83, 0xa7, 0xac, 0x32, 694 - 0xb6, 0x2b, 0xdb, }, 695 - .test[4].outlen = 16, .test[4].data = { 0xa7, 0x37, 0x01, 0xbe, 696 - 0xe8, 0xce, 0xed, 0x44, 0x49, 0x4a, 0xbb, 0xf6, 0x9e, 697 - 0xd9, 0x31, 0x3e, }, 698 - }, 699 - 700 - /* KASUMIF9*/ 701 - { .min_version = 0x65, 702 - .test[1].outlen = 4, .test[1].data = { 0x5b, 0x26, 0x81, 0x06 703 - } 704 - }, 705 - 706 - /* SNOW3G UIA2*/ 707 - { .min_version = 0x65, 708 - .test[1].outlen = 4, .test[1].data = { 0x08, 0xed, 0x2c, 0x76, 709 - } 710 - }, 711 - 712 - /* ZUC UIA3*/ 713 - { .min_version = 0x65, 714 - .test[1].outlen = 4, .test[1].data = { 0x6a, 0x2b, 0x4c, 0x3a, 715 - } 716 - }, 717 - 718 - /* POLY1305*/ 719 - { .min_version = 0x65, 720 - .test[4].outlen = 16, .test[4].data = { 0xef, 0x91, 0x06, 0x4e, 721 - 0xce, 0x99, 0x9c, 0x4e, 0xfd, 0x05, 0x6a, 0x8c, 0xe6, 722 - 0x18, 0x23, 0xad } 723 - }, 724 - 725 - /* SSLMAC MD5*/ 726 - { .min_version = 0x65, 727 - .test[1].outlen = 16, .test[1].data = { 0x0e, 0xf4, 0xca, 0x32, 728 - 0x32, 0x40, 0x1d, 0x1b, 0xaa, 0xfd, 0x6d, 0xa8, 0x01, 729 - 0x79, 0xed, 0xcd, }, 730 - }, 731 - 732 - /* SSLMAC_SHA1*/ 733 - { .min_version = 0x65, 734 - .test[2].outlen = 20, .test[2].data = { 0x05, 0x9d, 0x99, 0xb4, 735 - 0xf3, 0x03, 0x1e, 0xc5, 0x24, 0xbf, 0xec, 0xdf, 0x64, 736 - 0x8e, 0x37, 0x2e, 0xf0, 0xef, 0x93, 0xa0, }, 737 - }, 738 - 739 - /* CRC32*/ 740 - { .min_version = 0x65, 741 - .test[0].outlen = 0 742 - }, 743 - 744 - /* TKIP-MIC*/ 745 - { .min_version = 0x65, 746 - .test[0].outlen = 8, .test[0].data = { 0x16, 0xfb, 0xa0, 747 - 0x0e, 0xe2, 0xab, 0x6c, 0x97, } 748 - }, 749 - 750 - /* SHA3-224*/ 751 - { .min_version = 0x65, 752 - .test[1].outlen = 28, .test[1].data = { 0x73, 0xe0, 0x87, 753 - 0xae, 0x12, 0x71, 0xb2, 0xc5, 0xf6, 0x85, 0x46, 0xc9, 754 - 0x3a, 0xb4, 0x25, 0x14, 0xa6, 0x9e, 0xef, 0x25, 0x2b, 755 - 0xfd, 0xd1, 0x37, 0x55, 0x74, 0x8a, 0x00, } 756 - }, 757 - 758 - /* SHA3-256*/ 759 - { .min_version = 0x65, 760 - .test[1].outlen = 32, .test[1].data = { 0x9e, 0x62, 0x91, 0x97, 761 - 0x0c, 0xb4, 0x4d, 0xd9, 0x40, 0x08, 0xc7, 0x9b, 0xca, 762 - 0xf9, 0xd8, 0x6f, 0x18, 0xb4, 0xb4, 0x9b, 0xa5, 0xb2, 763 - 0xa0, 0x47, 0x81, 0xdb, 0x71, 0x99, 0xed, 0x3b, 0x9e, 764 - 0x4e, } 765 - }, 766 - 767 - /* SHA3-384*/ 768 - { .min_version = 0x65, 769 - .test[1].outlen = 48, .test[1].data = { 0x4b, 0xda, 0xab, 770 - 0xf7, 0x88, 0xd3, 0xad, 0x1a, 0xd8, 0x3d, 0x6d, 0x93, 771 - 0xc7, 0xe4, 0x49, 0x37, 0xc2, 0xe6, 0x49, 0x6a, 0xf2, 772 - 0x3b, 0xe3, 0x35, 0x4d, 0x75, 0x69, 0x87, 0xf4, 0x51, 773 - 0x60, 0xfc, 0x40, 0x23, 0xbd, 0xa9, 0x5e, 0xcd, 0xcb, 774 - 0x3c, 0x7e, 0x31, 0xa6, 0x2f, 0x72, 0x6d, 0x70, 0x2c, 775 - } 776 - }, 777 - 778 - /* SHA3-512*/ 779 - { .min_version = 0x65, 780 - .test[1].outlen = 64, .test[1].data = { 0xad, 0x56, 0xc3, 0x5c, 781 - 0xab, 0x50, 0x63, 0xb9, 0xe7, 0xea, 0x56, 0x83, 0x14, 782 - 0xec, 0x81, 0xc4, 0x0b, 0xa5, 0x77, 0xaa, 0xe6, 0x30, 783 - 0xde, 0x90, 0x20, 0x04, 0x00, 0x9e, 0x88, 0xf1, 0x8d, 784 - 0xa5, 0x7b, 0xbd, 0xfd, 0xaa, 0xa0, 0xfc, 0x18, 0x9c, 785 - 0x66, 0xc8, 0xd8, 0x53, 0x24, 0x8b, 0x6b, 0x11, 0x88, 786 - 0x44, 0xd5, 0x3f, 0x7d, 0x0b, 0xa1, 0x1d, 0xe0, 0xf3, 787 - 0xbf, 0xaf, 0x4c, 0xdd, 0x9b, 0x3f, } 788 - }, 789 - 790 - /* SHAKE128*/ 791 - { .min_version = 0x65, 792 - .test[4].outlen = 16, .test[4].data = { 0x24, 0xa7, 0xca, 793 - 0x4b, 0x75, 0xe3, 0x89, 0x8d, 0x4f, 0x12, 0xe7, 0x4d, 794 - 0xea, 0x8c, 0xbb, 0x65 } 795 - }, 796 - 797 - /* SHAKE256*/ 798 - { .min_version = 0x65, 799 - .test[4].outlen = 32, .test[4].data = { 0xf5, 0x97, 0x7c, 800 - 0x82, 0x83, 0x54, 0x6a, 0x63, 0x72, 0x3b, 0xc3, 0x1d, 801 - 0x26, 0x19, 0x12, 0x4f, 802 - 0x11, 0xdb, 0x46, 0x58, 0x64, 0x33, 0x36, 0x74, 0x1d, 803 - 0xf8, 0x17, 0x57, 0xd5, 0xad, 0x30, 0x62 } 804 - }, 805 - 806 - /* CSHAKE128*/ 807 - { .min_version = 0x65, 808 - .test[1].outlen = 16, .test[1].data = { 0xe0, 0x6f, 0xd8, 809 - 0x50, 0x57, 0x6f, 0xe4, 0xfa, 0x7e, 0x13, 0x42, 0xb5, 810 - 0xf8, 0x13, 0xeb, 0x23 } 811 - }, 812 - 813 - /* CSHAKE256*/ 814 - { .min_version = 0x65, 815 - .test[1].outlen = 32, .test[1].data = { 0xf3, 0xf2, 0xb5, 816 - 0x47, 0xf2, 0x16, 0xba, 0x6f, 0x49, 0x83, 0x3e, 0xad, 817 - 0x1e, 0x46, 0x85, 0x54, 818 - 0xd0, 0xd7, 0xf9, 0xc6, 0x7e, 0xe9, 0x27, 0xc6, 0xc3, 819 - 0xc3, 0xdb, 0x91, 0xdb, 0x97, 0x04, 0x0f } 820 - }, 821 - 822 - /* KMAC128*/ 823 - { .min_version = 0x65, 824 - .test[1].outlen = 16, .test[1].data = { 0x6c, 0x3f, 0x29, 825 - 0xfe, 0x01, 0x96, 0x59, 0x36, 0xb7, 0xae, 0xb7, 0xff, 826 - 0x71, 0xe0, 0x3d, 0xff }, 827 - .test[4].outlen = 16, .test[4].data = { 0x58, 0xd9, 0x8d, 828 - 0xe8, 0x1f, 0x64, 0xb4, 0xa3, 0x9f, 0x63, 0xaf, 0x21, 829 - 0x99, 0x03, 0x97, 0x06 }, 830 - .test[5].outlen = 16, .test[5].data = { 0xf8, 0xf9, 0xb7, 831 - 0xa4, 0x05, 0x3d, 0x90, 0x7c, 0xf2, 0xa1, 0x7c, 0x34, 832 - 0x39, 0xc2, 0x87, 0x4b }, 833 - .test[6].outlen = 16, .test[6].data = { 0xef, 0x4a, 0xd5, 834 - 0x1d, 0xd7, 0x83, 0x56, 0xd3, 0xa8, 0x3c, 0xf5, 0xf8, 835 - 0xd1, 0x12, 0xf4, 0x44 } 836 - }, 837 - 838 - /* KMAC256*/ 839 - { .min_version = 0x65, 840 - .test[1].outlen = 32, .test[1].data = { 0x0d, 0x86, 0xfa, 841 - 0x92, 0x92, 0xe4, 0x77, 0x24, 0x6a, 0xcc, 0x79, 0xa0, 842 - 0x1e, 0xb4, 0xc3, 0xac, 843 - 0xfc, 0x56, 0xbc, 0x63, 0xcc, 0x1b, 0x6e, 0xf6, 0xc8, 844 - 0x99, 0xa5, 0x3a, 0x38, 0x14, 0xa2, 0x40 }, 845 - .test[4].outlen = 32, .test[4].data = { 0xad, 0x99, 0xed, 846 - 0x20, 0x1f, 0xbe, 0x45, 0x07, 0x3d, 0xf4, 0xae, 0x9f, 847 - 0xc2, 0xd8, 0x06, 0x18, 848 - 0x31, 0x4e, 0x8c, 0xb6, 0x33, 0xe8, 0x31, 0x36, 0x00, 849 - 0xdd, 0x42, 0x20, 0xda, 0x2b, 0xd5, 0x2b }, 850 - .test[5].outlen = 32, .test[5].data = { 0xf9, 0xc6, 0x2b, 851 - 0x17, 0xa0, 0x04, 0xd9, 0xf2, 0x6c, 0xbf, 0x5d, 0xa5, 852 - 0x9a, 0xd7, 0x36, 0x1d, 853 - 0xad, 0x66, 0x6b, 0x3d, 0xb1, 0x52, 0xd3, 0x81, 0x39, 854 - 0x20, 0xd4, 0xf0, 0x43, 0x72, 0x2c, 0xb7 }, 855 - .test[6].outlen = 32, .test[6].data = { 0xcc, 0x89, 0xe4, 856 - 0x05, 0x58, 0x77, 0x38, 0x8b, 0x18, 0xa0, 0x7c, 0x8d, 857 - 0x20, 0x99, 0xea, 0x6e, 858 - 0x6b, 0xe9, 0xf7, 0x0c, 0xe1, 0xe5, 0xce, 0xbc, 0x55, 859 - 0x4c, 0x80, 0xa5, 0xdc, 0xae, 0xf7, 0x94 } 860 - }, 861 - 862 - /* KMAC128XOF*/ 863 - { .min_version = 0x65, 864 - .test[1].outlen = 16, .test[1].data = { 0x84, 0x07, 0x89, 865 - 0x29, 0xa7, 0xf4, 0x98, 0x91, 0xf5, 0x64, 0x61, 0x8d, 866 - 0xa5, 0x93, 0x00, 0x31 }, 867 - .test[4].outlen = 16, .test[4].data = { 0xf0, 0xa4, 0x1b, 868 - 0x98, 0x0f, 0xb3, 0xf2, 0xbd, 0xc3, 0xfc, 0x64, 0x1f, 869 - 0x73, 0x1f, 0xd4, 0x74 }, 870 - .test[5].outlen = 16, .test[5].data = { 0xa5, 0xc5, 0xad, 871 - 0x25, 0x59, 0xf1, 0x5d, 0xea, 0x5b, 0x18, 0x0a, 0x52, 872 - 0xce, 0x6c, 0xc0, 0x88 }, 873 - .test[6].outlen = 16, .test[6].data = { 0x1a, 0x81, 0xdd, 874 - 0x81, 0x47, 0x89, 0xf4, 0x15, 0xcc, 0x18, 0x05, 0x81, 875 - 0xe3, 0x95, 0x21, 0xc3 } 876 - }, 877 - 878 - /* KMAC256XOF*/ 879 - { .min_version = 0x65, 880 - .test[1].outlen = 32, .test[1].data = { 0xff, 0x85, 0xe9, 881 - 0x61, 0x67, 0x96, 0x35, 0x58, 0x33, 0x38, 0x2c, 0xe8, 882 - 0x25, 0x77, 0xbe, 0x63, 883 - 0xd5, 0x2c, 0xa7, 0xef, 0xce, 0x9b, 0x63, 0x71, 0xb2, 884 - 0x09, 0x7c, 0xd8, 0x60, 0x4e, 0x5a, 0xfa }, 885 - .test[4].outlen = 32, .test[4].data = { 0x86, 0x89, 0xc2, 886 - 0x4a, 0xe8, 0x18, 0x46, 0x10, 0x6b, 0xf2, 0x09, 0xd7, 887 - 0x37, 0x83, 0xab, 0x77, 888 - 0xb5, 0xce, 0x7c, 0x96, 0x9c, 0xfa, 0x0f, 0xa0, 0xd8, 889 - 0xde, 0xb5, 0xb7, 0xc6, 0xcd, 0xa9, 0x8f }, 890 - .test[5].outlen = 32, .test[5].data = { 0x4d, 0x71, 0x81, 891 - 0x5a, 0x5f, 0xac, 0x3b, 0x29, 0xf2, 0x5f, 0xb6, 0x56, 892 - 0xf1, 0x76, 0xcf, 0xdc, 893 - 0x51, 0x56, 0xd7, 0x3c, 0x47, 0xec, 0x6d, 0xea, 0xc6, 894 - 0x3e, 0x54, 0xe7, 0x6f, 0xdc, 0xe8, 0x39 }, 895 - .test[6].outlen = 32, .test[6].data = { 0x5f, 0xc5, 0xe1, 896 - 0x1e, 0xe7, 0x55, 0x0f, 0x62, 0x71, 0x29, 0xf3, 0x0a, 897 - 0xb3, 0x30, 0x68, 0x06, 898 - 0xea, 0xec, 0xe4, 0x37, 0x17, 0x37, 0x2d, 0x5d, 0x64, 899 - 0x09, 0x70, 0x63, 0x94, 0x80, 0x9b, 0x80 } 900 - }, 901 - 902 - /* HASH SM3*/ 903 - { .min_version = 0x65, 904 - .test[1].outlen = 32, .test[1].data = { 0xe0, 0xba, 0xb8, 905 - 0xf4, 0xd8, 0x17, 0x2b, 0xa2, 0x45, 0x19, 0x0d, 0x13, 906 - 0xc9, 0x41, 0x17, 0xe9, 907 - 0x3b, 0x82, 0x16, 0x6c, 0x25, 0xb2, 0xb6, 0x98, 0x83, 908 - 0x35, 0x0c, 0x19, 0x2c, 0x90, 0x51, 0x40 }, 909 - .test[4].outlen = 32, .test[4].data = { 0xe0, 0xba, 0xb8, 910 - 0xf4, 0xd8, 0x17, 0x2b, 0xa2, 0x45, 0x19, 0x0d, 0x13, 911 - 0xc9, 0x41, 0x17, 0xe9, 912 - 0x3b, 0x82, 0x16, 0x6c, 0x25, 0xb2, 0xb6, 0x98, 0x83, 913 - 0x35, 0x0c, 0x19, 0x2c, 0x90, 0x51, 0x40 }, 914 - .test[5].outlen = 32, .test[5].data = { 0xe0, 0xba, 0xb8, 915 - 0xf4, 0xd8, 0x17, 0x2b, 0xa2, 0x45, 0x19, 0x0d, 0x13, 916 - 0xc9, 0x41, 0x17, 0xe9, 917 - 0x3b, 0x82, 0x16, 0x6c, 0x25, 0xb2, 0xb6, 0x98, 0x83, 918 - 0x35, 0x0c, 0x19, 0x2c, 0x90, 0x51, 0x40 }, 919 - .test[6].outlen = 32, .test[6].data = { 0xe0, 0xba, 0xb8, 920 - 0xf4, 0xd8, 0x17, 0x2b, 0xa2, 0x45, 0x19, 0x0d, 0x13, 921 - 0xc9, 0x41, 0x17, 0xe9, 922 - 0x3b, 0x82, 0x16, 0x6c, 0x25, 0xb2, 0xb6, 0x98, 0x83, 923 - 0x35, 0x0c, 0x19, 0x2c, 0x90, 0x51, 0x40 } 924 - }, 925 - 926 - /* HMAC SM3*/ 927 - { .min_version = 0x65, 928 - .test[1].outlen = 32, .test[1].data = { 0x68, 0xf0, 0x65, 929 - 0xd8, 0xd8, 0xc9, 0xc2, 0x0e, 0x10, 0xfd, 0x52, 0x7c, 930 - 0xf2, 0xd7, 0x42, 0xd3, 931 - 0x08, 0x44, 0x22, 0xbc, 0xf0, 0x9d, 0xcc, 0x34, 0x7b, 932 - 0x76, 0x13, 0x91, 0xba, 0xce, 0x4d, 0x17 }, 933 - .test[4].outlen = 32, .test[4].data = { 0xd8, 0xab, 0x2a, 934 - 0x7b, 0x56, 0x21, 0xb1, 0x59, 0x64, 0xb2, 0xa3, 0xd6, 935 - 0x72, 0xb3, 0x95, 0x81, 936 - 0xa0, 0xcd, 0x96, 0x47, 0xf0, 0xbc, 0x8c, 0x16, 0x5b, 937 - 0x9b, 0x7d, 0x2f, 0x71, 0x3f, 0x23, 0x19}, 938 - .test[5].outlen = 32, .test[5].data = { 0xa0, 0xd1, 0xd5, 939 - 0xa0, 0x9e, 0x4c, 0xca, 0x8c, 0x7b, 0xe0, 0x8f, 0x70, 940 - 0x92, 0x2e, 0x3f, 0x4c, 941 - 0xa0, 0xca, 0xef, 0xa1, 0x86, 0x9d, 0xb2, 0xe1, 0xc5, 942 - 0xfa, 0x9d, 0xfa, 0xbc, 0x11, 0xcb, 0x1f }, 943 - .test[6].outlen = 32, .test[6].data = { 0xa0, 0xd1, 0xd5, 944 - 0xa0, 0x9e, 0x4c, 0xca, 0x8c, 0x7b, 0xe0, 0x8f, 0x70, 945 - 0x92, 0x2e, 0x3f, 0x4c, 946 - 0xa0, 0xca, 0xef, 0xa1, 0x86, 0x9d, 0xb2, 0xe1, 0xc5, 947 - 0xfa, 0x9d, 0xfa, 0xbc, 0x11, 0xcb, 0x1f} 948 - }, 949 - 950 - /* MAC_SM4_XCBC*/ 951 - { .min_version = 0x65, 952 - .test[1].outlen = 16, .test[1].data = { 0x69, 0xaf, 0x45, 953 - 0xe6, 0x0c, 0x78, 0x71, 0x7e, 0x44, 0x6c, 0xfe, 0x68, 954 - 0xd4, 0xfe, 0x20, 0x8b }, 955 - .test[4].outlen = 16, .test[4].data = { 0x69, 0xaf, 0x45, 956 - 0xe6, 0x0c, 0x78, 0x71, 0x7e, 0x44, 0x6c, 0xfe, 0x68, 957 - 0xd4, 0xfe, 0x20, 0x8b }, 958 - .test[5].outlen = 16, .test[5].data = { 0x69, 0xaf, 0x45, 959 - 0xe6, 0x0c, 0x78, 0x71, 0x7e, 0x44, 0x6c, 0xfe, 0x68, 960 - 0xd4, 0xfe, 0x20, 0x8b }, 961 - .test[6].outlen = 16, .test[6].data = { 0x69, 0xaf, 0x45, 962 - 0xe6, 0x0c, 0x78, 0x71, 0x7e, 0x44, 0x6c, 0xfe, 0x68, 963 - 0xd4, 0xfe, 0x20, 0x8b } 964 - }, 965 - 966 - /* MAC_SM4_CMAC*/ 967 - { .min_version = 0x65, 968 - .test[1].outlen = 16, .test[1].data = { 0x36, 0xbe, 0xec, 969 - 0x03, 0x9c, 0xc7, 0x0c, 0x28, 0x23, 0xdd, 0x71, 0x8b, 970 - 0x3c, 0xbd, 0x7f, 0x37 }, 971 - .test[4].outlen = 16, .test[4].data = { 0x36, 0xbe, 0xec, 972 - 0x03, 0x9c, 0xc7, 0x0c, 0x28, 0x23, 0xdd, 0x71, 0x8b, 973 - 0x3c, 0xbd, 0x7f, 0x37 }, 974 - .test[5].outlen = 16, .test[5].data = { 0x36, 0xbe, 0xec, 975 - 0x03, 0x9c, 0xc7, 0x0c, 0x28, 0x23, 0xdd, 0x71, 0x8b, 976 - 0x3c, 0xbd, 0x7f, 0x37 }, 977 - .test[6].outlen = 16, .test[6].data = { 0x36, 0xbe, 0xec, 978 - 0x03, 0x9c, 0xc7, 0x0c, 0x28, 0x23, 0xdd, 0x71, 0x8b, 979 - 0x3c, 0xbd, 0x7f, 0x37 } 980 - }, 981 - 982 - }; 983 - #endif 984 - 985 - int spacc_sg_to_ddt(struct device *dev, struct scatterlist *sg, 986 - int nbytes, struct pdu_ddt *ddt, int dma_direction) 987 - { 988 - struct scatterlist *sg_entry, *sgl; 989 - int nents, orig_nents; 990 - int i, rc; 991 - 992 - orig_nents = sg_nents(sg); 993 - if (orig_nents > 1) { 994 - sgl = sg_last(sg, orig_nents); 995 - if (sgl->length == 0) 996 - orig_nents--; 997 - } 998 - nents = dma_map_sg(dev, sg, orig_nents, dma_direction); 999 - 1000 - if (nents <= 0) 1001 - return -ENOMEM; 1002 - 1003 - /* require ATOMIC operations */ 1004 - rc = pdu_ddt_init(ddt, nents | 0x80000000); 1005 - if (rc < 0) { 1006 - dma_unmap_sg(dev, sg, nents, dma_direction); 1007 - return -EIO; 1008 - } 1009 - 1010 - for_each_sg(sg, sg_entry, nents, i) { 1011 - pdu_ddt_add(ddt, sg_dma_address(sg_entry), 1012 - sg_dma_len(sg_entry)); 1013 - } 1014 - 1015 - dma_sync_sg_for_device(dev, sg, nents, dma_direction); 1016 - 1017 - return nents; 1018 - } 1019 - 1020 - int spacc_set_operation(struct spacc_device *spacc, int handle, int op, 1021 - u32 prot, uint32_t icvcmd, uint32_t icvoff, 1022 - uint32_t icvsz, uint32_t sec_key) 1023 - { 1024 - int ret = CRYPTO_OK; 1025 - struct spacc_job *job = NULL; 1026 - 1027 - if (handle < 0 || handle >= SPACC_MAX_JOBS) 1028 - return -ENXIO; 1029 - 1030 - job = &spacc->job[handle]; 1031 - if (!job) 1032 - return -EIO; 1033 - 1034 - job->op = op; 1035 - if (op == OP_ENCRYPT) 1036 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_ENCRYPT); 1037 - else 1038 - job->ctrl &= ~SPACC_CTRL_MASK(SPACC_CTRL_ENCRYPT); 1039 - 1040 - switch (prot) { 1041 - case ICV_HASH: /* HASH of plaintext */ 1042 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_ICV_PT); 1043 - break; 1044 - case ICV_HASH_ENCRYPT: 1045 - /* HASH the plaintext and encrypt the lot */ 1046 - /* ICV_PT and ICV_APPEND must be set too */ 1047 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_ICV_ENC); 1048 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_ICV_PT); 1049 - /* This mode is not valid when BIT_ALIGN != 0 */ 1050 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_ICV_APPEND); 1051 - break; 1052 - case ICV_ENCRYPT_HASH: /* HASH the ciphertext */ 1053 - job->ctrl &= ~SPACC_CTRL_MASK(SPACC_CTRL_ICV_PT); 1054 - job->ctrl &= ~SPACC_CTRL_MASK(SPACC_CTRL_ICV_ENC); 1055 - break; 1056 - case ICV_IGNORE: 1057 - break; 1058 - default: 1059 - ret = -EINVAL; 1060 - } 1061 - 1062 - job->icv_len = icvsz; 1063 - 1064 - switch (icvcmd) { 1065 - case IP_ICV_OFFSET: 1066 - job->icv_offset = icvoff; 1067 - job->ctrl &= ~SPACC_CTRL_MASK(SPACC_CTRL_ICV_APPEND); 1068 - break; 1069 - case IP_ICV_APPEND: 1070 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_ICV_APPEND); 1071 - break; 1072 - case IP_ICV_IGNORE: 1073 - break; 1074 - default: 1075 - ret = -EINVAL; 1076 - } 1077 - 1078 - if (sec_key) 1079 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_SEC_KEY); 1080 - 1081 - return ret; 1082 - } 1083 - 1084 - static int _spacc_fifo_full(struct spacc_device *spacc, uint32_t prio) 1085 - { 1086 - if (spacc->config.is_qos) 1087 - return readl(spacc->regmap + SPACC_REG_FIFO_STAT) & 1088 - SPACC_FIFO_STAT_CMDX_FULL(prio); 1089 - else 1090 - return readl(spacc->regmap + SPACC_REG_FIFO_STAT) & 1091 - SPACC_FIFO_STAT_CMD0_FULL; 1092 - } 1093 - 1094 - /* When proc_sz != 0 it overrides the ddt_len value 1095 - * defined in the context referenced by 'job_idx' 1096 - */ 1097 - int spacc_packet_enqueue_ddt_ex(struct spacc_device *spacc, int use_jb, 1098 - int job_idx, struct pdu_ddt *src_ddt, 1099 - struct pdu_ddt *dst_ddt, u32 proc_sz, 1100 - uint32_t aad_offset, uint32_t pre_aad_sz, 1101 - u32 post_aad_sz, uint32_t iv_offset, 1102 - uint32_t prio) 1103 - { 1104 - int i; 1105 - struct spacc_job *job; 1106 - int proc_len; 1107 - 1108 - if (job_idx < 0 || job_idx >= SPACC_MAX_JOBS) 1109 - return -ENXIO; 1110 - 1111 - switch (prio) { 1112 - case SPACC_SW_CTRL_PRIO_MED: 1113 - if (spacc->config.cmd1_fifo_depth == 0) 1114 - return -EINVAL; 1115 - break; 1116 - case SPACC_SW_CTRL_PRIO_LOW: 1117 - if (spacc->config.cmd2_fifo_depth == 0) 1118 - return -EINVAL; 1119 - break; 1120 - } 1121 - 1122 - job = &spacc->job[job_idx]; 1123 - if (!job) 1124 - return -EIO; 1125 - 1126 - /* process any jobs in the jb*/ 1127 - if (use_jb && spacc_process_jb(spacc) != 0) 1128 - goto fifo_full; 1129 - 1130 - if (_spacc_fifo_full(spacc, prio)) { 1131 - if (use_jb) 1132 - goto fifo_full; 1133 - else 1134 - return -EBUSY; 1135 - } 1136 - 1137 - /* compute the length we must process, in decrypt mode 1138 - * with an ICV (hash, hmac or CCM modes) 1139 - * we must subtract the icv length from the buffer size 1140 - */ 1141 - if (proc_sz == SPACC_AUTO_SIZE) { 1142 - proc_len = src_ddt->len; 1143 - 1144 - if (job->op == OP_DECRYPT && 1145 - (job->hash_mode > 0 || 1146 - job->enc_mode == CRYPTO_MODE_AES_CCM || 1147 - job->enc_mode == CRYPTO_MODE_AES_GCM) && 1148 - !(job->ctrl & SPACC_CTRL_MASK(SPACC_CTRL_ICV_ENC))) 1149 - proc_len = src_ddt->len - job->icv_len; 1150 - } else { 1151 - proc_len = proc_sz; 1152 - } 1153 - 1154 - if (pre_aad_sz & SPACC_AADCOPY_FLAG) { 1155 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_AAD_COPY); 1156 - pre_aad_sz &= ~(SPACC_AADCOPY_FLAG); 1157 - } else { 1158 - job->ctrl &= ~SPACC_CTRL_MASK(SPACC_CTRL_AAD_COPY); 1159 - } 1160 - 1161 - job->pre_aad_sz = pre_aad_sz; 1162 - job->post_aad_sz = post_aad_sz; 1163 - 1164 - if (spacc->config.dma_type == SPACC_DMA_DDT) { 1165 - pdu_io_cached_write(spacc->regmap + SPACC_REG_SRC_PTR, 1166 - (uint32_t)src_ddt->phys, 1167 - &spacc->cache.src_ptr); 1168 - pdu_io_cached_write(spacc->regmap + SPACC_REG_DST_PTR, 1169 - (uint32_t)dst_ddt->phys, 1170 - &spacc->cache.dst_ptr); 1171 - } else if (spacc->config.dma_type == SPACC_DMA_LINEAR) { 1172 - pdu_io_cached_write(spacc->regmap + SPACC_REG_SRC_PTR, 1173 - (uint32_t)src_ddt->virt[0], 1174 - &spacc->cache.src_ptr); 1175 - pdu_io_cached_write(spacc->regmap + SPACC_REG_DST_PTR, 1176 - (uint32_t)dst_ddt->virt[0], 1177 - &spacc->cache.dst_ptr); 1178 - } else { 1179 - return -EIO; 1180 - } 1181 - 1182 - pdu_io_cached_write(spacc->regmap + SPACC_REG_PROC_LEN, 1183 - proc_len - job->post_aad_sz, 1184 - &spacc->cache.proc_len); 1185 - pdu_io_cached_write(spacc->regmap + SPACC_REG_ICV_LEN, 1186 - job->icv_len, &spacc->cache.icv_len); 1187 - pdu_io_cached_write(spacc->regmap + SPACC_REG_ICV_OFFSET, 1188 - job->icv_offset, &spacc->cache.icv_offset); 1189 - pdu_io_cached_write(spacc->regmap + SPACC_REG_PRE_AAD_LEN, 1190 - job->pre_aad_sz, &spacc->cache.pre_aad); 1191 - pdu_io_cached_write(spacc->regmap + SPACC_REG_POST_AAD_LEN, 1192 - job->post_aad_sz, &spacc->cache.post_aad); 1193 - pdu_io_cached_write(spacc->regmap + SPACC_REG_IV_OFFSET, 1194 - iv_offset, &spacc->cache.iv_offset); 1195 - pdu_io_cached_write(spacc->regmap + SPACC_REG_OFFSET, 1196 - aad_offset, &spacc->cache.offset); 1197 - pdu_io_cached_write(spacc->regmap + SPACC_REG_AUX_INFO, 1198 - AUX_DIR(job->auxinfo_dir) | 1199 - AUX_BIT_ALIGN(job->auxinfo_bit_align) | 1200 - AUX_CBC_CS(job->auxinfo_cs_mode), 1201 - &spacc->cache.aux); 1202 - 1203 - if (job->first_use == 1) { 1204 - writel(job->ckey_sz | SPACC_SET_KEY_CTX(job->ctx_idx), 1205 - spacc->regmap + SPACC_REG_KEY_SZ); 1206 - writel(job->hkey_sz | SPACC_SET_KEY_CTX(job->ctx_idx), 1207 - spacc->regmap + SPACC_REG_KEY_SZ); 1208 - } 1209 - 1210 - job->job_swid = spacc->job_next_swid; 1211 - spacc->job_lookup[job->job_swid] = job_idx; 1212 - spacc->job_next_swid = 1213 - (spacc->job_next_swid + 1) % SPACC_MAX_JOBS; 1214 - writel(SPACC_SW_CTRL_ID_SET(job->job_swid) | 1215 - SPACC_SW_CTRL_PRIO_SET(prio), 1216 - spacc->regmap + SPACC_REG_SW_CTRL); 1217 - writel(job->ctrl, spacc->regmap + SPACC_REG_CTRL); 1218 - 1219 - /* Clear an expansion key after the first call*/ 1220 - if (job->first_use == 1) { 1221 - job->first_use = 0; 1222 - job->ctrl &= ~SPACC_CTRL_MASK(SPACC_CTRL_KEY_EXP); 1223 - } 1224 - 1225 - return CRYPTO_OK; 1226 - 1227 - fifo_full: 1228 - /* try to add a job to the job buffers*/ 1229 - i = spacc->jb_head + 1; 1230 - if (i == SPACC_MAX_JOB_BUFFERS) 1231 - i = 0; 1232 - 1233 - if (i == spacc->jb_tail) 1234 - return -EBUSY; 1235 - 1236 - spacc->job_buffer[spacc->jb_head] = (struct spacc_job_buffer) { 1237 - .active = 1, 1238 - .job_idx = job_idx, 1239 - .src = src_ddt, 1240 - .dst = dst_ddt, 1241 - .proc_sz = proc_sz, 1242 - .aad_offset = aad_offset, 1243 - .pre_aad_sz = pre_aad_sz, 1244 - .post_aad_sz = post_aad_sz, 1245 - .iv_offset = iv_offset, 1246 - .prio = prio 1247 - }; 1248 - 1249 - spacc->jb_head = i; 1250 - 1251 - return CRYPTO_OK; 1252 - } 1253 - 1254 - int spacc_packet_enqueue_ddt(struct spacc_device *spacc, int job_idx, 1255 - struct pdu_ddt *src_ddt, struct pdu_ddt *dst_ddt, 1256 - u32 proc_sz, u32 aad_offset, uint32_t pre_aad_sz, 1257 - uint32_t post_aad_sz, u32 iv_offset, uint32_t prio) 1258 - { 1259 - int ret; 1260 - unsigned long lock_flags; 1261 - 1262 - spin_lock_irqsave(&spacc->lock, lock_flags); 1263 - ret = spacc_packet_enqueue_ddt_ex(spacc, 1, job_idx, src_ddt, 1264 - dst_ddt, proc_sz, aad_offset, 1265 - pre_aad_sz, post_aad_sz, 1266 - iv_offset, prio); 1267 - spin_unlock_irqrestore(&spacc->lock, lock_flags); 1268 - 1269 - return ret; 1270 - } 1271 - 1272 - static int spacc_packet_dequeue(struct spacc_device *spacc, int job_idx) 1273 - { 1274 - int ret = CRYPTO_OK; 1275 - struct spacc_job *job = &spacc->job[job_idx]; 1276 - unsigned long lock_flag; 1277 - 1278 - spin_lock_irqsave(&spacc->lock, lock_flag); 1279 - 1280 - if (!job && !(job_idx == SPACC_JOB_IDX_UNUSED)) { 1281 - ret = -EIO; 1282 - } else if (job->job_done) { 1283 - job->job_done = 0; 1284 - ret = job->job_err; 1285 - } else { 1286 - ret = -EINPROGRESS; 1287 - } 1288 - 1289 - spin_unlock_irqrestore(&spacc->lock, lock_flag); 1290 - 1291 - return ret; 1292 - } 1293 - 1294 - int spacc_isenabled(struct spacc_device *spacc, int mode, int keysize) 1295 - { 1296 - int x; 1297 - 1298 - if (mode < 0 || mode >= CRYPTO_MODE_LAST) 1299 - return 0; 1300 - 1301 - if (mode == CRYPTO_MODE_NULL || 1302 - mode == CRYPTO_MODE_AES_XTS || 1303 - mode == CRYPTO_MODE_SM4_XTS || 1304 - mode == CRYPTO_MODE_AES_F8 || 1305 - mode == CRYPTO_MODE_SM4_F8 || 1306 - spacc->config.modes[mode] & 128) 1307 - return 1; 1308 - 1309 - for (x = 0; x < 6; x++) { 1310 - if (keysizes[0][x] == keysize) { 1311 - if (spacc->config.modes[mode] & (1 << x)) 1312 - return 1; 1313 - else 1314 - return 0; 1315 - } 1316 - } 1317 - 1318 - return 0; 1319 - } 1320 - 1321 - /* Releases a crypto context back into appropriate module's pool*/ 1322 - int spacc_close(struct spacc_device *dev, int handle) 1323 - { 1324 - return spacc_job_release(dev, handle); 1325 - } 1326 - 1327 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_AUTODETECT) 1328 - static int spacc_set_auxinfo(struct spacc_device *spacc, int jobid, 1329 - uint32_t direction, uint32_t bitsize) 1330 - { 1331 - int ret = CRYPTO_OK; 1332 - struct spacc_job *job; 1333 - 1334 - if (jobid < 0 || jobid >= SPACC_MAX_JOBS) 1335 - return -ENXIO; 1336 - 1337 - job = &spacc->job[jobid]; 1338 - if (!job) { 1339 - ret = -EIO; 1340 - } else { 1341 - job->auxinfo_dir = direction; 1342 - job->auxinfo_bit_align = bitsize; 1343 - } 1344 - 1345 - return ret; 1346 - } 1347 - 1348 - static void check_modes(struct spacc_device *spacc, int x, int y, void *virt, 1349 - char *key, struct pdu_ddt *ddt) 1350 - { 1351 - int proclen, aadlen, ivsize, h, err, enc, hash; 1352 - 1353 - if (template[x] & (1 << y)) { 1354 - /* testing keysizes[y] with algo 'x' which 1355 - * should match the ENUMs above 1356 - */ 1357 - 1358 - if (template[x] & 128) { 1359 - enc = 0; 1360 - hash = x; 1361 - } else { 1362 - enc = x; 1363 - hash = 0; 1364 - } 1365 - 1366 - h = spacc_open(spacc, enc, hash, -1, 0, NULL, NULL); 1367 - if (h < 0) { 1368 - spacc->config.modes[x] &= ~(1 << y); 1369 - return; 1370 - } 1371 - 1372 - spacc_set_operation(spacc, h, OP_ENCRYPT, 0, IP_ICV_APPEND, 0, 1373 - 0, 0); 1374 - 1375 - /* if this is a hash or mac*/ 1376 - if (template[x] & 128) { 1377 - switch (x) { 1378 - case CRYPTO_MODE_HASH_CSHAKE128: 1379 - case CRYPTO_MODE_HASH_CSHAKE256: 1380 - case CRYPTO_MODE_MAC_KMAC128: 1381 - case CRYPTO_MODE_MAC_KMAC256: 1382 - case CRYPTO_MODE_MAC_KMACXOF128: 1383 - case CRYPTO_MODE_MAC_KMACXOF256: 1384 - /* special initial bytes to encode 1385 - * length for cust strings 1386 - */ 1387 - key[0] = 0x01; 1388 - key[1] = 0x70; 1389 - break; 1390 - } 1391 - 1392 - spacc_write_context(spacc, h, SPACC_HASH_OPERATION, 1393 - key, keysizes[1][y] + 1394 - (x == CRYPTO_MODE_MAC_XCBC ? 32 : 0), 1395 - key, 16); 1396 - } else { 1397 - u32 keysize; 1398 - 1399 - ivsize = 16; 1400 - keysize = keysizes[0][y]; 1401 - switch (x) { 1402 - case CRYPTO_MODE_CHACHA20_STREAM: 1403 - case CRYPTO_MODE_AES_CCM: 1404 - case CRYPTO_MODE_SM4_CCM: 1405 - ivsize = 16; 1406 - break; 1407 - case CRYPTO_MODE_SM4_GCM: 1408 - case CRYPTO_MODE_CHACHA20_POLY1305: 1409 - case CRYPTO_MODE_AES_GCM: 1410 - ivsize = 12; 1411 - break; 1412 - case CRYPTO_MODE_KASUMI_ECB: 1413 - case CRYPTO_MODE_KASUMI_F8: 1414 - case CRYPTO_MODE_3DES_CBC: 1415 - case CRYPTO_MODE_3DES_ECB: 1416 - case CRYPTO_MODE_DES_CBC: 1417 - case CRYPTO_MODE_DES_ECB: 1418 - ivsize = 8; 1419 - break; 1420 - case CRYPTO_MODE_SM4_XTS: 1421 - case CRYPTO_MODE_AES_XTS: 1422 - keysize <<= 1; 1423 - break; 1424 - } 1425 - spacc_write_context(spacc, h, SPACC_CRYPTO_OPERATION, 1426 - key, keysize, key, ivsize); 1427 - } 1428 - 1429 - spacc_set_key_exp(spacc, h); 1430 - 1431 - switch (x) { 1432 - case CRYPTO_MODE_ZUC_UEA3: 1433 - case CRYPTO_MODE_SNOW3G_UEA2: 1434 - case CRYPTO_MODE_MAC_SNOW3G_UIA2: 1435 - case CRYPTO_MODE_MAC_ZUC_UIA3: 1436 - case CRYPTO_MODE_KASUMI_F8: 1437 - spacc_set_auxinfo(spacc, h, 0, 0); 1438 - break; 1439 - case CRYPTO_MODE_MAC_KASUMI_F9: 1440 - spacc_set_auxinfo(spacc, h, 0, 8); 1441 - break; 1442 - } 1443 - 1444 - memset(virt, 0, 256); 1445 - 1446 - /* 16AAD/16PT or 32AAD/0PT depending on 1447 - * whether we're in a hash or not mode 1448 - */ 1449 - aadlen = 16; 1450 - proclen = 32; 1451 - if (!enc) 1452 - aadlen += 16; 1453 - 1454 - switch (x) { 1455 - case CRYPTO_MODE_SM4_CS1: 1456 - case CRYPTO_MODE_SM4_CS2: 1457 - case CRYPTO_MODE_SM4_CS3: 1458 - case CRYPTO_MODE_AES_CS1: 1459 - case CRYPTO_MODE_AES_CS2: 1460 - case CRYPTO_MODE_AES_CS3: 1461 - proclen = 31; 1462 - fallthrough; 1463 - case CRYPTO_MODE_SM4_XTS: 1464 - case CRYPTO_MODE_AES_XTS: 1465 - aadlen = 0; 1466 - } 1467 - 1468 - err = spacc_packet_enqueue_ddt(spacc, h, ddt, ddt, proclen, 0, 1469 - aadlen, 0, 0, 0); 1470 - if (err == CRYPTO_OK) { 1471 - do { 1472 - err = spacc_packet_dequeue(spacc, h); 1473 - } while (err == -EINPROGRESS); 1474 - } 1475 - if (err != CRYPTO_OK || !testdata[x].test[y].outlen || 1476 - memcmp(testdata[x].test[y].data, virt, 1477 - testdata[x].test[y].outlen)) { 1478 - spacc->config.modes[x] &= ~(1 << y); 1479 - } 1480 - spacc_close(spacc, h); 1481 - } 1482 - } 1483 - 1484 - int spacc_autodetect(struct spacc_device *spacc) 1485 - { 1486 - struct pdu_ddt ddt; 1487 - dma_addr_t dma; 1488 - void *virt; 1489 - int x, y; 1490 - unsigned char key[64]; 1491 - 1492 - /* allocate DMA memory ...*/ 1493 - virt = dma_alloc_coherent(get_ddt_device(), 256, &dma, GFP_KERNEL); 1494 - if (!virt) 1495 - return -2; 1496 - 1497 - if (pdu_ddt_init(&ddt, 1)) { 1498 - dma_free_coherent(get_ddt_device(), 256, virt, dma); 1499 - return -3; 1500 - } 1501 - 1502 - pdu_ddt_add(&ddt, dma, 256); 1503 - 1504 - for (x = 0; x < 64; x++) 1505 - key[x] = x; 1506 - 1507 - for (x = 0; x < ARRAY_SIZE(template); x++) { 1508 - spacc->config.modes[x] = template[x]; 1509 - if (template[x] && spacc->config.version >= 1510 - testdata[x].min_version) { 1511 - for (y = 0; y < (ARRAY_SIZE(keysizes[0])); y++) 1512 - check_modes(spacc, x, y, virt, key, &ddt); 1513 - } 1514 - } 1515 - 1516 - pdu_ddt_free(&ddt); 1517 - dma_free_coherent(get_ddt_device(), 256, virt, dma); 1518 - 1519 - return 0; 1520 - } 1521 - 1522 - #else 1523 - 1524 - static void spacc_static_modes(struct spacc_device *spacc, int x, int y) 1525 - { 1526 - /* Disable the algos that as not supported here */ 1527 - switch (x) { 1528 - case CRYPTO_MODE_AES_F8: 1529 - case CRYPTO_MODE_AES_CFB: 1530 - case CRYPTO_MODE_AES_OFB: 1531 - case CRYPTO_MODE_MULTI2_ECB: 1532 - case CRYPTO_MODE_MULTI2_CBC: 1533 - case CRYPTO_MODE_MULTI2_CFB: 1534 - case CRYPTO_MODE_MULTI2_OFB: 1535 - case CRYPTO_MODE_MAC_POLY1305: 1536 - case CRYPTO_MODE_HASH_CRC32: 1537 - /* Disable the modes */ 1538 - spacc->config.modes[x] &= ~(1 << y); 1539 - break; 1540 - default: 1541 - break;/* Algos are enabled */ 1542 - } 1543 - } 1544 - 1545 - int spacc_static_config(struct spacc_device *spacc) 1546 - { 1547 - 1548 - int x, y; 1549 - 1550 - for (x = 0; x < ARRAY_SIZE(template); x++) { 1551 - spacc->config.modes[x] = template[x]; 1552 - 1553 - for (y = 0; y < (ARRAY_SIZE(keysizes[0])); y++) { 1554 - /* List static modes */ 1555 - spacc_static_modes(spacc, x, y); 1556 - } 1557 - } 1558 - 1559 - return 0; 1560 - } 1561 - #endif 1562 - int spacc_clone_handle(struct spacc_device *spacc, int old_handle, 1563 - void *cbdata) 1564 - { 1565 - int new_handle; 1566 - 1567 - new_handle = spacc_job_request(spacc, spacc->job[old_handle].ctx_idx); 1568 - if (new_handle < 0) 1569 - return new_handle; 1570 - 1571 - spacc->job[new_handle] = spacc->job[old_handle]; 1572 - spacc->job[new_handle].job_used = new_handle; 1573 - spacc->job[new_handle].cbdata = cbdata; 1574 - 1575 - return new_handle; 1576 - } 1577 - 1578 - /* Allocates a job for spacc module context and initialize 1579 - * it with an appropriate type. 1580 - */ 1581 - int spacc_open(struct spacc_device *spacc, int enc, int hash, int ctxid, 1582 - int secure_mode, spacc_callback cb, void *cbdata) 1583 - { 1584 - u32 ctrl = 0; 1585 - int job_idx = 0; 1586 - int ret = CRYPTO_OK; 1587 - struct spacc_job *job = NULL; 1588 - 1589 - job_idx = spacc_job_request(spacc, ctxid); 1590 - if (job_idx < 0) 1591 - return -EIO; 1592 - 1593 - job = &spacc->job[job_idx]; 1594 - 1595 - if (secure_mode && job->ctx_idx > spacc->config.num_sec_ctx) { 1596 - pr_debug("ERR: For secure contexts"); 1597 - pr_debug("ERR: Job ctx ID is outside allowed range\n"); 1598 - spacc_job_release(spacc, job_idx); 1599 - return -EIO; 1600 - } 1601 - 1602 - job->auxinfo_cs_mode = 0; 1603 - job->auxinfo_bit_align = 0; 1604 - job->auxinfo_dir = 0; 1605 - job->icv_len = 0; 1606 - 1607 - switch (enc) { 1608 - case CRYPTO_MODE_NULL: 1609 - break; 1610 - case CRYPTO_MODE_AES_ECB: 1611 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1612 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_ECB); 1613 - break; 1614 - case CRYPTO_MODE_AES_CBC: 1615 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1616 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1617 - break; 1618 - 1619 - case CRYPTO_MODE_AES_CS1: 1620 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1621 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1622 - job->auxinfo_cs_mode = 1; 1623 - break; 1624 - case CRYPTO_MODE_AES_CS2: 1625 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1626 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1627 - job->auxinfo_cs_mode = 2; 1628 - break; 1629 - case CRYPTO_MODE_AES_CS3: 1630 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1631 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1632 - job->auxinfo_cs_mode = 3; 1633 - break; 1634 - case CRYPTO_MODE_AES_CFB: 1635 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1636 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CFB); 1637 - break; 1638 - case CRYPTO_MODE_AES_OFB: 1639 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1640 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_OFB); 1641 - break; 1642 - case CRYPTO_MODE_AES_CTR: 1643 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1644 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CTR); 1645 - break; 1646 - case CRYPTO_MODE_AES_CCM: 1647 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1648 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CCM); 1649 - break; 1650 - case CRYPTO_MODE_AES_GCM: 1651 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1652 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_GCM); 1653 - break; 1654 - case CRYPTO_MODE_AES_F8: 1655 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1656 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_F8); 1657 - break; 1658 - case CRYPTO_MODE_AES_XTS: 1659 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_AES); 1660 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_XTS); 1661 - break; 1662 - case CRYPTO_MODE_MULTI2_ECB: 1663 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_MULTI2); 1664 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_ECB); 1665 - break; 1666 - case CRYPTO_MODE_MULTI2_CBC: 1667 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_MULTI2); 1668 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1669 - break; 1670 - case CRYPTO_MODE_MULTI2_OFB: 1671 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_MULTI2); 1672 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_OFB); 1673 - break; 1674 - case CRYPTO_MODE_MULTI2_CFB: 1675 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_MULTI2); 1676 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CFB); 1677 - break; 1678 - case CRYPTO_MODE_3DES_CBC: 1679 - case CRYPTO_MODE_DES_CBC: 1680 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_DES); 1681 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1682 - break; 1683 - case CRYPTO_MODE_3DES_ECB: 1684 - case CRYPTO_MODE_DES_ECB: 1685 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_DES); 1686 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_ECB); 1687 - break; 1688 - case CRYPTO_MODE_KASUMI_ECB: 1689 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_KASUMI); 1690 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_ECB); 1691 - break; 1692 - case CRYPTO_MODE_KASUMI_F8: 1693 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_KASUMI); 1694 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_F8); 1695 - break; 1696 - case CRYPTO_MODE_SNOW3G_UEA2: 1697 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, 1698 - C_SNOW3G_UEA2); 1699 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_ECB); 1700 - break; 1701 - case CRYPTO_MODE_ZUC_UEA3: 1702 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, 1703 - C_ZUC_UEA3); 1704 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_ECB); 1705 - break; 1706 - case CRYPTO_MODE_CHACHA20_STREAM: 1707 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_CHACHA20); 1708 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CHACHA_STREAM); 1709 - break; 1710 - case CRYPTO_MODE_CHACHA20_POLY1305: 1711 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, 1712 - C_CHACHA20); 1713 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, 1714 - CM_CHACHA_AEAD); 1715 - break; 1716 - case CRYPTO_MODE_SM4_ECB: 1717 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1718 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_ECB); 1719 - break; 1720 - case CRYPTO_MODE_SM4_CBC: 1721 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1722 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1723 - break; 1724 - case CRYPTO_MODE_SM4_CS1: 1725 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1726 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1727 - job->auxinfo_cs_mode = 1; 1728 - break; 1729 - case CRYPTO_MODE_SM4_CS2: 1730 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1731 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1732 - job->auxinfo_cs_mode = 2; 1733 - break; 1734 - case CRYPTO_MODE_SM4_CS3: 1735 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1736 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CBC); 1737 - job->auxinfo_cs_mode = 3; 1738 - break; 1739 - case CRYPTO_MODE_SM4_CFB: 1740 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1741 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CFB); 1742 - break; 1743 - case CRYPTO_MODE_SM4_OFB: 1744 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1745 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_OFB); 1746 - break; 1747 - case CRYPTO_MODE_SM4_CTR: 1748 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1749 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CTR); 1750 - break; 1751 - case CRYPTO_MODE_SM4_CCM: 1752 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1753 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_CCM); 1754 - break; 1755 - case CRYPTO_MODE_SM4_GCM: 1756 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1757 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_GCM); 1758 - break; 1759 - case CRYPTO_MODE_SM4_F8: 1760 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1761 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_F8); 1762 - break; 1763 - case CRYPTO_MODE_SM4_XTS: 1764 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_ALG, C_SM4); 1765 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_CIPH_MODE, CM_XTS); 1766 - break; 1767 - default: 1768 - ret = -EOPNOTSUPP; 1769 - } 1770 - 1771 - switch (hash) { 1772 - case CRYPTO_MODE_NULL: 1773 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_NULL); 1774 - break; 1775 - case CRYPTO_MODE_HMAC_SHA1: 1776 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA1); 1777 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1778 - break; 1779 - case CRYPTO_MODE_HMAC_MD5: 1780 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_MD5); 1781 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1782 - break; 1783 - case CRYPTO_MODE_HMAC_SHA224: 1784 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA224); 1785 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1786 - break; 1787 - case CRYPTO_MODE_HMAC_SHA256: 1788 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA256); 1789 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1790 - break; 1791 - case CRYPTO_MODE_HMAC_SHA384: 1792 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA384); 1793 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1794 - break; 1795 - case CRYPTO_MODE_HMAC_SHA512: 1796 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA512); 1797 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1798 - break; 1799 - case CRYPTO_MODE_HMAC_SHA512_224: 1800 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1801 - H_SHA512_224); 1802 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1803 - break; 1804 - case CRYPTO_MODE_HMAC_SHA512_256: 1805 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1806 - H_SHA512_256); 1807 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1808 - break; 1809 - case CRYPTO_MODE_SSLMAC_MD5: 1810 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_MD5); 1811 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1812 - HM_SSLMAC); 1813 - break; 1814 - case CRYPTO_MODE_SSLMAC_SHA1: 1815 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA1); 1816 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1817 - HM_SSLMAC); 1818 - break; 1819 - case CRYPTO_MODE_HASH_SHA1: 1820 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA1); 1821 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1822 - break; 1823 - case CRYPTO_MODE_HASH_MD5: 1824 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_MD5); 1825 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1826 - break; 1827 - case CRYPTO_MODE_HASH_SHA224: 1828 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA224); 1829 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1830 - break; 1831 - case CRYPTO_MODE_HASH_SHA256: 1832 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA256); 1833 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1834 - break; 1835 - case CRYPTO_MODE_HASH_SHA384: 1836 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA384); 1837 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1838 - break; 1839 - case CRYPTO_MODE_HASH_SHA512: 1840 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SHA512); 1841 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1842 - break; 1843 - case CRYPTO_MODE_HASH_SHA512_224: 1844 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1845 - H_SHA512_224); 1846 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1847 - break; 1848 - case CRYPTO_MODE_HASH_SHA512_256: 1849 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1850 - H_SHA512_256); 1851 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1852 - break; 1853 - case CRYPTO_MODE_HASH_SHA3_224: 1854 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1855 - H_SHA3_224); 1856 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1857 - break; 1858 - case CRYPTO_MODE_HASH_SHA3_256: 1859 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1860 - H_SHA3_256); 1861 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1862 - break; 1863 - case CRYPTO_MODE_HASH_SHA3_384: 1864 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1865 - H_SHA3_384); 1866 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1867 - break; 1868 - case CRYPTO_MODE_HASH_SHA3_512: 1869 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1870 - H_SHA3_512); 1871 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1872 - break; 1873 - case CRYPTO_MODE_HASH_SHAKE128: 1874 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1875 - H_SHAKE128); 1876 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1877 - HM_SHAKE_SHAKE); 1878 - break; 1879 - case CRYPTO_MODE_HASH_SHAKE256: 1880 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1881 - H_SHAKE256); 1882 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1883 - HM_SHAKE_SHAKE); 1884 - break; 1885 - case CRYPTO_MODE_HASH_CSHAKE128: 1886 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1887 - H_SHAKE128); 1888 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1889 - HM_SHAKE_CSHAKE); 1890 - break; 1891 - case CRYPTO_MODE_HASH_CSHAKE256: 1892 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1893 - H_SHAKE256); 1894 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1895 - HM_SHAKE_CSHAKE); 1896 - break; 1897 - case CRYPTO_MODE_MAC_KMAC128: 1898 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1899 - H_SHAKE128); 1900 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1901 - HM_SHAKE_KMAC); 1902 - break; 1903 - case CRYPTO_MODE_MAC_KMAC256: 1904 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1905 - H_SHAKE256); 1906 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1907 - HM_SHAKE_KMAC); 1908 - break; 1909 - case CRYPTO_MODE_MAC_KMACXOF128: 1910 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1911 - H_SHAKE128); 1912 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1913 - HM_SHAKE_KMAC); 1914 - /* auxinfo_dir reused to indicate XOF */ 1915 - job->auxinfo_dir = 1; 1916 - break; 1917 - case CRYPTO_MODE_MAC_KMACXOF256: 1918 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1919 - H_SHAKE256); 1920 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, 1921 - HM_SHAKE_KMAC); 1922 - /* auxinfo_dir reused to indicate XOF */ 1923 - job->auxinfo_dir = 1; 1924 - break; 1925 - case CRYPTO_MODE_MAC_XCBC: 1926 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_XCBC); 1927 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1928 - break; 1929 - case CRYPTO_MODE_MAC_CMAC: 1930 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_CMAC); 1931 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1932 - break; 1933 - case CRYPTO_MODE_MAC_KASUMI_F9: 1934 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_KF9); 1935 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1936 - break; 1937 - case CRYPTO_MODE_MAC_SNOW3G_UIA2: 1938 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1939 - H_SNOW3G_UIA2); 1940 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1941 - break; 1942 - case CRYPTO_MODE_MAC_ZUC_UIA3: 1943 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1944 - H_ZUC_UIA3); 1945 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1946 - break; 1947 - case CRYPTO_MODE_MAC_POLY1305: 1948 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1949 - H_POLY1305); 1950 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1951 - break; 1952 - case CRYPTO_MODE_HASH_CRC32: 1953 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1954 - H_CRC32_I3E802_3); 1955 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1956 - break; 1957 - case CRYPTO_MODE_MAC_MICHAEL: 1958 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_MICHAEL); 1959 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1960 - break; 1961 - case CRYPTO_MODE_HASH_SM3: 1962 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SM3); 1963 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1964 - break; 1965 - case CRYPTO_MODE_HMAC_SM3: 1966 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, H_SM3); 1967 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_HMAC); 1968 - break; 1969 - case CRYPTO_MODE_MAC_SM4_XCBC: 1970 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1971 - H_SM4_XCBC_MAC); 1972 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1973 - break; 1974 - case CRYPTO_MODE_MAC_SM4_CMAC: 1975 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_ALG, 1976 - H_SM4_CMAC); 1977 - ctrl |= SPACC_CTRL_SET(SPACC_CTRL_HASH_MODE, HM_RAW); 1978 - break; 1979 - default: 1980 - ret = -EOPNOTSUPP; 1981 - } 1982 - ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_MSG_BEGIN) | 1983 - SPACC_CTRL_MASK(SPACC_CTRL_MSG_END); 1984 - 1985 - if (ret != CRYPTO_OK) { 1986 - spacc_job_release(spacc, job_idx); 1987 - } else { 1988 - ret = job_idx; 1989 - job->first_use = 1; 1990 - job->enc_mode = enc; 1991 - job->hash_mode = hash; 1992 - job->ckey_sz = 0; 1993 - job->hkey_sz = 0; 1994 - job->job_done = 0; 1995 - job->job_swid = 0; 1996 - job->job_secure = !!secure_mode; 1997 - 1998 - job->auxinfo_bit_align = 0; 1999 - job->job_err = -EINPROGRESS; 2000 - job->ctrl = ctrl | 2001 - SPACC_CTRL_SET(SPACC_CTRL_CTX_IDX, 2002 - job->ctx_idx); 2003 - job->cb = cb; 2004 - job->cbdata = cbdata; 2005 - } 2006 - 2007 - return ret; 2008 - } 2009 - 2010 - static int spacc_xof_stringsize_autodetect(struct spacc_device *spacc) 2011 - { 2012 - void *virt; 2013 - dma_addr_t dma; 2014 - struct pdu_ddt ddt; 2015 - int ss, alg, i, stat; 2016 - unsigned long spacc_ctrl[2] = {0xF400B400, 0xF400D400}; 2017 - unsigned char buf[256]; 2018 - unsigned long buflen, rbuf; 2019 - unsigned char test_str[6] = {0x01, 0x20, 0x54, 0x45, 0x53, 0x54}; 2020 - unsigned char md[2][16] = { 2021 - {0xc3, 0x6d, 0x0a, 0x88, 0xfa, 0x37, 0x4c, 0x9b, 2022 - 0x44, 0x74, 0xeb, 0x00, 0x5f, 0xe8, 0xca, 0x25}, 2023 - {0x68, 0x77, 0x04, 0x11, 0xf8, 0xe3, 0xb0, 0x1e, 2024 - 0x0d, 0xbf, 0x71, 0x6a, 0xe9, 0x87, 0x1a, 0x0d}}; 2025 - 2026 - virt = dma_alloc_coherent(get_ddt_device(), 256, &dma, GFP_KERNEL); 2027 - if (!virt) 2028 - return -EIO; 2029 - 2030 - if (pdu_ddt_init(&ddt, 1)) { 2031 - dma_free_coherent(get_ddt_device(), 256, virt, dma); 2032 - return -EIO; 2033 - } 2034 - pdu_ddt_add(&ddt, dma, 256); 2035 - 2036 - /* populate registers for jobs*/ 2037 - writel((uint32_t)ddt.phys, spacc->regmap + SPACC_REG_SRC_PTR); 2038 - writel((uint32_t)ddt.phys, spacc->regmap + SPACC_REG_DST_PTR); 2039 - 2040 - writel(16, spacc->regmap + SPACC_REG_PROC_LEN); 2041 - writel(16, spacc->regmap + SPACC_REG_PRE_AAD_LEN); 2042 - writel(16, spacc->regmap + SPACC_REG_ICV_LEN); 2043 - writel(6, spacc->regmap + SPACC_REG_KEY_SZ); 2044 - writel(0, spacc->regmap + SPACC_REG_SW_CTRL); 2045 - 2046 - /* repeat for 2 algorithms, CSHAKE128 and KMAC128*/ 2047 - for (alg = 0; (alg < 2) && (spacc->config.string_size == 0); alg++) { 2048 - /* repeat for 4 string_size sizes*/ 2049 - for (ss = 0; ss < 4; ss++) { 2050 - buflen = (32UL << ss); 2051 - if (buflen > spacc->config.hash_page_size) 2052 - break; 2053 - 2054 - /* clear I/O memory*/ 2055 - memset(virt, 0, 256); 2056 - 2057 - /* clear buf and then insert test string*/ 2058 - memset(buf, 0, sizeof(buf)); 2059 - memcpy(buf, test_str, sizeof(test_str)); 2060 - memcpy(buf + (buflen >> 1), test_str, sizeof(test_str)); 2061 - 2062 - /* write key context */ 2063 - pdu_to_dev_s(spacc->regmap + SPACC_CTX_HASH_KEY, 2064 - buf, 2065 - spacc->config.hash_page_size >> 2, 2066 - spacc->config.spacc_endian); 2067 - 2068 - /* write ctrl register */ 2069 - writel(spacc_ctrl[alg], spacc->regmap + SPACC_REG_CTRL); 2070 - 2071 - /* wait for job to complete */ 2072 - for (i = 0; i < 20; i++) { 2073 - rbuf = 0; 2074 - rbuf = readl(spacc->regmap + 2075 - SPACC_REG_FIFO_STAT) & 2076 - SPACC_FIFO_STAT_STAT_EMPTY; 2077 - if (!rbuf) { 2078 - /* check result, if it matches, 2079 - * we have string_size 2080 - */ 2081 - writel(1, spacc->regmap + 2082 - SPACC_REG_STAT_POP); 2083 - rbuf = 0; 2084 - rbuf = readl(spacc->regmap + 2085 - SPACC_REG_STATUS); 2086 - stat = SPACC_GET_STATUS_RET_CODE(rbuf); 2087 - if ((!memcmp(virt, md[alg], 16)) && 2088 - stat == SPACC_OK) { 2089 - spacc->config.string_size = 2090 - (16 << ss); 2091 - } 2092 - break; 2093 - } 2094 - } 2095 - } 2096 - } 2097 - 2098 - /* reset registers */ 2099 - writel(0, spacc->regmap + SPACC_REG_IRQ_CTRL); 2100 - writel(0, spacc->regmap + SPACC_REG_IRQ_EN); 2101 - writel(0xFFFFFFFF, spacc->regmap + SPACC_REG_IRQ_STAT); 2102 - 2103 - writel(0, spacc->regmap + SPACC_REG_SRC_PTR); 2104 - writel(0, spacc->regmap + SPACC_REG_DST_PTR); 2105 - writel(0, spacc->regmap + SPACC_REG_PROC_LEN); 2106 - writel(0, spacc->regmap + SPACC_REG_ICV_LEN); 2107 - writel(0, spacc->regmap + SPACC_REG_PRE_AAD_LEN); 2108 - 2109 - pdu_ddt_free(&ddt); 2110 - dma_free_coherent(get_ddt_device(), 256, virt, dma); 2111 - 2112 - return CRYPTO_OK; 2113 - } 2114 - 2115 - /* free up the memory */ 2116 - void spacc_fini(struct spacc_device *spacc) 2117 - { 2118 - vfree(spacc->ctx); 2119 - vfree(spacc->job); 2120 - } 2121 - 2122 - int spacc_init(void __iomem *baseaddr, struct spacc_device *spacc, 2123 - struct pdu_info *info) 2124 - { 2125 - unsigned long id; 2126 - char version_string[3][16] = { "SPACC", "SPACC-PDU" }; 2127 - char idx_string[2][16] = { "(Normal Port)", "(Secure Port)" }; 2128 - char dma_type_string[4][16] = { "Unknown", "Scattergather", "Linear", 2129 - "Unknown" }; 2130 - 2131 - if (!baseaddr) { 2132 - pr_debug("ERR: baseaddr is NULL\n"); 2133 - return -1; 2134 - } 2135 - if (!spacc) { 2136 - pr_debug("ERR: spacc is NULL\n"); 2137 - return -1; 2138 - } 2139 - 2140 - memset(spacc, 0, sizeof(*spacc)); 2141 - spin_lock_init(&spacc->lock); 2142 - spin_lock_init(&spacc->ctx_lock); 2143 - 2144 - /* assign the baseaddr*/ 2145 - spacc->regmap = baseaddr; 2146 - 2147 - /* version info*/ 2148 - spacc->config.version = info->spacc_version.version; 2149 - spacc->config.pdu_version = (info->pdu_config.major << 4) | 2150 - info->pdu_config.minor; 2151 - spacc->config.project = info->spacc_version.project; 2152 - spacc->config.is_pdu = info->spacc_version.is_pdu; 2153 - spacc->config.is_qos = info->spacc_version.qos; 2154 - 2155 - /* misc*/ 2156 - spacc->config.is_partial = info->spacc_version.partial; 2157 - spacc->config.num_ctx = info->spacc_config.num_ctx; 2158 - spacc->config.ciph_page_size = 1U << 2159 - info->spacc_config.ciph_ctx_page_size; 2160 - 2161 - spacc->config.hash_page_size = 1U << 2162 - info->spacc_config.hash_ctx_page_size; 2163 - 2164 - spacc->config.dma_type = info->spacc_config.dma_type; 2165 - spacc->config.idx = info->spacc_version.vspacc_idx; 2166 - spacc->config.cmd0_fifo_depth = info->spacc_config.cmd0_fifo_depth; 2167 - spacc->config.cmd1_fifo_depth = info->spacc_config.cmd1_fifo_depth; 2168 - spacc->config.cmd2_fifo_depth = info->spacc_config.cmd2_fifo_depth; 2169 - spacc->config.stat_fifo_depth = info->spacc_config.stat_fifo_depth; 2170 - spacc->config.fifo_cnt = 1; 2171 - spacc->config.is_ivimport = info->spacc_version.ivimport; 2172 - 2173 - /* ctrl register map*/ 2174 - if (spacc->config.version <= 0x4E) 2175 - spacc->config.ctrl_map = spacc_ctrl_map[SPACC_CTRL_VER_0]; 2176 - else if (spacc->config.version <= 0x60) 2177 - spacc->config.ctrl_map = spacc_ctrl_map[SPACC_CTRL_VER_1]; 2178 - else 2179 - spacc->config.ctrl_map = spacc_ctrl_map[SPACC_CTRL_VER_2]; 2180 - 2181 - spacc->job_next_swid = 0; 2182 - spacc->wdcnt = 0; 2183 - spacc->config.wd_timer = SPACC_WD_TIMER_INIT; 2184 - 2185 - /* version 4.10 uses IRQ, 2186 - * above uses WD and we don't support below 4.00 2187 - */ 2188 - if (spacc->config.version < 0x40) { 2189 - pr_debug("ERR: Unsupported SPAcc version\n"); 2190 - return -EIO; 2191 - } else if (spacc->config.version < 0x4B) { 2192 - spacc->op_mode = SPACC_OP_MODE_IRQ; 2193 - } else { 2194 - spacc->op_mode = SPACC_OP_MODE_WD; 2195 - } 2196 - 2197 - /* set threshold and enable irq 2198 - * on 4.11 and newer cores we can derive this 2199 - * from the HW reported depths. 2200 - */ 2201 - if (spacc->config.stat_fifo_depth == 1) 2202 - spacc->config.ideal_stat_level = 1; 2203 - else if (spacc->config.stat_fifo_depth <= 4) 2204 - spacc->config.ideal_stat_level = 2205 - spacc->config.stat_fifo_depth - 1; 2206 - else if (spacc->config.stat_fifo_depth <= 8) 2207 - spacc->config.ideal_stat_level = 2208 - spacc->config.stat_fifo_depth - 2; 2209 - else 2210 - spacc->config.ideal_stat_level = 2211 - spacc->config.stat_fifo_depth - 4; 2212 - 2213 - /* determine max PROClen value */ 2214 - writel(0xFFFFFFFF, spacc->regmap + SPACC_REG_PROC_LEN); 2215 - spacc->config.max_msg_size = readl(spacc->regmap + SPACC_REG_PROC_LEN); 2216 - 2217 - /* read config info*/ 2218 - if (spacc->config.is_pdu) { 2219 - pr_debug("PDU:\n"); 2220 - pr_debug(" MAJOR : %u\n", info->pdu_config.major); 2221 - pr_debug(" MINOR : %u\n", info->pdu_config.minor); 2222 - } 2223 - 2224 - id = readl(spacc->regmap + SPACC_REG_ID); 2225 - pr_debug("SPACC ID: (%08lx)\n", (unsigned long)id); 2226 - pr_debug(" MAJOR : %x\n", info->spacc_version.major); 2227 - pr_debug(" MINOR : %x\n", info->spacc_version.minor); 2228 - pr_debug(" QOS : %x\n", info->spacc_version.qos); 2229 - pr_debug(" IVIMPORT : %x\n", spacc->config.is_ivimport); 2230 - 2231 - if (spacc->config.version >= 0x48) 2232 - pr_debug(" TYPE : %lx (%s)\n", SPACC_ID_TYPE(id), 2233 - version_string[SPACC_ID_TYPE(id) & 3]); 2234 - 2235 - pr_debug(" AUX : %x\n", info->spacc_version.qos); 2236 - pr_debug(" IDX : %lx %s\n", SPACC_ID_VIDX(id), 2237 - spacc->config.is_secure ? 2238 - (idx_string[spacc->config.is_secure_port & 1]) : ""); 2239 - pr_debug(" PARTIAL : %x\n", info->spacc_version.partial); 2240 - pr_debug(" PROJECT : %x\n", info->spacc_version.project); 2241 - 2242 - if (spacc->config.version >= 0x48) 2243 - id = readl(spacc->regmap + SPACC_REG_CONFIG); 2244 - else 2245 - id = 0xFFFFFFFF; 2246 - 2247 - pr_debug("SPACC CFG: (%08lx)\n", id); 2248 - pr_debug(" CTX CNT : %u\n", info->spacc_config.num_ctx); 2249 - pr_debug(" VSPACC CNT : %u\n", info->spacc_config.num_vspacc); 2250 - pr_debug(" CIPH SZ : %-3lu bytes\n", 1UL << 2251 - info->spacc_config.ciph_ctx_page_size); 2252 - pr_debug(" HASH SZ : %-3lu bytes\n", 1UL << 2253 - info->spacc_config.hash_ctx_page_size); 2254 - pr_debug(" DMA TYPE : %u (%s)\n", info->spacc_config.dma_type, 2255 - dma_type_string[info->spacc_config.dma_type & 3]); 2256 - pr_debug(" MAX PROCLEN: %lu bytes\n", (unsigned long) 2257 - spacc->config.max_msg_size); 2258 - pr_debug(" FIFO CONFIG :\n"); 2259 - pr_debug(" CMD0 DEPTH: %d\n", spacc->config.cmd0_fifo_depth); 2260 - 2261 - if (spacc->config.is_qos) { 2262 - pr_debug(" CMD1 DEPTH: %d\n", 2263 - spacc->config.cmd1_fifo_depth); 2264 - pr_debug(" CMD2 DEPTH: %d\n", 2265 - spacc->config.cmd2_fifo_depth); 2266 - } 2267 - pr_debug(" STAT DEPTH: %d\n", spacc->config.stat_fifo_depth); 2268 - 2269 - if (spacc->config.dma_type == SPACC_DMA_DDT) { 2270 - writel(0x1234567F, baseaddr + SPACC_REG_DST_PTR); 2271 - writel(0xDEADBEEF, baseaddr + SPACC_REG_SRC_PTR); 2272 - 2273 - if (((readl(baseaddr + SPACC_REG_DST_PTR)) != 2274 - (0x1234567F & SPACC_DST_PTR_PTR)) || 2275 - ((readl(baseaddr + SPACC_REG_SRC_PTR)) != 2276 - (0xDEADBEEF & SPACC_SRC_PTR_PTR))) { 2277 - pr_debug("ERR: Failed to set pointers\n"); 2278 - goto ERR; 2279 - } 2280 - } 2281 - 2282 - /* zero the IRQ CTRL/EN register 2283 - * (to make sure we're in a sane state) 2284 - */ 2285 - writel(0, spacc->regmap + SPACC_REG_IRQ_CTRL); 2286 - writel(0, spacc->regmap + SPACC_REG_IRQ_EN); 2287 - writel(0xFFFFFFFF, spacc->regmap + SPACC_REG_IRQ_STAT); 2288 - 2289 - /* init cache*/ 2290 - memset(&spacc->cache, 0, sizeof(spacc->cache)); 2291 - writel(0, spacc->regmap + SPACC_REG_SRC_PTR); 2292 - writel(0, spacc->regmap + SPACC_REG_DST_PTR); 2293 - writel(0, spacc->regmap + SPACC_REG_PROC_LEN); 2294 - writel(0, spacc->regmap + SPACC_REG_ICV_LEN); 2295 - writel(0, spacc->regmap + SPACC_REG_ICV_OFFSET); 2296 - writel(0, spacc->regmap + SPACC_REG_PRE_AAD_LEN); 2297 - writel(0, spacc->regmap + SPACC_REG_POST_AAD_LEN); 2298 - writel(0, spacc->regmap + SPACC_REG_IV_OFFSET); 2299 - writel(0, spacc->regmap + SPACC_REG_OFFSET); 2300 - writel(0, spacc->regmap + SPACC_REG_AUX_INFO); 2301 - 2302 - spacc->ctx = vmalloc(sizeof(struct spacc_ctx) * spacc->config.num_ctx); 2303 - if (!spacc->ctx) 2304 - goto ERR; 2305 - 2306 - spacc->job = vmalloc(sizeof(struct spacc_job) * SPACC_MAX_JOBS); 2307 - if (!spacc->job) 2308 - goto ERR; 2309 - 2310 - /* initialize job_idx and lookup table */ 2311 - spacc_job_init_all(spacc); 2312 - 2313 - /* initialize contexts */ 2314 - spacc_ctx_init_all(spacc); 2315 - 2316 - /* autodetect and set string size setting*/ 2317 - if (spacc->config.version == 0x61 || spacc->config.version >= 0x65) 2318 - spacc_xof_stringsize_autodetect(spacc); 2319 - 2320 - return CRYPTO_OK; 2321 - ERR: 2322 - spacc_fini(spacc); 2323 - pr_debug("ERR: Crypto Failed\n"); 2324 - 2325 - return -EIO; 2326 - } 2327 - 2328 - /* callback function to initialize tasklet running */ 2329 - void spacc_pop_jobs(unsigned long data) 2330 - { 2331 - int num = 0; 2332 - struct spacc_priv *priv = (struct spacc_priv *)data; 2333 - struct spacc_device *spacc = &priv->spacc; 2334 - 2335 - /* decrement the WD CNT here since 2336 - * now we're actually going to respond 2337 - * to the IRQ completely 2338 - */ 2339 - if (spacc->wdcnt) 2340 - --(spacc->wdcnt); 2341 - 2342 - spacc_pop_packets(spacc, &num); 2343 - } 2344 - 2345 - int spacc_remove(struct platform_device *pdev) 2346 - { 2347 - struct spacc_device *spacc; 2348 - struct spacc_priv *priv = platform_get_drvdata(pdev); 2349 - 2350 - /* free test vector memory*/ 2351 - spacc = &priv->spacc; 2352 - spacc_fini(spacc); 2353 - 2354 - tasklet_kill(&priv->pop_jobs); 2355 - 2356 - /* devm functions do proper cleanup */ 2357 - pdu_mem_deinit(&pdev->dev); 2358 - dev_dbg(&pdev->dev, "removed!\n"); 2359 - 2360 - return 0; 2361 - } 2362 - 2363 - int spacc_set_key_exp(struct spacc_device *spacc, int job_idx) 2364 - { 2365 - struct spacc_ctx *ctx = NULL; 2366 - struct spacc_job *job = NULL; 2367 - 2368 - if (job_idx < 0 || job_idx >= SPACC_MAX_JOBS) { 2369 - pr_debug("ERR: Invalid Job id specified (out of range)\n"); 2370 - return -ENXIO; 2371 - } 2372 - 2373 - job = &spacc->job[job_idx]; 2374 - ctx = context_lookup_by_job(spacc, job_idx); 2375 - 2376 - if (!ctx) { 2377 - pr_debug("ERR: Failed to find ctx id\n"); 2378 - return -EIO; 2379 - } 2380 - 2381 - job->ctrl |= SPACC_CTRL_MASK(SPACC_CTRL_KEY_EXP); 2382 - 2383 - return CRYPTO_OK; 2384 - } 2385 - 2386 - int spacc_compute_xcbc_key(struct spacc_device *spacc, int mode_id, 2387 - int job_idx, const unsigned char *key, 2388 - int keylen, unsigned char *xcbc_out) 2389 - { 2390 - unsigned char *buf; 2391 - dma_addr_t bufphys; 2392 - struct pdu_ddt ddt; 2393 - unsigned char iv[16]; 2394 - int err, i, handle, usecbc, ctx_idx; 2395 - 2396 - if (job_idx >= 0 && job_idx < SPACC_MAX_JOBS) 2397 - ctx_idx = spacc->job[job_idx].ctx_idx; 2398 - else 2399 - ctx_idx = -1; 2400 - 2401 - if (mode_id == CRYPTO_MODE_MAC_XCBC) { 2402 - /* figure out if we can schedule the key */ 2403 - if (spacc_isenabled(spacc, CRYPTO_MODE_AES_ECB, 16)) 2404 - usecbc = 0; 2405 - else if (spacc_isenabled(spacc, CRYPTO_MODE_AES_CBC, 16)) 2406 - usecbc = 1; 2407 - else 2408 - return -1; 2409 - } else if (mode_id == CRYPTO_MODE_MAC_SM4_XCBC) { 2410 - /* figure out if we can schedule the key */ 2411 - if (spacc_isenabled(spacc, CRYPTO_MODE_SM4_ECB, 16)) 2412 - usecbc = 0; 2413 - else if (spacc_isenabled(spacc, CRYPTO_MODE_SM4_CBC, 16)) 2414 - usecbc = 1; 2415 - else 2416 - return -1; 2417 - } else { 2418 - return -1; 2419 - } 2420 - 2421 - memset(iv, 0, sizeof(iv)); 2422 - memset(&ddt, 0, sizeof(ddt)); 2423 - 2424 - buf = dma_alloc_coherent(get_ddt_device(), 64, &bufphys, GFP_KERNEL); 2425 - if (!buf) 2426 - return -EINVAL; 2427 - 2428 - handle = -1; 2429 - 2430 - /* set to 1111...., 2222...., 333... */ 2431 - for (i = 0; i < 48; i++) 2432 - buf[i] = (i >> 4) + 1; 2433 - 2434 - /* build DDT */ 2435 - err = pdu_ddt_init(&ddt, 1); 2436 - if (err) 2437 - goto xcbc_err; 2438 - 2439 - pdu_ddt_add(&ddt, bufphys, 48); 2440 - 2441 - /* open a handle in either CBC or ECB mode */ 2442 - if (mode_id == CRYPTO_MODE_MAC_XCBC) { 2443 - handle = spacc_open(spacc, (usecbc ? 2444 - CRYPTO_MODE_AES_CBC : CRYPTO_MODE_AES_ECB), 2445 - CRYPTO_MODE_NULL, ctx_idx, 0, NULL, NULL); 2446 - if (handle < 0) { 2447 - err = handle; 2448 - goto xcbc_err; 2449 - } 2450 - } else if (mode_id == CRYPTO_MODE_MAC_SM4_XCBC) { 2451 - handle = spacc_open(spacc, (usecbc ? 2452 - CRYPTO_MODE_SM4_CBC : CRYPTO_MODE_SM4_ECB), 2453 - CRYPTO_MODE_NULL, ctx_idx, 0, NULL, NULL); 2454 - if (handle < 0) { 2455 - err = handle; 2456 - goto xcbc_err; 2457 - } 2458 - } 2459 - spacc_set_operation(spacc, handle, OP_ENCRYPT, 0, 0, 0, 0, 0); 2460 - 2461 - if (usecbc) { 2462 - /* we can do the ECB work in CBC using three 2463 - * jobs with the IVreset to zero each time 2464 - */ 2465 - for (i = 0; i < 3; i++) { 2466 - spacc_write_context(spacc, handle, 2467 - SPACC_CRYPTO_OPERATION, key, 2468 - keylen, iv, 16); 2469 - err = spacc_packet_enqueue_ddt(spacc, handle, &ddt, 2470 - &ddt, 16, (i * 16) | 2471 - ((i * 16) << 16), 0, 0, 0, 0); 2472 - if (err != CRYPTO_OK) 2473 - goto xcbc_err; 2474 - 2475 - do { 2476 - err = spacc_packet_dequeue(spacc, handle); 2477 - } while (err == -EINPROGRESS); 2478 - if (err != CRYPTO_OK) 2479 - goto xcbc_err; 2480 - } 2481 - } else { 2482 - /* do the 48 bytes as a single SPAcc job this is the ideal case 2483 - * but only possible if ECB was enabled in the core 2484 - */ 2485 - spacc_write_context(spacc, handle, SPACC_CRYPTO_OPERATION, 2486 - key, keylen, iv, 16); 2487 - err = spacc_packet_enqueue_ddt(spacc, handle, &ddt, &ddt, 48, 2488 - 0, 0, 0, 0, 0); 2489 - if (err != CRYPTO_OK) 2490 - goto xcbc_err; 2491 - 2492 - do { 2493 - err = spacc_packet_dequeue(spacc, handle); 2494 - } while (err == -EINPROGRESS); 2495 - if (err != CRYPTO_OK) 2496 - goto xcbc_err; 2497 - } 2498 - 2499 - /* now we can copy the key*/ 2500 - memcpy(xcbc_out, buf, 48); 2501 - memset(buf, 0, 64); 2502 - 2503 - xcbc_err: 2504 - dma_free_coherent(get_ddt_device(), 64, buf, bufphys); 2505 - pdu_ddt_free(&ddt); 2506 - if (handle >= 0) 2507 - spacc_close(spacc, handle); 2508 - 2509 - if (err) 2510 - return -EINVAL; 2511 - 2512 - return 0; 2513 - }
-824
drivers/crypto/dwc-spacc/spacc_core.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - 3 - 4 - #ifndef SPACC_CORE_H_ 5 - #define SPACC_CORE_H_ 6 - 7 - #include <linux/interrupt.h> 8 - #include <linux/platform_device.h> 9 - #include <linux/of_device.h> 10 - #include <linux/dma-mapping.h> 11 - #include <crypto/skcipher.h> 12 - #include "spacc_hal.h" 13 - 14 - enum { 15 - SPACC_DMA_UNDEF = 0, 16 - SPACC_DMA_DDT = 1, 17 - SPACC_DMA_LINEAR = 2 18 - }; 19 - 20 - enum { 21 - SPACC_OP_MODE_IRQ = 0, 22 - SPACC_OP_MODE_WD = 1 /* watchdog */ 23 - }; 24 - 25 - #define OP_ENCRYPT 0 26 - #define OP_DECRYPT 1 27 - 28 - #define SPACC_CRYPTO_OPERATION 1 29 - #define SPACC_HASH_OPERATION 2 30 - 31 - #define SPACC_AADCOPY_FLAG 0x80000000 32 - 33 - #define SPACC_AUTO_SIZE (-1) 34 - 35 - #define SPACC_WD_LIMIT 0x80 36 - #define SPACC_WD_TIMER_INIT 0x40000 37 - 38 - /********* Register Offsets **********/ 39 - #define SPACC_REG_IRQ_EN 0x00000L 40 - #define SPACC_REG_IRQ_STAT 0x00004L 41 - #define SPACC_REG_IRQ_CTRL 0x00008L 42 - #define SPACC_REG_FIFO_STAT 0x0000CL 43 - #define SPACC_REG_SDMA_BRST_SZ 0x00010L 44 - 45 - #define SPACC_REG_SRC_PTR 0x00020L 46 - #define SPACC_REG_DST_PTR 0x00024L 47 - #define SPACC_REG_OFFSET 0x00028L 48 - #define SPACC_REG_PRE_AAD_LEN 0x0002CL 49 - #define SPACC_REG_POST_AAD_LEN 0x00030L 50 - 51 - #define SPACC_REG_PROC_LEN 0x00034L 52 - #define SPACC_REG_ICV_LEN 0x00038L 53 - #define SPACC_REG_ICV_OFFSET 0x0003CL 54 - #define SPACC_REG_IV_OFFSET 0x00040L 55 - 56 - #define SPACC_REG_SW_CTRL 0x00044L 57 - #define SPACC_REG_AUX_INFO 0x00048L 58 - #define SPACC_REG_CTRL 0x0004CL 59 - 60 - #define SPACC_REG_STAT_POP 0x00050L 61 - #define SPACC_REG_STATUS 0x00054L 62 - 63 - #define SPACC_REG_STAT_WD_CTRL 0x00080L 64 - 65 - #define SPACC_REG_KEY_SZ 0x00100L 66 - 67 - #define SPACC_REG_VIRTUAL_RQST 0x00140L 68 - #define SPACC_REG_VIRTUAL_ALLOC 0x00144L 69 - #define SPACC_REG_VIRTUAL_PRIO 0x00148L 70 - 71 - #define SPACC_REG_ID 0x00180L 72 - #define SPACC_REG_CONFIG 0x00184L 73 - #define SPACC_REG_CONFIG2 0x00190L 74 - 75 - #define SPACC_REG_SECURE_CTRL 0x001C0L 76 - #define SPACC_REG_SECURE_RELEASE 0x001C4 77 - 78 - #define SPACC_REG_SK_LOAD 0x00200L 79 - #define SPACC_REG_SK_STAT 0x00204L 80 - #define SPACC_REG_SK_KEY 0x00240L 81 - 82 - #define SPACC_REG_VERSION_EXT_3 0x00194L 83 - 84 - /* out 8MB from base of SPACC */ 85 - #define SPACC_REG_SKP 0x800000UL 86 - 87 - /********** Context Offsets **********/ 88 - #define SPACC_CTX_CIPH_KEY 0x04000L 89 - #define SPACC_CTX_HASH_KEY 0x08000L 90 - 91 - /******** Sub-Context Offsets ********/ 92 - #define SPACC_CTX_AES_KEY 0x00 93 - #define SPACC_CTX_AES_IV 0x20 94 - 95 - #define SPACC_CTX_DES_KEY 0x08 96 - #define SPACC_CTX_DES_IV 0x00 97 - 98 - /* use these to loop over CMDX macros */ 99 - #define SPACC_CMDX_MAX 1 100 - #define SPACC_CMDX_MAX_QOS 3 101 - /********** IRQ_EN Bit Masks **********/ 102 - 103 - #define _SPACC_IRQ_CMD0 0 104 - #define _SPACC_IRQ_STAT 4 105 - #define _SPACC_IRQ_STAT_WD 12 106 - #define _SPACC_IRQ_GLBL 31 107 - 108 - #define SPACC_IRQ_EN_CMD(x) (1UL << _SPACC_IRQ_CMD0 << (x)) 109 - #define SPACC_IRQ_EN_STAT BIT(_SPACC_IRQ_STAT) 110 - #define SPACC_IRQ_EN_STAT_WD BIT(_SPACC_IRQ_STAT_WD) 111 - #define SPACC_IRQ_EN_GLBL BIT(_SPACC_IRQ_GLBL) 112 - 113 - /********* IRQ_STAT Bitmasks *********/ 114 - 115 - #define SPACC_IRQ_STAT_CMDX(x) (1UL << _SPACC_IRQ_CMD0 << (x)) 116 - #define SPACC_IRQ_STAT_STAT BIT(_SPACC_IRQ_STAT) 117 - #define SPACC_IRQ_STAT_STAT_WD BIT(_SPACC_IRQ_STAT_WD) 118 - 119 - #define SPACC_IRQ_STAT_CLEAR_STAT(spacc) writel(SPACC_IRQ_STAT_STAT, \ 120 - (spacc)->regmap + SPACC_REG_IRQ_STAT) 121 - 122 - #define SPACC_IRQ_STAT_CLEAR_STAT_WD(spacc) writel(SPACC_IRQ_STAT_STAT_WD, \ 123 - (spacc)->regmap + SPACC_REG_IRQ_STAT) 124 - 125 - #define SPACC_IRQ_STAT_CLEAR_CMDX(spacc, x) writel(SPACC_IRQ_STAT_CMDX(x), \ 126 - (spacc)->regmap + SPACC_REG_IRQ_STAT) 127 - 128 - /********* IRQ_CTRL Bitmasks *********/ 129 - /* CMD0 = 0; for QOS, CMD1 = 8, CMD2 = 16 */ 130 - #define _SPACC_IRQ_CTRL_CMDX_CNT(x) (8 * (x)) 131 - #define SPACC_IRQ_CTRL_CMDX_CNT_SET(x, n) \ 132 - (((n) & 0xFF) << _SPACC_IRQ_CTRL_CMDX_CNT(x)) 133 - #define SPACC_IRQ_CTRL_CMDX_CNT_MASK(x) \ 134 - (0xFF << _SPACC_IRQ_CTRL_CMDX_CNT(x)) 135 - 136 - /* STAT_CNT is at 16 and for QOS at 24 */ 137 - #define _SPACC_IRQ_CTRL_STAT_CNT 16 138 - #define SPACC_IRQ_CTRL_STAT_CNT_SET(n) ((n) << _SPACC_IRQ_CTRL_STAT_CNT) 139 - #define SPACC_IRQ_CTRL_STAT_CNT_MASK (0x1FF << _SPACC_IRQ_CTRL_STAT_CNT) 140 - 141 - #define _SPACC_IRQ_CTRL_STAT_CNT_QOS 24 142 - #define SPACC_IRQ_CTRL_STAT_CNT_SET_QOS(n) \ 143 - ((n) << _SPACC_IRQ_CTRL_STAT_CNT_QOS) 144 - #define SPACC_IRQ_CTRL_STAT_CNT_MASK_QOS \ 145 - (0x7F << _SPACC_IRQ_CTRL_STAT_CNT_QOS) 146 - 147 - /******** FIFO_STAT Bitmasks *********/ 148 - 149 - /* SPACC with QOS */ 150 - #define SPACC_FIFO_STAT_CMDX_CNT_MASK(x) \ 151 - (0x7F << ((x) * 8)) 152 - #define SPACC_FIFO_STAT_CMDX_CNT_GET(x, y) \ 153 - (((y) & SPACC_FIFO_STAT_CMDX_CNT_MASK(x)) >> ((x) * 8)) 154 - #define SPACC_FIFO_STAT_CMDX_FULL(x) (1UL << (7 + (x) * 8)) 155 - 156 - #define _SPACC_FIFO_STAT_STAT_CNT_QOS 24 157 - #define SPACC_FIFO_STAT_STAT_CNT_MASK_QOS \ 158 - (0x7F << _SPACC_FIFO_STAT_STAT_CNT_QOS) 159 - #define SPACC_FIFO_STAT_STAT_CNT_GET_QOS(y) \ 160 - (((y) & \ 161 - SPACC_FIFO_STAT_STAT_CNT_MASK_QOS) >> _SPACC_FIFO_STAT_STAT_CNT_QOS) 162 - 163 - /* SPACC without QOS */ 164 - #define SPACC_FIFO_STAT_CMD0_CNT_MASK (0x1FF) 165 - #define SPACC_FIFO_STAT_CMD0_CNT_GET(y) ((y) & SPACC_FIFO_STAT_CMD0_CNT_MASK) 166 - #define _SPACC_FIFO_STAT_CMD0_FULL 15 167 - #define SPACC_FIFO_STAT_CMD0_FULL BIT(_SPACC_FIFO_STAT_CMD0_FULL) 168 - 169 - #define _SPACC_FIFO_STAT_STAT_CNT 16 170 - #define SPACC_FIFO_STAT_STAT_CNT_MASK (0x1FF << _SPACC_FIFO_STAT_STAT_CNT) 171 - #define SPACC_FIFO_STAT_STAT_CNT_GET(y) \ 172 - (((y) & SPACC_FIFO_STAT_STAT_CNT_MASK) >> _SPACC_FIFO_STAT_STAT_CNT) 173 - 174 - /* both */ 175 - #define _SPACC_FIFO_STAT_STAT_EMPTY 31 176 - #define SPACC_FIFO_STAT_STAT_EMPTY BIT(_SPACC_FIFO_STAT_STAT_EMPTY) 177 - 178 - /********* SRC/DST_PTR Bitmasks **********/ 179 - 180 - #define SPACC_SRC_PTR_PTR 0xFFFFFFF8 181 - #define SPACC_DST_PTR_PTR 0xFFFFFFF8 182 - 183 - /********** OFFSET Bitmasks **********/ 184 - 185 - #define SPACC_OFFSET_SRC_O 0 186 - #define SPACC_OFFSET_SRC_W 16 187 - #define SPACC_OFFSET_DST_O 16 188 - #define SPACC_OFFSET_DST_W 16 189 - 190 - #define SPACC_MIN_CHUNK_SIZE 1024 191 - #define SPACC_MAX_CHUNK_SIZE 16384 192 - 193 - /********* PKT_LEN Bitmasks **********/ 194 - 195 - #ifndef _SPACC_PKT_LEN_PROC_LEN 196 - #define _SPACC_PKT_LEN_PROC_LEN 0 197 - #endif 198 - #ifndef _SPACC_PKT_LEN_AAD_LEN 199 - #define _SPACC_PKT_LEN_AAD_LEN 16 200 - #endif 201 - 202 - /********* SW_CTRL Bitmasks ***********/ 203 - 204 - #define _SPACC_SW_CTRL_ID_0 0 205 - #define SPACC_SW_CTRL_ID_W 8 206 - #define SPACC_SW_CTRL_ID_MASK (0xFF << _SPACC_SW_CTRL_ID_0) 207 - #define SPACC_SW_CTRL_ID_GET(y) \ 208 - (((y) & SPACC_SW_CTRL_ID_MASK) >> _SPACC_SW_CTRL_ID_0) 209 - #define SPACC_SW_CTRL_ID_SET(id) \ 210 - (((id) & SPACC_SW_CTRL_ID_MASK) >> _SPACC_SW_CTRL_ID_0) 211 - 212 - #define _SPACC_SW_CTRL_PRIO 30 213 - #define SPACC_SW_CTRL_PRIO_MASK 0x3 214 - #define SPACC_SW_CTRL_PRIO_SET(prio) \ 215 - (((prio) & SPACC_SW_CTRL_PRIO_MASK) << _SPACC_SW_CTRL_PRIO) 216 - 217 - /* Priorities */ 218 - #define SPACC_SW_CTRL_PRIO_HI 0 219 - #define SPACC_SW_CTRL_PRIO_MED 1 220 - #define SPACC_SW_CTRL_PRIO_LOW 2 221 - 222 - /*********** SECURE_CTRL bitmasks *********/ 223 - #define _SPACC_SECURE_CTRL_MS_SRC 0 224 - #define _SPACC_SECURE_CTRL_MS_DST 1 225 - #define _SPACC_SECURE_CTRL_MS_DDT 2 226 - #define _SPACC_SECURE_CTRL_LOCK 31 227 - 228 - #define SPACC_SECURE_CTRL_MS_SRC BIT(_SPACC_SECURE_CTRL_MS_SRC) 229 - #define SPACC_SECURE_CTRL_MS_DST BIT(_SPACC_SECURE_CTRL_MS_DST) 230 - #define SPACC_SECURE_CTRL_MS_DDT BIT(_SPACC_SECURE_CTRL_MS_DDT) 231 - #define SPACC_SECURE_CTRL_LOCK BIT(_SPACC_SECURE_CTRL_LOCK) 232 - 233 - /********* SKP bits **************/ 234 - #define _SPACC_SK_LOAD_CTX_IDX 0 235 - #define _SPACC_SK_LOAD_ALG 8 236 - #define _SPACC_SK_LOAD_MODE 12 237 - #define _SPACC_SK_LOAD_SIZE 16 238 - #define _SPACC_SK_LOAD_ENC_EN 30 239 - #define _SPACC_SK_LOAD_DEC_EN 31 240 - #define _SPACC_SK_STAT_BUSY 0 241 - 242 - #define SPACC_SK_LOAD_ENC_EN BIT(_SPACC_SK_LOAD_ENC_EN) 243 - #define SPACC_SK_LOAD_DEC_EN BIT(_SPACC_SK_LOAD_DEC_EN) 244 - #define SPACC_SK_STAT_BUSY BIT(_SPACC_SK_STAT_BUSY) 245 - 246 - /*********** CTRL Bitmasks ***********/ 247 - /* These CTRL field locations vary with SPACC version 248 - * and if they are used, they should be set accordingly 249 - */ 250 - #define _SPACC_CTRL_CIPH_ALG 0 251 - #define _SPACC_CTRL_HASH_ALG 4 252 - #define _SPACC_CTRL_CIPH_MODE 8 253 - #define _SPACC_CTRL_HASH_MODE 12 254 - #define _SPACC_CTRL_MSG_BEGIN 14 255 - #define _SPACC_CTRL_MSG_END 15 256 - #define _SPACC_CTRL_CTX_IDX 16 257 - #define _SPACC_CTRL_ENCRYPT 24 258 - #define _SPACC_CTRL_AAD_COPY 25 259 - #define _SPACC_CTRL_ICV_PT 26 260 - #define _SPACC_CTRL_ICV_ENC 27 261 - #define _SPACC_CTRL_ICV_APPEND 28 262 - #define _SPACC_CTRL_KEY_EXP 29 263 - #define _SPACC_CTRL_SEC_KEY 31 264 - 265 - /* CTRL bitmasks for 4.15+ cores */ 266 - #define _SPACC_CTRL_CIPH_ALG_415 0 267 - #define _SPACC_CTRL_HASH_ALG_415 3 268 - #define _SPACC_CTRL_CIPH_MODE_415 8 269 - #define _SPACC_CTRL_HASH_MODE_415 12 270 - 271 - /********* Virtual Spacc Priority Bitmasks **********/ 272 - #define _SPACC_VPRIO_MODE 0 273 - #define _SPACC_VPRIO_WEIGHT 8 274 - 275 - /********* AUX INFO Bitmasks *********/ 276 - #define _SPACC_AUX_INFO_DIR 0 277 - #define _SPACC_AUX_INFO_BIT_ALIGN 1 278 - #define _SPACC_AUX_INFO_CBC_CS 16 279 - 280 - /********* STAT_POP Bitmasks *********/ 281 - #define _SPACC_STAT_POP_POP 0 282 - #define SPACC_STAT_POP_POP BIT(_SPACC_STAT_POP_POP) 283 - 284 - /********** STATUS Bitmasks **********/ 285 - #define _SPACC_STATUS_SW_ID 0 286 - #define _SPACC_STATUS_RET_CODE 24 287 - #define _SPACC_STATUS_SEC_CMD 31 288 - #define SPACC_GET_STATUS_RET_CODE(s) \ 289 - (((s) >> _SPACC_STATUS_RET_CODE) & 0x7) 290 - 291 - #define SPACC_STATUS_SW_ID_MASK (0xFF << _SPACC_STATUS_SW_ID) 292 - #define SPACC_STATUS_SW_ID_GET(y) \ 293 - (((y) & SPACC_STATUS_SW_ID_MASK) >> _SPACC_STATUS_SW_ID) 294 - 295 - /********** KEY_SZ Bitmasks **********/ 296 - #define _SPACC_KEY_SZ_SIZE 0 297 - #define _SPACC_KEY_SZ_CTX_IDX 8 298 - #define _SPACC_KEY_SZ_CIPHER 31 299 - 300 - #define SPACC_KEY_SZ_CIPHER BIT(_SPACC_KEY_SZ_CIPHER) 301 - 302 - #define SPACC_SET_CIPHER_KEY_SZ(z) \ 303 - (((z) << _SPACC_KEY_SZ_SIZE) | (1UL << _SPACC_KEY_SZ_CIPHER)) 304 - #define SPACC_SET_HASH_KEY_SZ(z) ((z) << _SPACC_KEY_SZ_SIZE) 305 - #define SPACC_SET_KEY_CTX(ctx) ((ctx) << _SPACC_KEY_SZ_CTX_IDX) 306 - 307 - /*****************************************************************************/ 308 - 309 - #define AUX_DIR(a) ((a) << _SPACC_AUX_INFO_DIR) 310 - #define AUX_BIT_ALIGN(a) ((a) << _SPACC_AUX_INFO_BIT_ALIGN) 311 - #define AUX_CBC_CS(a) ((a) << _SPACC_AUX_INFO_CBC_CS) 312 - 313 - #define VPRIO_SET(mode, weight) \ 314 - (((mode) << _SPACC_VPRIO_MODE) | ((weight) << _SPACC_VPRIO_WEIGHT)) 315 - 316 - #ifndef MAX_DDT_ENTRIES 317 - /* add one for null at end of list */ 318 - #define MAX_DDT_ENTRIES \ 319 - ((SPACC_MAX_MSG_MALLOC_SIZE / SPACC_MAX_PARTICLE_SIZE) + 1) 320 - #endif 321 - 322 - #define DDT_ENTRY_SIZE (sizeof(ddt_entry) * MAX_DDT_ENTRIES) 323 - 324 - #ifndef SPACC_MAX_JOBS 325 - #define SPACC_MAX_JOBS BIT(SPACC_SW_CTRL_ID_W) 326 - #endif 327 - 328 - #if SPACC_MAX_JOBS > 256 329 - # error SPACC_MAX_JOBS cannot exceed 256. 330 - #endif 331 - 332 - #ifndef SPACC_MAX_JOB_BUFFERS 333 - #define SPACC_MAX_JOB_BUFFERS 192 334 - #endif 335 - 336 - /* max DDT particle size */ 337 - #ifndef SPACC_MAX_PARTICLE_SIZE 338 - #define SPACC_MAX_PARTICLE_SIZE 4096 339 - #endif 340 - 341 - /* max message size from HW configuration */ 342 - /* usually defined in ICD as (2 exponent 16) -1 */ 343 - #ifndef _SPACC_MAX_MSG_MALLOC_SIZE 344 - #define _SPACC_MAX_MSG_MALLOC_SIZE 16 345 - #endif 346 - #define SPACC_MAX_MSG_MALLOC_SIZE BIT(_SPACC_MAX_MSG_MALLOC_SIZE) 347 - 348 - #ifndef SPACC_MAX_MSG_SIZE 349 - #define SPACC_MAX_MSG_SIZE (SPACC_MAX_MSG_MALLOC_SIZE - 1) 350 - #endif 351 - 352 - #define SPACC_LOOP_WAIT 1000000 353 - #define SPACC_CTR_IV_MAX8 ((u32)0xFF) 354 - #define SPACC_CTR_IV_MAX16 ((u32)0xFFFF) 355 - #define SPACC_CTR_IV_MAX32 ((u32)0xFFFFFFFF) 356 - #define SPACC_CTR_IV_MAX64 ((u64)0xFFFFFFFFFFFFFFFF) 357 - 358 - /* cipher algos */ 359 - enum ecipher { 360 - C_NULL = 0, 361 - C_DES = 1, 362 - C_AES = 2, 363 - C_RC4 = 3, 364 - C_MULTI2 = 4, 365 - C_KASUMI = 5, 366 - C_SNOW3G_UEA2 = 6, 367 - C_ZUC_UEA3 = 7, 368 - C_CHACHA20 = 8, 369 - C_SM4 = 9, 370 - C_MAX = 10 371 - }; 372 - 373 - /* ctrl reg cipher modes */ 374 - enum eciphermode { 375 - CM_ECB = 0, 376 - CM_CBC = 1, 377 - CM_CTR = 2, 378 - CM_CCM = 3, 379 - CM_GCM = 5, 380 - CM_OFB = 7, 381 - CM_CFB = 8, 382 - CM_F8 = 9, 383 - CM_XTS = 10, 384 - CM_MAX = 11 385 - }; 386 - 387 - enum echachaciphermode { 388 - CM_CHACHA_STREAM = 2, 389 - CM_CHACHA_AEAD = 5 390 - }; 391 - 392 - enum ehash { 393 - H_NULL = 0, 394 - H_MD5 = 1, 395 - H_SHA1 = 2, 396 - H_SHA224 = 3, 397 - H_SHA256 = 4, 398 - H_SHA384 = 5, 399 - H_SHA512 = 6, 400 - H_XCBC = 7, 401 - H_CMAC = 8, 402 - H_KF9 = 9, 403 - H_SNOW3G_UIA2 = 10, 404 - H_CRC32_I3E802_3 = 11, 405 - H_ZUC_UIA3 = 12, 406 - H_SHA512_224 = 13, 407 - H_SHA512_256 = 14, 408 - H_MICHAEL = 15, 409 - H_SHA3_224 = 16, 410 - H_SHA3_256 = 17, 411 - H_SHA3_384 = 18, 412 - H_SHA3_512 = 19, 413 - H_SHAKE128 = 20, 414 - H_SHAKE256 = 21, 415 - H_POLY1305 = 22, 416 - H_SM3 = 23, 417 - H_SM4_XCBC_MAC = 24, 418 - H_SM4_CMAC = 25, 419 - H_MAX = 26 420 - }; 421 - 422 - enum ehashmode { 423 - HM_RAW = 0, 424 - HM_SSLMAC = 1, 425 - HM_HMAC = 2, 426 - HM_MAX = 3 427 - }; 428 - 429 - enum eshakehashmode { 430 - HM_SHAKE_SHAKE = 0, 431 - HM_SHAKE_CSHAKE = 1, 432 - HM_SHAKE_KMAC = 2 433 - }; 434 - 435 - enum spacc_ret_code { 436 - SPACC_OK = 0, 437 - SPACC_ICVFAIL = 1, 438 - SPACC_MEMERR = 2, 439 - SPACC_BLOCKERR = 3, 440 - SPACC_SECERR = 4 441 - }; 442 - 443 - enum eicvpos { 444 - IP_ICV_OFFSET = 0, 445 - IP_ICV_APPEND = 1, 446 - IP_ICV_IGNORE = 2, 447 - IP_MAX = 3 448 - }; 449 - 450 - enum { 451 - /* HASH of plaintext */ 452 - ICV_HASH = 0, 453 - /* HASH the plaintext and encrypt the plaintext and ICV */ 454 - ICV_HASH_ENCRYPT = 1, 455 - /* HASH the ciphertext */ 456 - ICV_ENCRYPT_HASH = 2, 457 - ICV_IGNORE = 3, 458 - IM_MAX = 4 459 - }; 460 - 461 - enum { 462 - NO_PARTIAL_PCK = 0, 463 - FIRST_PARTIAL_PCK = 1, 464 - MIDDLE_PARTIAL_PCK = 2, 465 - LAST_PARTIAL_PCK = 3 466 - }; 467 - 468 - enum crypto_modes { 469 - CRYPTO_MODE_NULL, 470 - CRYPTO_MODE_AES_ECB, 471 - CRYPTO_MODE_AES_CBC, 472 - CRYPTO_MODE_AES_CTR, 473 - CRYPTO_MODE_AES_CCM, 474 - CRYPTO_MODE_AES_GCM, 475 - CRYPTO_MODE_AES_F8, 476 - CRYPTO_MODE_AES_XTS, 477 - CRYPTO_MODE_AES_CFB, 478 - CRYPTO_MODE_AES_OFB, 479 - CRYPTO_MODE_AES_CS1, 480 - CRYPTO_MODE_AES_CS2, 481 - CRYPTO_MODE_AES_CS3, 482 - CRYPTO_MODE_MULTI2_ECB, 483 - CRYPTO_MODE_MULTI2_CBC, 484 - CRYPTO_MODE_MULTI2_OFB, 485 - CRYPTO_MODE_MULTI2_CFB, 486 - CRYPTO_MODE_3DES_CBC, 487 - CRYPTO_MODE_3DES_ECB, 488 - CRYPTO_MODE_DES_CBC, 489 - CRYPTO_MODE_DES_ECB, 490 - CRYPTO_MODE_KASUMI_ECB, 491 - CRYPTO_MODE_KASUMI_F8, 492 - CRYPTO_MODE_SNOW3G_UEA2, 493 - CRYPTO_MODE_ZUC_UEA3, 494 - CRYPTO_MODE_CHACHA20_STREAM, 495 - CRYPTO_MODE_CHACHA20_POLY1305, 496 - CRYPTO_MODE_SM4_ECB, 497 - CRYPTO_MODE_SM4_CBC, 498 - CRYPTO_MODE_SM4_CFB, 499 - CRYPTO_MODE_SM4_OFB, 500 - CRYPTO_MODE_SM4_CTR, 501 - CRYPTO_MODE_SM4_CCM, 502 - CRYPTO_MODE_SM4_GCM, 503 - CRYPTO_MODE_SM4_F8, 504 - CRYPTO_MODE_SM4_XTS, 505 - CRYPTO_MODE_SM4_CS1, 506 - CRYPTO_MODE_SM4_CS2, 507 - CRYPTO_MODE_SM4_CS3, 508 - 509 - CRYPTO_MODE_HASH_MD5, 510 - CRYPTO_MODE_HMAC_MD5, 511 - CRYPTO_MODE_HASH_SHA1, 512 - CRYPTO_MODE_HMAC_SHA1, 513 - CRYPTO_MODE_HASH_SHA224, 514 - CRYPTO_MODE_HMAC_SHA224, 515 - CRYPTO_MODE_HASH_SHA256, 516 - CRYPTO_MODE_HMAC_SHA256, 517 - CRYPTO_MODE_HASH_SHA384, 518 - CRYPTO_MODE_HMAC_SHA384, 519 - CRYPTO_MODE_HASH_SHA512, 520 - CRYPTO_MODE_HMAC_SHA512, 521 - CRYPTO_MODE_HASH_SHA512_224, 522 - CRYPTO_MODE_HMAC_SHA512_224, 523 - CRYPTO_MODE_HASH_SHA512_256, 524 - CRYPTO_MODE_HMAC_SHA512_256, 525 - 526 - CRYPTO_MODE_MAC_XCBC, 527 - CRYPTO_MODE_MAC_CMAC, 528 - CRYPTO_MODE_MAC_KASUMI_F9, 529 - CRYPTO_MODE_MAC_SNOW3G_UIA2, 530 - CRYPTO_MODE_MAC_ZUC_UIA3, 531 - CRYPTO_MODE_MAC_POLY1305, 532 - 533 - CRYPTO_MODE_SSLMAC_MD5, 534 - CRYPTO_MODE_SSLMAC_SHA1, 535 - CRYPTO_MODE_HASH_CRC32, 536 - CRYPTO_MODE_MAC_MICHAEL, 537 - 538 - CRYPTO_MODE_HASH_SHA3_224, 539 - CRYPTO_MODE_HASH_SHA3_256, 540 - CRYPTO_MODE_HASH_SHA3_384, 541 - CRYPTO_MODE_HASH_SHA3_512, 542 - 543 - CRYPTO_MODE_HASH_SHAKE128, 544 - CRYPTO_MODE_HASH_SHAKE256, 545 - CRYPTO_MODE_HASH_CSHAKE128, 546 - CRYPTO_MODE_HASH_CSHAKE256, 547 - CRYPTO_MODE_MAC_KMAC128, 548 - CRYPTO_MODE_MAC_KMAC256, 549 - CRYPTO_MODE_MAC_KMACXOF128, 550 - CRYPTO_MODE_MAC_KMACXOF256, 551 - 552 - CRYPTO_MODE_HASH_SM3, 553 - CRYPTO_MODE_HMAC_SM3, 554 - CRYPTO_MODE_MAC_SM4_XCBC, 555 - CRYPTO_MODE_MAC_SM4_CMAC, 556 - 557 - CRYPTO_MODE_LAST 558 - }; 559 - 560 - /* job descriptor */ 561 - typedef void (*spacc_callback)(void *spacc_dev, void *data); 562 - 563 - struct spacc_job { 564 - unsigned long 565 - enc_mode, /* Encryption Algorithm mode */ 566 - hash_mode, /* HASH Algorithm mode */ 567 - icv_len, 568 - icv_offset, 569 - op, /* Operation */ 570 - ctrl, /* CTRL shadow register */ 571 - 572 - /* context just initialized or taken, 573 - * and this is the first use. 574 - */ 575 - first_use, 576 - pre_aad_sz, post_aad_sz, /* size of AAD for the latest packet*/ 577 - hkey_sz, 578 - ckey_sz; 579 - 580 - /* Direction and bit alignment parameters for the AUX_INFO reg */ 581 - unsigned int auxinfo_dir, auxinfo_bit_align; 582 - unsigned int auxinfo_cs_mode; /* AUX info setting for CBC-CS */ 583 - 584 - u32 ctx_idx; 585 - unsigned int job_used, job_swid, job_done, job_err, job_secure; 586 - spacc_callback cb; 587 - void *cbdata; 588 - 589 - }; 590 - 591 - #define SPACC_CTX_IDX_UNUSED 0xFFFFFFFF 592 - #define SPACC_JOB_IDX_UNUSED 0xFFFFFFFF 593 - 594 - struct spacc_ctx { 595 - /* Memory context to store cipher keys*/ 596 - void __iomem *ciph_key; 597 - /* Memory context to store hash keys*/ 598 - void __iomem *hash_key; 599 - /* reference count of jobs using this context */ 600 - int ref_cnt; 601 - /* number of contexts following related to this one */ 602 - int ncontig; 603 - }; 604 - 605 - #define SPACC_CTRL_MASK(field) \ 606 - (1UL << spacc->config.ctrl_map[(field)]) 607 - #define SPACC_CTRL_SET(field, value) \ 608 - ((value) << spacc->config.ctrl_map[(field)]) 609 - 610 - enum { 611 - SPACC_CTRL_VER_0, 612 - SPACC_CTRL_VER_1, 613 - SPACC_CTRL_VER_2, 614 - SPACC_CTRL_VER_SIZE 615 - }; 616 - 617 - enum { 618 - SPACC_CTRL_CIPH_ALG, 619 - SPACC_CTRL_CIPH_MODE, 620 - SPACC_CTRL_HASH_ALG, 621 - SPACC_CTRL_HASH_MODE, 622 - SPACC_CTRL_ENCRYPT, 623 - SPACC_CTRL_CTX_IDX, 624 - SPACC_CTRL_SEC_KEY, 625 - SPACC_CTRL_AAD_COPY, 626 - SPACC_CTRL_ICV_PT, 627 - SPACC_CTRL_ICV_ENC, 628 - SPACC_CTRL_ICV_APPEND, 629 - SPACC_CTRL_KEY_EXP, 630 - SPACC_CTRL_MSG_BEGIN, 631 - SPACC_CTRL_MSG_END, 632 - SPACC_CTRL_MAPSIZE 633 - }; 634 - 635 - struct spacc_device { 636 - void __iomem *regmap; 637 - int zero_key; 638 - 639 - /* hardware configuration */ 640 - struct { 641 - unsigned int version, 642 - pdu_version, 643 - project; 644 - uint32_t max_msg_size; /* max PROCLEN value */ 645 - 646 - unsigned char modes[CRYPTO_MODE_LAST]; 647 - 648 - int num_ctx, /* no. of contexts */ 649 - num_sec_ctx, /* no. of SKP contexts*/ 650 - sec_ctx_page_size, /* page size of SKP context in bytes*/ 651 - ciph_page_size, /* cipher context page size in bytes*/ 652 - hash_page_size, /* hash context page size in bytes*/ 653 - string_size, 654 - is_qos, /* QOS spacc? */ 655 - is_pdu, /* PDU spacc? */ 656 - is_secure, 657 - is_secure_port, /* Are we on the secure port? */ 658 - is_partial, /* Is partial processing enabled? */ 659 - is_ivimport, /* is ivimport enabled? */ 660 - dma_type, /* DMA type: linear or scattergather */ 661 - idx, /* Which virtual spacc IDX is this? */ 662 - priority, /* Weighted priority of virtual spacc */ 663 - cmd0_fifo_depth, /* CMD FIFO depths */ 664 - cmd1_fifo_depth, 665 - cmd2_fifo_depth, 666 - stat_fifo_depth, /* depth of STATUS FIFO */ 667 - fifo_cnt, 668 - ideal_stat_level, 669 - spacc_endian; 670 - 671 - uint32_t wd_timer; 672 - u64 oldtimer, timer; 673 - 674 - const u8 *ctrl_map; /* map of ctrl register field offsets */ 675 - } config; 676 - 677 - struct spacc_job_buffer { 678 - int active; 679 - int job_idx; 680 - struct pdu_ddt *src, *dst; 681 - u32 proc_sz, aad_offset, pre_aad_sz, 682 - post_aad_sz, iv_offset, prio; 683 - } job_buffer[SPACC_MAX_JOB_BUFFERS]; 684 - 685 - int jb_head, jb_tail; 686 - 687 - int op_mode, /* operating mode and watchdog functionality */ 688 - wdcnt; /* number of pending WD IRQs*/ 689 - 690 - /* SW_ID value which will be used for next job. */ 691 - unsigned int job_next_swid; 692 - 693 - struct spacc_ctx *ctx; /* This size changes per configured device */ 694 - struct spacc_job *job; /* allocate memory for [SPACC_MAX_JOBS]; */ 695 - int job_lookup[SPACC_MAX_JOBS]; /* correlate SW_ID back to job index */ 696 - 697 - spinlock_t lock; /* lock for register access */ 698 - spinlock_t ctx_lock; /* lock for context manager */ 699 - 700 - /* callback functions for IRQ processing */ 701 - void (*irq_cb_cmdx)(struct spacc_device *spacc, int x); 702 - void (*irq_cb_stat)(struct spacc_device *spacc); 703 - void (*irq_cb_stat_wd)(struct spacc_device *spacc); 704 - 705 - /* this is called after jobs have been popped off the STATUS FIFO 706 - * useful so you can be told when there might be space available 707 - * in the CMD FIFO 708 - */ 709 - void (*spacc_notify_jobs)(struct spacc_device *spacc); 710 - 711 - /* cache*/ 712 - struct { 713 - u32 src_ptr, 714 - dst_ptr, 715 - proc_len, 716 - icv_len, 717 - icv_offset, 718 - pre_aad, 719 - post_aad, 720 - iv_offset, 721 - offset, 722 - aux; 723 - } cache; 724 - 725 - struct device *dptr; 726 - }; 727 - 728 - enum { 729 - SPACC_IRQ_MODE_WD = 1, /* use WD*/ 730 - SPACC_IRQ_MODE_STEP = 2 /* older use CMD/STAT stepping */ 731 - }; 732 - 733 - enum { 734 - SPACC_IRQ_CMD_GET = 0, 735 - SPACC_IRQ_CMD_SET = 1 736 - }; 737 - 738 - struct spacc_priv { 739 - struct spacc_device spacc; 740 - struct semaphore core_running; 741 - struct tasklet_struct pop_jobs; 742 - spinlock_t hw_lock; 743 - unsigned long max_msg_len; 744 - }; 745 - 746 - 747 - int spacc_open(struct spacc_device *spacc, int enc, int hash, int ctx, 748 - int secure_mode, spacc_callback cb, void *cbdata); 749 - int spacc_clone_handle(struct spacc_device *spacc, int old_handle, 750 - void *cbdata); 751 - int spacc_close(struct spacc_device *spacc, int job_idx); 752 - int spacc_set_operation(struct spacc_device *spacc, int job_idx, int op, 753 - u32 prot, uint32_t icvcmd, uint32_t icvoff, 754 - uint32_t icvsz, uint32_t sec_key); 755 - int spacc_set_key_exp(struct spacc_device *spacc, int job_idx); 756 - 757 - int spacc_packet_enqueue_ddt_ex(struct spacc_device *spacc, int use_jb, 758 - int job_idx, struct pdu_ddt *src_ddt, struct pdu_ddt *dst_ddt, 759 - u32 proc_sz, uint32_t aad_offset, uint32_t pre_aad_sz, 760 - u32 post_aad_sz, uint32_t iv_offset, uint32_t prio); 761 - int spacc_packet_enqueue_ddt(struct spacc_device *spacc, int job_idx, 762 - struct pdu_ddt *src_ddt, struct pdu_ddt *dst_ddt, 763 - uint32_t proc_sz, u32 aad_offset, uint32_t pre_aad_sz, 764 - uint32_t post_aad_sz, u32 iv_offset, uint32_t prio); 765 - 766 - /* IRQ handling functions */ 767 - void spacc_irq_cmdx_enable(struct spacc_device *spacc, int cmdx, int cmdx_cnt); 768 - void spacc_irq_cmdx_disable(struct spacc_device *spacc, int cmdx); 769 - void spacc_irq_stat_enable(struct spacc_device *spacc, int stat_cnt); 770 - void spacc_irq_stat_disable(struct spacc_device *spacc); 771 - void spacc_irq_stat_wd_enable(struct spacc_device *spacc); 772 - void spacc_irq_stat_wd_disable(struct spacc_device *spacc); 773 - void spacc_irq_glbl_enable(struct spacc_device *spacc); 774 - void spacc_irq_glbl_disable(struct spacc_device *spacc); 775 - uint32_t spacc_process_irq(struct spacc_device *spacc); 776 - void spacc_set_wd_count(struct spacc_device *spacc, uint32_t val); 777 - irqreturn_t spacc_irq_handler(int irq, void *dev); 778 - int spacc_sgs_to_ddt(struct device *dev, 779 - struct scatterlist *sg1, int len1, int *ents1, 780 - struct scatterlist *sg2, int len2, int *ents2, 781 - struct scatterlist *sg3, int len3, int *ents3, 782 - struct pdu_ddt *ddt, int dma_direction); 783 - int spacc_sg_to_ddt(struct device *dev, struct scatterlist *sg, 784 - int nbytes, struct pdu_ddt *ddt, int dma_direction); 785 - 786 - /* Context Manager */ 787 - void spacc_ctx_init_all(struct spacc_device *spacc); 788 - 789 - /* SPAcc specific manipulation of context memory */ 790 - int spacc_write_context(struct spacc_device *spacc, int job_idx, int op, 791 - const unsigned char *key, int ksz, 792 - const unsigned char *iv, int ivsz); 793 - 794 - int spacc_read_context(struct spacc_device *spacc, int job_idx, int op, 795 - unsigned char *key, int ksz, unsigned char *iv, 796 - int ivsz); 797 - 798 - /* Job Manager */ 799 - void spacc_job_init_all(struct spacc_device *spacc); 800 - int spacc_job_request(struct spacc_device *dev, int job_idx); 801 - int spacc_job_release(struct spacc_device *dev, int job_idx); 802 - int spacc_handle_release(struct spacc_device *spacc, int job_idx); 803 - 804 - /* Helper functions */ 805 - struct spacc_ctx *context_lookup_by_job(struct spacc_device *spacc, 806 - int job_idx); 807 - int spacc_isenabled(struct spacc_device *spacc, int mode, int keysize); 808 - int spacc_compute_xcbc_key(struct spacc_device *spacc, int mode_id, 809 - int job_idx, const unsigned char *key, 810 - int keylen, unsigned char *xcbc_out); 811 - 812 - int spacc_process_jb(struct spacc_device *spacc); 813 - int spacc_remove(struct platform_device *pdev); 814 - int spacc_static_config(struct spacc_device *spacc); 815 - int spacc_autodetect(struct spacc_device *spacc); 816 - void spacc_pop_jobs(unsigned long data); 817 - void spacc_fini(struct spacc_device *spacc); 818 - int spacc_init(void __iomem *baseaddr, struct spacc_device *spacc, 819 - struct pdu_info *info); 820 - int spacc_pop_packets(struct spacc_device *spacc, int *num_popped); 821 - void spacc_stat_process(struct spacc_device *spacc); 822 - void spacc_cmd_process(struct spacc_device *spacc, int x); 823 - 824 - #endif
-338
drivers/crypto/dwc-spacc/spacc_device.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - 3 - #include <linux/of_device.h> 4 - #include <linux/module.h> 5 - #include <linux/dma-mapping.h> 6 - #include <linux/platform_device.h> 7 - #include "spacc_device.h" 8 - 9 - static struct platform_device *spacc_pdev[MAX_DEVICES]; 10 - 11 - #define VSPACC_PRIORITY_MAX 15 12 - 13 - void spacc_cmd_process(struct spacc_device *spacc, int x) 14 - { 15 - struct spacc_priv *priv = container_of(spacc, struct spacc_priv, spacc); 16 - 17 - /* run tasklet to pop jobs off fifo */ 18 - tasklet_schedule(&priv->pop_jobs); 19 - } 20 - void spacc_stat_process(struct spacc_device *spacc) 21 - { 22 - struct spacc_priv *priv = container_of(spacc, struct spacc_priv, spacc); 23 - 24 - /* run tasklet to pop jobs off fifo */ 25 - tasklet_schedule(&priv->pop_jobs); 26 - } 27 - 28 - 29 - int spacc_probe(struct platform_device *pdev, 30 - const struct of_device_id snps_spacc_id[]) 31 - { 32 - int spacc_idx = -1; 33 - struct resource *mem; 34 - int spacc_endian = 0; 35 - void __iomem *baseaddr; 36 - struct pdu_info info; 37 - int spacc_priority = -1; 38 - struct spacc_priv *priv; 39 - int x = 0, err, oldmode, irq_num; 40 - const struct of_device_id *match, *id; 41 - u64 oldtimer = 100000, timer = 100000; 42 - 43 - if (pdev->dev.of_node) { 44 - id = of_match_node(snps_spacc_id, pdev->dev.of_node); 45 - if (!id) { 46 - dev_err(&pdev->dev, "DT node did not match\n"); 47 - return -EINVAL; 48 - } 49 - } 50 - 51 - /* Initialize DDT DMA pools based on this device's resources */ 52 - if (pdu_mem_init(&pdev->dev)) { 53 - dev_err(&pdev->dev, "Could not initialize DMA pools\n"); 54 - return -ENOMEM; 55 - } 56 - 57 - match = of_match_device(of_match_ptr(snps_spacc_id), &pdev->dev); 58 - if (!match) { 59 - dev_err(&pdev->dev, "SPAcc dtb missing"); 60 - return -ENODEV; 61 - } 62 - 63 - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 64 - if (!mem) { 65 - dev_err(&pdev->dev, "no memory resource for spacc\n"); 66 - err = -ENXIO; 67 - goto free_ddt_mem_pool; 68 - } 69 - 70 - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 71 - if (!priv) { 72 - err = -ENOMEM; 73 - goto free_ddt_mem_pool; 74 - } 75 - 76 - /* Read spacc priority and index and save inside priv.spacc.config */ 77 - if (of_property_read_u32(pdev->dev.of_node, "spacc_priority", 78 - &spacc_priority)) { 79 - dev_err(&pdev->dev, "No vspacc priority specified\n"); 80 - err = -EINVAL; 81 - goto free_ddt_mem_pool; 82 - } 83 - 84 - if (spacc_priority < 0 && spacc_priority > VSPACC_PRIORITY_MAX) { 85 - dev_err(&pdev->dev, "Invalid vspacc priority\n"); 86 - err = -EINVAL; 87 - goto free_ddt_mem_pool; 88 - } 89 - priv->spacc.config.priority = spacc_priority; 90 - 91 - if (of_property_read_u32(pdev->dev.of_node, "spacc_index", 92 - &spacc_idx)) { 93 - dev_err(&pdev->dev, "No vspacc index specified\n"); 94 - err = -EINVAL; 95 - goto free_ddt_mem_pool; 96 - } 97 - priv->spacc.config.idx = spacc_idx; 98 - 99 - if (of_property_read_u32(pdev->dev.of_node, "spacc_endian", 100 - &spacc_endian)) { 101 - dev_dbg(&pdev->dev, "No spacc_endian specified\n"); 102 - dev_dbg(&pdev->dev, "Default spacc Endianness (0==little)\n"); 103 - spacc_endian = 0; 104 - } 105 - priv->spacc.config.spacc_endian = spacc_endian; 106 - 107 - if (of_property_read_u64(pdev->dev.of_node, "oldtimer", 108 - &oldtimer)) { 109 - dev_dbg(&pdev->dev, "No oldtimer specified\n"); 110 - dev_dbg(&pdev->dev, "Default oldtimer (100000)\n"); 111 - oldtimer = 100000; 112 - } 113 - priv->spacc.config.oldtimer = oldtimer; 114 - 115 - if (of_property_read_u64(pdev->dev.of_node, "timer", &timer)) { 116 - dev_dbg(&pdev->dev, "No timer specified\n"); 117 - dev_dbg(&pdev->dev, "Default timer (100000)\n"); 118 - timer = 100000; 119 - } 120 - priv->spacc.config.timer = timer; 121 - 122 - baseaddr = devm_ioremap_resource(&pdev->dev, mem); 123 - if (IS_ERR(baseaddr)) { 124 - dev_err(&pdev->dev, "unable to map iomem\n"); 125 - err = PTR_ERR(baseaddr); 126 - goto free_ddt_mem_pool; 127 - } 128 - 129 - pdu_get_version(baseaddr, &info); 130 - if (pdev->dev.platform_data) { 131 - struct pdu_info *parent_info = pdev->dev.platform_data; 132 - 133 - memcpy(&info.pdu_config, &parent_info->pdu_config, 134 - sizeof(info.pdu_config)); 135 - } 136 - 137 - dev_dbg(&pdev->dev, "EPN %04X : virt [%d]\n", 138 - info.spacc_version.project, 139 - info.spacc_version.vspacc_idx); 140 - 141 - /* Validate virtual spacc index with vspacc count read from 142 - * VERSION_EXT.VSPACC_CNT. Thus vspacc count=3, gives valid index 0,1,2 143 - */ 144 - if (spacc_idx != info.spacc_version.vspacc_idx) { 145 - dev_err(&pdev->dev, "DTS vspacc_idx mismatch read value\n"); 146 - err = -EINVAL; 147 - goto free_ddt_mem_pool; 148 - } 149 - 150 - if (spacc_idx < 0 || spacc_idx > (info.spacc_config.num_vspacc - 1)) { 151 - dev_err(&pdev->dev, "Invalid vspacc index specified\n"); 152 - err = -EINVAL; 153 - goto free_ddt_mem_pool; 154 - } 155 - 156 - err = spacc_init(baseaddr, &priv->spacc, &info); 157 - if (err != CRYPTO_OK) { 158 - dev_err(&pdev->dev, "Failed to initialize device %d\n", x); 159 - err = -ENXIO; 160 - goto free_ddt_mem_pool; 161 - } 162 - 163 - spin_lock_init(&priv->hw_lock); 164 - spacc_irq_glbl_disable(&priv->spacc); 165 - tasklet_init(&priv->pop_jobs, spacc_pop_jobs, (unsigned long)priv); 166 - 167 - priv->spacc.dptr = &pdev->dev; 168 - platform_set_drvdata(pdev, priv); 169 - 170 - irq_num = platform_get_irq(pdev, 0); 171 - if (irq_num < 0) { 172 - dev_err(&pdev->dev, "no irq resource for spacc\n"); 173 - err = -ENXIO; 174 - goto free_ddt_mem_pool; 175 - } 176 - 177 - /* Determine configured maximum message length. */ 178 - priv->max_msg_len = priv->spacc.config.max_msg_size; 179 - 180 - if (devm_request_irq(&pdev->dev, irq_num, spacc_irq_handler, 181 - IRQF_SHARED, dev_name(&pdev->dev), 182 - &pdev->dev)) { 183 - dev_err(&pdev->dev, "failed to request IRQ\n"); 184 - err = -EBUSY; 185 - goto err_tasklet_kill; 186 - } 187 - 188 - priv->spacc.irq_cb_stat = spacc_stat_process; 189 - priv->spacc.irq_cb_cmdx = spacc_cmd_process; 190 - oldmode = priv->spacc.op_mode; 191 - priv->spacc.op_mode = SPACC_OP_MODE_IRQ; 192 - 193 - spacc_irq_stat_enable(&priv->spacc, 1); 194 - spacc_irq_cmdx_enable(&priv->spacc, 0, 1); 195 - spacc_irq_stat_wd_disable(&priv->spacc); 196 - spacc_irq_glbl_enable(&priv->spacc); 197 - 198 - 199 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_AUTODETECT) 200 - err = spacc_autodetect(&priv->spacc); 201 - if (err < 0) { 202 - spacc_irq_glbl_disable(&priv->spacc); 203 - goto err_tasklet_kill; 204 - } 205 - #else 206 - err = spacc_static_config(&priv->spacc); 207 - if (err < 0) { 208 - spacc_irq_glbl_disable(&priv->spacc); 209 - goto err_tasklet_kill; 210 - } 211 - #endif 212 - 213 - priv->spacc.op_mode = oldmode; 214 - 215 - if (priv->spacc.op_mode == SPACC_OP_MODE_IRQ) { 216 - priv->spacc.irq_cb_stat = spacc_stat_process; 217 - priv->spacc.irq_cb_cmdx = spacc_cmd_process; 218 - 219 - spacc_irq_stat_enable(&priv->spacc, 1); 220 - spacc_irq_cmdx_enable(&priv->spacc, 0, 1); 221 - spacc_irq_glbl_enable(&priv->spacc); 222 - } else { 223 - priv->spacc.irq_cb_stat = spacc_stat_process; 224 - priv->spacc.irq_cb_stat_wd = spacc_stat_process; 225 - 226 - spacc_irq_stat_enable(&priv->spacc, 227 - priv->spacc.config.ideal_stat_level); 228 - 229 - spacc_irq_cmdx_disable(&priv->spacc, 0); 230 - spacc_irq_stat_wd_enable(&priv->spacc); 231 - spacc_irq_glbl_enable(&priv->spacc); 232 - 233 - /* enable the wd by setting the wd_timer = 100000 */ 234 - spacc_set_wd_count(&priv->spacc, 235 - priv->spacc.config.wd_timer = 236 - priv->spacc.config.timer); 237 - } 238 - 239 - /* unlock normal*/ 240 - if (priv->spacc.config.is_secure_port) { 241 - u32 t; 242 - 243 - t = readl(baseaddr + SPACC_REG_SECURE_CTRL); 244 - t &= ~(1UL << 31); 245 - writel(t, baseaddr + SPACC_REG_SECURE_CTRL); 246 - } 247 - 248 - /* unlock device by default */ 249 - writel(0, baseaddr + SPACC_REG_SECURE_CTRL); 250 - 251 - return err; 252 - 253 - err_tasklet_kill: 254 - tasklet_kill(&priv->pop_jobs); 255 - spacc_fini(&priv->spacc); 256 - 257 - free_ddt_mem_pool: 258 - pdu_mem_deinit(&pdev->dev); 259 - 260 - return err; 261 - } 262 - 263 - static void spacc_unregister_algs(void) 264 - { 265 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_HASH) 266 - spacc_unregister_hash_algs(); 267 - #endif 268 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_AEAD) 269 - spacc_unregister_aead_algs(); 270 - #endif 271 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_CIPHER) 272 - spacc_unregister_cipher_algs(); 273 - #endif 274 - } 275 - 276 - static const struct of_device_id snps_spacc_id[] = { 277 - {.compatible = "snps-dwc-spacc" }, 278 - { /*sentinel */ } 279 - }; 280 - 281 - MODULE_DEVICE_TABLE(of, snps_spacc_id); 282 - 283 - static int spacc_crypto_probe(struct platform_device *pdev) 284 - { 285 - int rc; 286 - 287 - rc = spacc_probe(pdev, snps_spacc_id); 288 - if (rc < 0) 289 - goto err; 290 - 291 - spacc_pdev[0] = pdev; 292 - 293 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_HASH) 294 - rc = probe_hashes(pdev); 295 - if (rc < 0) 296 - goto err; 297 - #endif 298 - 299 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_CIPHER) 300 - rc = probe_ciphers(pdev); 301 - if (rc < 0) 302 - goto err; 303 - #endif 304 - 305 - #if IS_ENABLED(CONFIG_CRYPTO_DEV_SPACC_AEAD) 306 - rc = probe_aeads(pdev); 307 - if (rc < 0) 308 - goto err; 309 - #endif 310 - 311 - return 0; 312 - err: 313 - spacc_unregister_algs(); 314 - 315 - return rc; 316 - } 317 - 318 - static void spacc_crypto_remove(struct platform_device *pdev) 319 - { 320 - spacc_unregister_algs(); 321 - spacc_remove(pdev); 322 - } 323 - 324 - static struct platform_driver spacc_driver = { 325 - .probe = spacc_crypto_probe, 326 - .remove = spacc_crypto_remove, 327 - .driver = { 328 - .name = "spacc", 329 - .of_match_table = of_match_ptr(snps_spacc_id), 330 - .owner = THIS_MODULE, 331 - }, 332 - }; 333 - 334 - module_platform_driver(spacc_driver); 335 - 336 - MODULE_LICENSE("GPL"); 337 - MODULE_AUTHOR("Synopsys, Inc."); 338 - MODULE_DESCRIPTION("SPAcc Crypto Accelerator Driver");
-231
drivers/crypto/dwc-spacc/spacc_device.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - 3 - #ifndef SPACC_DEVICE_H_ 4 - #define SPACC_DEVICE_H_ 5 - 6 - #include <crypto/hash.h> 7 - #include <crypto/ctr.h> 8 - #include <crypto/internal/aead.h> 9 - #include <linux/of.h> 10 - #include "spacc_core.h" 11 - 12 - #define MODE_TAB_AEAD(_name, _ciph, _hash, _hashlen, _ivlen, _blocklen) \ 13 - .name = _name, .aead = { .ciph = _ciph, .hash = _hash }, \ 14 - .hashlen = _hashlen, .ivlen = _ivlen, .blocklen = _blocklen 15 - 16 - /* Helper macros for initializing the hash/cipher tables. */ 17 - #define MODE_TAB_COMMON(_name, _id_name, _blocklen) \ 18 - .name = _name, .id = CRYPTO_MODE_##_id_name, .blocklen = _blocklen 19 - 20 - #define MODE_TAB_HASH(_name, _id_name, _hashlen, _blocklen) \ 21 - MODE_TAB_COMMON(_name, _id_name, _blocklen), \ 22 - .hashlen = _hashlen, .testlen = _hashlen 23 - 24 - #define MODE_TAB_CIPH(_name, _id_name, _ivlen, _blocklen) \ 25 - MODE_TAB_COMMON(_name, _id_name, _blocklen), \ 26 - .ivlen = _ivlen 27 - 28 - #define MODE_TAB_HASH_XCBC 0x8000 29 - 30 - #define SPACC_MAX_DIGEST_SIZE 64 31 - #define SPACC_MAX_KEY_SIZE 32 32 - #define SPACC_MAX_IV_SIZE 16 33 - 34 - #define SPACC_DMA_ALIGN 4 35 - #define SPACC_DMA_BOUNDARY 0x10000 36 - 37 - #define MAX_DEVICES 2 38 - /* flag means the IV is computed from setkey and crypt*/ 39 - #define SPACC_MANGLE_IV_FLAG 0x8000 40 - 41 - /* we're doing a CTR mangle (for RFC3686/IPsec)*/ 42 - #define SPACC_MANGLE_IV_RFC3686 0x0100 43 - 44 - /* we're doing GCM */ 45 - #define SPACC_MANGLE_IV_RFC4106 0x0200 46 - 47 - /* we're doing GMAC */ 48 - #define SPACC_MANGLE_IV_RFC4543 0x0300 49 - 50 - /* we're doing CCM */ 51 - #define SPACC_MANGLE_IV_RFC4309 0x0400 52 - 53 - /* we're doing SM4 GCM/CCM */ 54 - #define SPACC_MANGLE_IV_RFC8998 0x0500 55 - 56 - #define CRYPTO_MODE_AES_CTR_RFC3686 (CRYPTO_MODE_AES_CTR \ 57 - | SPACC_MANGLE_IV_FLAG \ 58 - | SPACC_MANGLE_IV_RFC3686) 59 - #define CRYPTO_MODE_AES_GCM_RFC4106 (CRYPTO_MODE_AES_GCM \ 60 - | SPACC_MANGLE_IV_FLAG \ 61 - | SPACC_MANGLE_IV_RFC4106) 62 - #define CRYPTO_MODE_AES_GCM_RFC4543 (CRYPTO_MODE_AES_GCM \ 63 - | SPACC_MANGLE_IV_FLAG \ 64 - | SPACC_MANGLE_IV_RFC4543) 65 - #define CRYPTO_MODE_AES_CCM_RFC4309 (CRYPTO_MODE_AES_CCM \ 66 - | SPACC_MANGLE_IV_FLAG \ 67 - | SPACC_MANGLE_IV_RFC4309) 68 - #define CRYPTO_MODE_SM4_GCM_RFC8998 (CRYPTO_MODE_SM4_GCM) 69 - #define CRYPTO_MODE_SM4_CCM_RFC8998 (CRYPTO_MODE_SM4_CCM) 70 - 71 - struct spacc_crypto_ctx { 72 - struct device *dev; 73 - 74 - spinlock_t lock; 75 - struct list_head jobs; 76 - int handle, mode, auth_size, key_len; 77 - unsigned char *cipher_key; 78 - 79 - /* 80 - * Indicates that the H/W context has been setup and can be used for 81 - * crypto; otherwise, the software fallback will be used. 82 - */ 83 - bool ctx_valid; 84 - unsigned int flag_ppp; 85 - 86 - /* salt used for rfc3686/givencrypt mode */ 87 - unsigned char csalt[16]; 88 - u8 ipad[128] __aligned(sizeof(u32)); 89 - u8 digest_ctx_buf[128] __aligned(sizeof(u32)); 90 - u8 tmp_buffer[128] __aligned(sizeof(u32)); 91 - 92 - /* Save keylen from setkey */ 93 - int keylen; 94 - u8 key[256]; 95 - int zero_key; 96 - unsigned char *tmp_sgl_buff; 97 - struct scatterlist *tmp_sgl; 98 - 99 - union{ 100 - struct crypto_ahash *hash; 101 - struct crypto_aead *aead; 102 - struct crypto_skcipher *cipher; 103 - } fb; 104 - }; 105 - 106 - struct spacc_crypto_reqctx { 107 - struct pdu_ddt src, dst; 108 - void *digest_buf, *iv_buf; 109 - dma_addr_t digest_dma; 110 - int dst_nents, src_nents, aead_nents, total_nents; 111 - int encrypt_op, mode, single_shot; 112 - unsigned int spacc_cipher_cryptlen, rem_nents; 113 - 114 - struct aead_cb_data { 115 - int new_handle; 116 - struct spacc_crypto_ctx *tctx; 117 - struct spacc_crypto_reqctx *ctx; 118 - struct aead_request *req; 119 - struct spacc_device *spacc; 120 - } cb; 121 - 122 - struct ahash_cb_data { 123 - int new_handle; 124 - struct spacc_crypto_ctx *tctx; 125 - struct spacc_crypto_reqctx *ctx; 126 - struct ahash_request *req; 127 - struct spacc_device *spacc; 128 - } acb; 129 - 130 - struct cipher_cb_data { 131 - int new_handle; 132 - struct spacc_crypto_ctx *tctx; 133 - struct spacc_crypto_reqctx *ctx; 134 - struct skcipher_request *req; 135 - struct spacc_device *spacc; 136 - } ccb; 137 - 138 - union { 139 - struct ahash_request hash_req; 140 - struct skcipher_request cipher_req; 141 - struct aead_request aead_req; 142 - } fb; 143 - }; 144 - 145 - struct mode_tab { 146 - char name[128]; 147 - 148 - int valid; 149 - 150 - /* mode ID used in hash/cipher mode but not aead*/ 151 - int id; 152 - 153 - /* ciph/hash mode used in aead */ 154 - struct { 155 - int ciph, hash; 156 - } aead; 157 - 158 - unsigned int hashlen, ivlen, blocklen, keylen[3]; 159 - unsigned int keylen_mask, testlen; 160 - unsigned int chunksize, walksize, min_keysize, max_keysize; 161 - 162 - bool sw_fb; 163 - 164 - union { 165 - unsigned char hash_test[SPACC_MAX_DIGEST_SIZE]; 166 - unsigned char ciph_test[3][2 * SPACC_MAX_IV_SIZE]; 167 - }; 168 - }; 169 - 170 - struct spacc_alg { 171 - struct mode_tab *mode; 172 - unsigned int keylen_mask; 173 - 174 - struct device *dev[MAX_DEVICES]; 175 - 176 - struct list_head list; 177 - struct crypto_alg *calg; 178 - struct crypto_tfm *tfm; 179 - 180 - union { 181 - struct ahash_alg hash; 182 - struct aead_alg aead; 183 - struct skcipher_alg skcipher; 184 - } alg; 185 - }; 186 - 187 - static inline const struct spacc_alg *spacc_tfm_ahash(struct crypto_tfm *tfm) 188 - { 189 - const struct crypto_alg *calg = tfm->__crt_alg; 190 - 191 - if ((calg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH) 192 - return container_of(calg, struct spacc_alg, alg.hash.halg.base); 193 - 194 - return NULL; 195 - } 196 - 197 - static inline const struct spacc_alg *spacc_tfm_skcipher(struct crypto_tfm *tfm) 198 - { 199 - const struct crypto_alg *calg = tfm->__crt_alg; 200 - 201 - if ((calg->cra_flags & CRYPTO_ALG_TYPE_MASK) == 202 - CRYPTO_ALG_TYPE_SKCIPHER) 203 - return container_of(calg, struct spacc_alg, alg.skcipher.base); 204 - 205 - return NULL; 206 - } 207 - 208 - static inline const struct spacc_alg *spacc_tfm_aead(struct crypto_tfm *tfm) 209 - { 210 - const struct crypto_alg *calg = tfm->__crt_alg; 211 - 212 - if ((calg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AEAD) 213 - return container_of(calg, struct spacc_alg, alg.aead.base); 214 - 215 - return NULL; 216 - } 217 - 218 - int probe_hashes(struct platform_device *spacc_pdev); 219 - int spacc_unregister_hash_algs(void); 220 - 221 - int probe_aeads(struct platform_device *spacc_pdev); 222 - int spacc_unregister_aead_algs(void); 223 - 224 - int probe_ciphers(struct platform_device *spacc_pdev); 225 - int spacc_unregister_cipher_algs(void); 226 - 227 - int spacc_probe(struct platform_device *pdev, 228 - const struct of_device_id snps_spacc_id[]); 229 - 230 - irqreturn_t spacc_irq_handler(int irq, void *dev); 231 - #endif
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drivers/crypto/dwc-spacc/spacc_hal.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - 3 - #include <linux/dmapool.h> 4 - #include <linux/dma-mapping.h> 5 - #include "spacc_hal.h" 6 - 7 - static struct dma_pool *ddt_pool, *ddt16_pool, *ddt4_pool; 8 - static struct device *ddt_device; 9 - 10 - #define PDU_REG_SPACC_VERSION 0x00180UL 11 - #define PDU_REG_SPACC_CONFIG 0x00184UL 12 - #define PDU_REG_SPACC_CONFIG2 0x00190UL 13 - #define PDU_REG_SPACC_IV_OFFSET 0x00040UL 14 - #define PDU_REG_PDU_CONFIG 0x00188UL 15 - #define PDU_REG_SECURE_LOCK 0x001C0UL 16 - 17 - int pdu_get_version(void __iomem *dev, struct pdu_info *inf) 18 - { 19 - unsigned long tmp; 20 - 21 - if (!inf) 22 - return -1; 23 - 24 - memset(inf, 0, sizeof(*inf)); 25 - tmp = readl(dev + PDU_REG_SPACC_VERSION); 26 - 27 - /* Read the SPAcc version block this tells us the revision, 28 - * project, and a few other feature bits 29 - * 30 - * layout for v6.5+ 31 - */ 32 - inf->spacc_version = (struct spacc_version_block) { 33 - .minor = SPACC_ID_MINOR(tmp), 34 - .major = SPACC_ID_MAJOR(tmp), 35 - .version = (SPACC_ID_MAJOR(tmp) << 4) | SPACC_ID_MINOR(tmp), 36 - .qos = SPACC_ID_QOS(tmp), 37 - .is_spacc = SPACC_ID_TYPE(tmp) == SPACC_TYPE_SPACCQOS, 38 - .is_pdu = SPACC_ID_TYPE(tmp) == SPACC_TYPE_PDU, 39 - .aux = SPACC_ID_AUX(tmp), 40 - .vspacc_idx = SPACC_ID_VIDX(tmp), 41 - .partial = SPACC_ID_PARTIAL(tmp), 42 - .project = SPACC_ID_PROJECT(tmp), 43 - }; 44 - 45 - /* try to autodetect */ 46 - writel(0x80000000, dev + PDU_REG_SPACC_IV_OFFSET); 47 - 48 - if (readl(dev + PDU_REG_SPACC_IV_OFFSET) == 0x80000000) 49 - inf->spacc_version.ivimport = 1; 50 - else 51 - inf->spacc_version.ivimport = 0; 52 - 53 - 54 - /* Read the SPAcc config block (v6.5+) which tells us how many 55 - * contexts there are and context page sizes 56 - * this register is only available in v6.5 and up 57 - */ 58 - tmp = readl(dev + PDU_REG_SPACC_CONFIG); 59 - inf->spacc_config = (struct spacc_config_block) { 60 - SPACC_CFG_CTX_CNT(tmp), 61 - SPACC_CFG_VSPACC_CNT(tmp), 62 - SPACC_CFG_CIPH_CTX_SZ(tmp), 63 - SPACC_CFG_HASH_CTX_SZ(tmp), 64 - SPACC_CFG_DMA_TYPE(tmp), 65 - 0, 0, 0, 0 66 - }; 67 - 68 - /* CONFIG2 only present in v6.5+ cores */ 69 - tmp = readl(dev + PDU_REG_SPACC_CONFIG2); 70 - if (inf->spacc_version.qos) { 71 - inf->spacc_config.cmd0_fifo_depth = 72 - SPACC_CFG_CMD0_FIFO_QOS(tmp); 73 - inf->spacc_config.cmd1_fifo_depth = 74 - SPACC_CFG_CMD1_FIFO(tmp); 75 - inf->spacc_config.cmd2_fifo_depth = 76 - SPACC_CFG_CMD2_FIFO(tmp); 77 - inf->spacc_config.stat_fifo_depth = 78 - SPACC_CFG_STAT_FIFO_QOS(tmp); 79 - } else { 80 - inf->spacc_config.cmd0_fifo_depth = 81 - SPACC_CFG_CMD0_FIFO(tmp); 82 - inf->spacc_config.stat_fifo_depth = 83 - SPACC_CFG_STAT_FIFO(tmp); 84 - } 85 - 86 - /* only read PDU config if it's actually a PDU engine */ 87 - if (inf->spacc_version.is_pdu) { 88 - tmp = readl(dev + PDU_REG_PDU_CONFIG); 89 - inf->pdu_config = (struct pdu_config_block) 90 - {SPACC_PDU_CFG_MINOR(tmp), 91 - SPACC_PDU_CFG_MAJOR(tmp)}; 92 - 93 - /* unlock all cores by default */ 94 - writel(0, dev + PDU_REG_SECURE_LOCK); 95 - } 96 - 97 - return 0; 98 - } 99 - 100 - void pdu_to_dev(void __iomem *addr_, uint32_t *src, unsigned long nword) 101 - { 102 - void __iomem *addr = addr_; 103 - 104 - while (nword--) { 105 - writel(*src++, addr); 106 - addr += 4; 107 - } 108 - } 109 - 110 - void pdu_from_dev(u32 *dst, void __iomem *addr_, unsigned long nword) 111 - { 112 - void __iomem *addr = addr_; 113 - 114 - while (nword--) { 115 - *dst++ = readl(addr); 116 - addr += 4; 117 - } 118 - } 119 - 120 - static void pdu_to_dev_big(void __iomem *addr_, const unsigned char *src, 121 - unsigned long nword) 122 - { 123 - unsigned long v; 124 - void __iomem *addr = addr_; 125 - 126 - while (nword--) { 127 - v = 0; 128 - v = (v << 8) | ((unsigned long)*src++); 129 - v = (v << 8) | ((unsigned long)*src++); 130 - v = (v << 8) | ((unsigned long)*src++); 131 - v = (v << 8) | ((unsigned long)*src++); 132 - writel(v, addr); 133 - addr += 4; 134 - } 135 - } 136 - 137 - static void pdu_from_dev_big(unsigned char *dst, void __iomem *addr_, 138 - unsigned long nword) 139 - { 140 - unsigned long v; 141 - void __iomem *addr = addr_; 142 - 143 - while (nword--) { 144 - v = readl(addr); 145 - addr += 4; 146 - *dst++ = (v >> 24) & 0xFF; v <<= 8; 147 - *dst++ = (v >> 24) & 0xFF; v <<= 8; 148 - *dst++ = (v >> 24) & 0xFF; v <<= 8; 149 - *dst++ = (v >> 24) & 0xFF; v <<= 8; 150 - } 151 - } 152 - 153 - static void pdu_to_dev_little(void __iomem *addr_, const unsigned char *src, 154 - unsigned long nword) 155 - { 156 - unsigned long v; 157 - void __iomem *addr = addr_; 158 - 159 - while (nword--) { 160 - v = 0; 161 - v = (v >> 8) | ((unsigned long)*src++ << 24UL); 162 - v = (v >> 8) | ((unsigned long)*src++ << 24UL); 163 - v = (v >> 8) | ((unsigned long)*src++ << 24UL); 164 - v = (v >> 8) | ((unsigned long)*src++ << 24UL); 165 - writel(v, addr); 166 - addr += 4; 167 - } 168 - } 169 - 170 - static void pdu_from_dev_little(unsigned char *dst, void __iomem *addr_, 171 - unsigned long nword) 172 - { 173 - unsigned long v; 174 - void __iomem *addr = addr_; 175 - 176 - while (nword--) { 177 - v = readl(addr); 178 - addr += 4; 179 - *dst++ = v & 0xFF; v >>= 8; 180 - *dst++ = v & 0xFF; v >>= 8; 181 - *dst++ = v & 0xFF; v >>= 8; 182 - *dst++ = v & 0xFF; v >>= 8; 183 - } 184 - } 185 - 186 - void pdu_to_dev_s(void __iomem *addr, const unsigned char *src, 187 - unsigned long nword, int endian) 188 - { 189 - if (endian) 190 - pdu_to_dev_big(addr, src, nword); 191 - else 192 - pdu_to_dev_little(addr, src, nword); 193 - } 194 - 195 - void pdu_from_dev_s(unsigned char *dst, void __iomem *addr, 196 - unsigned long nword, int endian) 197 - { 198 - if (endian) 199 - pdu_from_dev_big(dst, addr, nword); 200 - else 201 - pdu_from_dev_little(dst, addr, nword); 202 - } 203 - 204 - void pdu_io_cached_write(void __iomem *addr, unsigned long val, 205 - uint32_t *cache) 206 - { 207 - if (*cache == val) { 208 - #ifdef CONFIG_CRYPTO_DEV_SPACC_DEBUG_TRACE_IO 209 - pr_debug("PDU: write %.8lx -> %p (cached)\n", val, addr); 210 - #endif 211 - return; 212 - } 213 - 214 - *cache = val; 215 - writel(val, addr); 216 - } 217 - 218 - struct device *get_ddt_device(void) 219 - { 220 - return ddt_device; 221 - } 222 - 223 - /* Platform specific DDT routines */ 224 - 225 - /* create a DMA pool for DDT entries this should help from splitting 226 - * pages for DDTs which by default are 520 bytes long meaning we would 227 - * otherwise waste 3576 bytes per DDT allocated... 228 - * we also maintain a smaller table of 4 entries common for simple jobs 229 - * which uses 480 fewer bytes of DMA memory. 230 - * and for good measure another table for 16 entries saving 384 bytes 231 - */ 232 - int pdu_mem_init(void *device) 233 - { 234 - if (ddt_device) 235 - return 0; /* Already setup */ 236 - 237 - ddt_device = device; 238 - ddt_pool = dma_pool_create("spaccddt", device, (PDU_MAX_DDT + 1) * 8, 239 - 8, 0); /* max of 64 DDT entries */ 240 - 241 - if (!ddt_pool) 242 - return -1; 243 - 244 - #if PDU_MAX_DDT > 16 245 - /* max of 16 DDT entries */ 246 - ddt16_pool = dma_pool_create("spaccddt16", device, (16 + 1) * 8, 8, 0); 247 - if (!ddt16_pool) { 248 - dma_pool_destroy(ddt_pool); 249 - return -1; 250 - } 251 - #else 252 - ddt16_pool = ddt_pool; 253 - #endif 254 - /* max of 4 DDT entries */ 255 - ddt4_pool = dma_pool_create("spaccddt4", device, (4 + 1) * 8, 8, 0); 256 - if (!ddt4_pool) { 257 - dma_pool_destroy(ddt_pool); 258 - #if PDU_MAX_DDT > 16 259 - dma_pool_destroy(ddt16_pool); 260 - #endif 261 - return -1; 262 - } 263 - 264 - return 0; 265 - } 266 - 267 - /* destroy the pool */ 268 - void pdu_mem_deinit(void *device) 269 - { 270 - /* For now, just skip deinit except for matching device */ 271 - if (device != ddt_device) 272 - return; 273 - 274 - dma_pool_destroy(ddt_pool); 275 - 276 - #if PDU_MAX_DDT > 16 277 - dma_pool_destroy(ddt16_pool); 278 - #endif 279 - dma_pool_destroy(ddt4_pool); 280 - 281 - ddt_device = NULL; 282 - } 283 - 284 - int pdu_ddt_init(struct pdu_ddt *ddt, unsigned long limit) 285 - { 286 - /* set the MSB if we want to use an ATOMIC 287 - * allocation required for top half processing 288 - */ 289 - int flag = (limit & 0x80000000); 290 - 291 - limit &= 0x7FFFFFFF; 292 - if (limit + 1 >= SIZE_MAX / 8) { 293 - /* Too big to even compute DDT size */ 294 - return -1; 295 - } else if (limit > PDU_MAX_DDT) { 296 - size_t len = 8 * ((size_t)limit + 1); 297 - 298 - ddt->virt = dma_alloc_coherent(ddt_device, len, &ddt->phys, 299 - flag ? GFP_ATOMIC : GFP_KERNEL); 300 - } else if (limit > 16) { 301 - ddt->virt = dma_pool_alloc(ddt_pool, flag ? GFP_ATOMIC : 302 - GFP_KERNEL, &ddt->phys); 303 - } else if (limit > 4) { 304 - ddt->virt = dma_pool_alloc(ddt16_pool, flag ? GFP_ATOMIC : 305 - GFP_KERNEL, &ddt->phys); 306 - } else { 307 - ddt->virt = dma_pool_alloc(ddt4_pool, flag ? GFP_ATOMIC : 308 - GFP_KERNEL, &ddt->phys); 309 - } 310 - 311 - ddt->idx = 0; 312 - ddt->len = 0; 313 - ddt->limit = limit; 314 - 315 - if (!ddt->virt) 316 - return -1; 317 - 318 - #ifdef CONFIG_CRYPTO_DEV_SPACC_DEBUG_TRACE_DDT 319 - pr_debug(" DDT[%.8lx]: allocated %lu fragments\n", 320 - (unsigned long)ddt->phys, limit); 321 - #endif 322 - 323 - return 0; 324 - } 325 - 326 - int pdu_ddt_add(struct pdu_ddt *ddt, dma_addr_t phys, unsigned long size) 327 - { 328 - #ifdef CONFIG_CRYPTO_DEV_SPACC_DEBUG_TRACE_DDT 329 - pr_debug(" DDT[%.8lx]: 0x%.8lx size %lu\n", 330 - (unsigned long)ddt->phys, 331 - (unsigned long)phys, size); 332 - #endif 333 - 334 - if (ddt->idx == ddt->limit) 335 - return -1; 336 - 337 - ddt->virt[ddt->idx * 2 + 0] = (uint32_t)phys; 338 - ddt->virt[ddt->idx * 2 + 1] = size; 339 - ddt->virt[ddt->idx * 2 + 2] = 0; 340 - ddt->virt[ddt->idx * 2 + 3] = 0; 341 - ddt->len += size; 342 - ++(ddt->idx); 343 - 344 - return 0; 345 - } 346 - 347 - int pdu_ddt_free(struct pdu_ddt *ddt) 348 - { 349 - if (ddt->virt) { 350 - if (ddt->limit > PDU_MAX_DDT) { 351 - size_t len = 8 * ((size_t)ddt->limit + 1); 352 - 353 - dma_free_coherent(ddt_device, len, ddt->virt, 354 - ddt->phys); 355 - } else if (ddt->limit > 16) { 356 - dma_pool_free(ddt_pool, ddt->virt, ddt->phys); 357 - } else if (ddt->limit > 4) { 358 - dma_pool_free(ddt16_pool, ddt->virt, ddt->phys); 359 - } else { 360 - dma_pool_free(ddt4_pool, ddt->virt, ddt->phys); 361 - } 362 - 363 - ddt->virt = NULL; 364 - } 365 - 366 - return 0; 367 - }
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drivers/crypto/dwc-spacc/spacc_hal.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - 3 - #ifndef SPACC_HAL_H 4 - #define SPACC_HAL_H 5 - 6 - /* Maximum number of DDT entries allowed*/ 7 - #ifndef PDU_MAX_DDT 8 - #define PDU_MAX_DDT 64 9 - #endif 10 - 11 - /* Platform Generic */ 12 - #define PDU_IRQ_EN_GLBL BIT(31) 13 - #define PDU_IRQ_EN_VSPACC(x) (1UL << (x)) 14 - #define PDU_IRQ_EN_RNG BIT(16) 15 - 16 - #ifndef SPACC_ID_MINOR 17 - #define SPACC_ID_MINOR(x) ((x) & 0x0F) 18 - #define SPACC_ID_MAJOR(x) (((x) >> 4) & 0x0F) 19 - #define SPACC_ID_QOS(x) (((x) >> 8) & 0x01) 20 - #define SPACC_ID_TYPE(x) (((x) >> 9) & 0x03) 21 - #define SPACC_ID_AUX(x) (((x) >> 11) & 0x01) 22 - #define SPACC_ID_VIDX(x) (((x) >> 12) & 0x07) 23 - #define SPACC_ID_PARTIAL(x) (((x) >> 15) & 0x01) 24 - #define SPACC_ID_PROJECT(x) ((x) >> 16) 25 - 26 - #define SPACC_TYPE_SPACCQOS 0 27 - #define SPACC_TYPE_PDU 1 28 - 29 - #define SPACC_CFG_CTX_CNT(x) ((x) & 0x7F) 30 - #define SPACC_CFG_RC4_CTX_CNT(x) (((x) >> 8) & 0x7F) 31 - #define SPACC_CFG_VSPACC_CNT(x) (((x) >> 16) & 0x0F) 32 - #define SPACC_CFG_CIPH_CTX_SZ(x) (((x) >> 20) & 0x07) 33 - #define SPACC_CFG_HASH_CTX_SZ(x) (((x) >> 24) & 0x0F) 34 - #define SPACC_CFG_DMA_TYPE(x) (((x) >> 28) & 0x03) 35 - 36 - #define SPACC_CFG_CMD0_FIFO_QOS(x) (((x) >> 0) & 0x7F) 37 - #define SPACC_CFG_CMD0_FIFO(x) (((x) >> 0) & 0x1FF) 38 - #define SPACC_CFG_CMD1_FIFO(x) (((x) >> 8) & 0x7F) 39 - #define SPACC_CFG_CMD2_FIFO(x) (((x) >> 16) & 0x7F) 40 - #define SPACC_CFG_STAT_FIFO_QOS(x) (((x) >> 24) & 0x7F) 41 - #define SPACC_CFG_STAT_FIFO(x) (((x) >> 16) & 0x1FF) 42 - 43 - #define SPACC_PDU_CFG_MINOR(x) ((x) & 0x0F) 44 - #define SPACC_PDU_CFG_MAJOR(x) (((x) >> 4) & 0x0F) 45 - 46 - #define PDU_SECURE_LOCK_SPACC(x) (x) 47 - #define PDU_SECURE_LOCK_CFG BIT(30) 48 - #define PDU_SECURE_LOCK_GLBL BIT(31) 49 - #endif /* SPACC_ID_MINOR */ 50 - 51 - #define CRYPTO_OK (0) 52 - 53 - struct spacc_version_block { 54 - unsigned int minor, 55 - major, 56 - version, 57 - qos, 58 - is_spacc, 59 - is_pdu, 60 - aux, 61 - vspacc_idx, 62 - partial, 63 - project, 64 - ivimport; 65 - }; 66 - 67 - struct spacc_config_block { 68 - unsigned int num_ctx, 69 - num_vspacc, 70 - ciph_ctx_page_size, 71 - hash_ctx_page_size, 72 - dma_type, 73 - cmd0_fifo_depth, 74 - cmd1_fifo_depth, 75 - cmd2_fifo_depth, 76 - stat_fifo_depth; 77 - }; 78 - 79 - struct pdu_config_block { 80 - unsigned int minor, 81 - major; 82 - }; 83 - 84 - struct pdu_info { 85 - u32 clockrate; 86 - struct spacc_version_block spacc_version; 87 - struct spacc_config_block spacc_config; 88 - struct pdu_config_block pdu_config; 89 - }; 90 - 91 - struct pdu_ddt { 92 - dma_addr_t phys; 93 - u32 *virt; 94 - u32 *virt_orig; 95 - unsigned long idx, limit, len; 96 - }; 97 - 98 - void pdu_io_cached_write(void __iomem *addr, unsigned long val, 99 - uint32_t *cache); 100 - void pdu_to_dev(void __iomem *addr, uint32_t *src, unsigned long nword); 101 - void pdu_from_dev(u32 *dst, void __iomem *addr, unsigned long nword); 102 - void pdu_from_dev_s(unsigned char *dst, void __iomem *addr, unsigned long nword, 103 - int endian); 104 - void pdu_to_dev_s(void __iomem *addr, const unsigned char *src, 105 - unsigned long nword, int endian); 106 - struct device *get_ddt_device(void); 107 - int pdu_mem_init(void *device); 108 - void pdu_mem_deinit(void *device); 109 - int pdu_ddt_init(struct pdu_ddt *ddt, unsigned long limit); 110 - int pdu_ddt_add(struct pdu_ddt *ddt, dma_addr_t phys, unsigned long size); 111 - int pdu_ddt_free(struct pdu_ddt *ddt); 112 - int pdu_get_version(void __iomem *dev, struct pdu_info *inf); 113 - 114 - #endif
-316
drivers/crypto/dwc-spacc/spacc_interrupt.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - 3 - #include <linux/interrupt.h> 4 - #include <linux/platform_device.h> 5 - #include "spacc_core.h" 6 - 7 - /* Read the IRQ status register and process as needed */ 8 - 9 - 10 - void spacc_disable_int (struct spacc_device *spacc); 11 - 12 - static inline uint32_t _spacc_get_stat_cnt(struct spacc_device *spacc) 13 - { 14 - u32 fifo; 15 - 16 - if (spacc->config.is_qos) 17 - fifo = SPACC_FIFO_STAT_STAT_CNT_GET_QOS(readl(spacc->regmap + 18 - SPACC_REG_FIFO_STAT)); 19 - else 20 - fifo = SPACC_FIFO_STAT_STAT_CNT_GET(readl(spacc->regmap + 21 - SPACC_REG_FIFO_STAT)); 22 - 23 - return fifo; 24 - } 25 - 26 - static int spacc_pop_packets_ex(struct spacc_device *spacc, int *num_popped, 27 - unsigned long *lock_flag) 28 - { 29 - int jobs; 30 - int ret = -EINPROGRESS; 31 - struct spacc_job *job = NULL; 32 - u32 cmdstat, swid, spacc_errcode = SPACC_OK; 33 - 34 - *num_popped = 0; 35 - 36 - while ((jobs = _spacc_get_stat_cnt(spacc))) { 37 - while (jobs-- > 0) { 38 - /* write the pop register to get the next job */ 39 - writel(1, spacc->regmap + SPACC_REG_STAT_POP); 40 - cmdstat = readl(spacc->regmap + SPACC_REG_STATUS); 41 - 42 - swid = SPACC_STATUS_SW_ID_GET(cmdstat); 43 - 44 - if (spacc->job_lookup[swid] == SPACC_JOB_IDX_UNUSED) { 45 - ret = -EIO; 46 - goto ERR; 47 - } 48 - 49 - /* find the associated job with popped swid */ 50 - if (swid < 0 || swid >= SPACC_MAX_JOBS) 51 - job = NULL; 52 - else 53 - job = &spacc->job[spacc->job_lookup[swid]]; 54 - 55 - if (!job) { 56 - ret = -EIO; 57 - goto ERR; 58 - } 59 - 60 - /* mark job as done */ 61 - job->job_done = 1; 62 - spacc->job_lookup[swid] = SPACC_JOB_IDX_UNUSED; 63 - spacc_errcode = SPACC_GET_STATUS_RET_CODE(cmdstat); 64 - 65 - switch (spacc_errcode) { 66 - case SPACC_ICVFAIL: 67 - ret = -EBADMSG; 68 - break; 69 - case SPACC_MEMERR: 70 - ret = -EINVAL; 71 - break; 72 - case SPACC_BLOCKERR: 73 - ret = -EINVAL; 74 - break; 75 - case SPACC_SECERR: 76 - ret = -EIO; 77 - break; 78 - case SPACC_OK: 79 - ret = CRYPTO_OK; 80 - break; 81 - default: 82 - pr_debug("Invalid SPAcc Error"); 83 - } 84 - 85 - job->job_err = ret; 86 - 87 - /* 88 - * We're done touching the SPAcc hw, so release the 89 - * lock across the job callback. It must be reacquired 90 - * before continuing to the next iteration. 91 - */ 92 - 93 - if (job->cb) { 94 - spin_unlock_irqrestore(&spacc->lock, 95 - *lock_flag); 96 - job->cb(spacc, job->cbdata); 97 - spin_lock_irqsave(&spacc->lock, 98 - *lock_flag); 99 - } 100 - 101 - (*num_popped)++; 102 - } 103 - } 104 - 105 - if (!*num_popped) 106 - pr_debug(" Failed to pop a single job\n"); 107 - 108 - ERR: 109 - spacc_process_jb(spacc); 110 - 111 - /* reset the WD timer to the original value*/ 112 - if (spacc->op_mode == SPACC_OP_MODE_WD) 113 - spacc_set_wd_count(spacc, spacc->config.wd_timer); 114 - 115 - if (*num_popped && spacc->spacc_notify_jobs) 116 - spacc->spacc_notify_jobs(spacc); 117 - 118 - return ret; 119 - } 120 - 121 - int spacc_pop_packets(struct spacc_device *spacc, int *num_popped) 122 - { 123 - int err; 124 - unsigned long lock_flag; 125 - 126 - spin_lock_irqsave(&spacc->lock, lock_flag); 127 - err = spacc_pop_packets_ex(spacc, num_popped, &lock_flag); 128 - spin_unlock_irqrestore(&spacc->lock, lock_flag); 129 - 130 - return err; 131 - } 132 - 133 - uint32_t spacc_process_irq(struct spacc_device *spacc) 134 - { 135 - u32 temp; 136 - int x, cmd_max; 137 - unsigned long lock_flag; 138 - 139 - spin_lock_irqsave(&spacc->lock, lock_flag); 140 - 141 - temp = readl(spacc->regmap + SPACC_REG_IRQ_STAT); 142 - 143 - /* clear interrupt pin and run registered callback */ 144 - if (temp & SPACC_IRQ_STAT_STAT) { 145 - SPACC_IRQ_STAT_CLEAR_STAT(spacc); 146 - if (spacc->op_mode == SPACC_OP_MODE_IRQ) { 147 - spacc->config.fifo_cnt <<= 2; 148 - if (spacc->config.fifo_cnt >= 149 - spacc->config.stat_fifo_depth) 150 - spacc->config.fifo_cnt = 151 - spacc->config.stat_fifo_depth; 152 - 153 - /* update fifo count to allow more stati to pile up*/ 154 - spacc_irq_stat_enable(spacc, spacc->config.fifo_cnt); 155 - /* reenable CMD0 empty interrupt*/ 156 - spacc_irq_cmdx_enable(spacc, 0, 0); 157 - } 158 - 159 - if (spacc->irq_cb_stat) 160 - spacc->irq_cb_stat(spacc); 161 - } 162 - 163 - /* Watchdog IRQ */ 164 - if (spacc->op_mode == SPACC_OP_MODE_WD) { 165 - if (temp & SPACC_IRQ_STAT_STAT_WD) { 166 - if (++spacc->wdcnt == SPACC_WD_LIMIT) { 167 - /* this happens when you get too many IRQs that 168 - * go unanswered 169 - */ 170 - spacc_irq_stat_wd_disable(spacc); 171 - /* we set the STAT CNT to 1 so that every job 172 - * generates an IRQ now 173 - */ 174 - spacc_irq_stat_enable(spacc, 1); 175 - spacc->op_mode = SPACC_OP_MODE_IRQ; 176 - } else if (spacc->config.wd_timer < (0xFFFFFFUL >> 4)) { 177 - /* if the timer isn't too high lets bump it up 178 - * a bit so as to give the IRQ a chance to 179 - * reply 180 - */ 181 - spacc_set_wd_count(spacc, 182 - spacc->config.wd_timer << 4); 183 - } 184 - 185 - SPACC_IRQ_STAT_CLEAR_STAT_WD(spacc); 186 - if (spacc->irq_cb_stat_wd) 187 - spacc->irq_cb_stat_wd(spacc); 188 - } 189 - } 190 - 191 - if (spacc->op_mode == SPACC_OP_MODE_IRQ) { 192 - cmd_max = (spacc->config.is_qos ? SPACC_CMDX_MAX_QOS : 193 - SPACC_CMDX_MAX); 194 - for (x = 0; x < cmd_max; x++) { 195 - if (temp & SPACC_IRQ_STAT_CMDX(x)) { 196 - spacc->config.fifo_cnt = 1; 197 - /* disable CMD0 interrupt since STAT=1 */ 198 - spacc_irq_cmdx_disable(spacc, x); 199 - spacc_irq_stat_enable(spacc, 200 - spacc->config.fifo_cnt); 201 - 202 - SPACC_IRQ_STAT_CLEAR_CMDX(spacc, x); 203 - /* run registered callback */ 204 - if (spacc->irq_cb_cmdx) 205 - spacc->irq_cb_cmdx(spacc, x); 206 - } 207 - } 208 - } 209 - 210 - spin_unlock_irqrestore(&spacc->lock, lock_flag); 211 - 212 - return temp; 213 - } 214 - 215 - void spacc_set_wd_count(struct spacc_device *spacc, uint32_t val) 216 - { 217 - writel(val, spacc->regmap + SPACC_REG_STAT_WD_CTRL); 218 - } 219 - 220 - /* cmdx and cmdx_cnt depend on HW config 221 - * cmdx can be 0, 1 or 2 222 - * cmdx_cnt must be 2^6 or less 223 - */ 224 - void spacc_irq_cmdx_enable(struct spacc_device *spacc, int cmdx, int cmdx_cnt) 225 - { 226 - u32 temp; 227 - 228 - /* read the reg, clear the bit range and set the new value */ 229 - temp = readl(spacc->regmap + SPACC_REG_IRQ_CTRL) & 230 - (~SPACC_IRQ_CTRL_CMDX_CNT_MASK(cmdx)); 231 - temp |= SPACC_IRQ_CTRL_CMDX_CNT_SET(cmdx, cmdx_cnt); 232 - 233 - writel(temp | SPACC_IRQ_CTRL_CMDX_CNT_SET(cmdx, cmdx_cnt), 234 - spacc->regmap + SPACC_REG_IRQ_CTRL); 235 - 236 - writel(readl(spacc->regmap + SPACC_REG_IRQ_EN) | SPACC_IRQ_EN_CMD(cmdx), 237 - spacc->regmap + SPACC_REG_IRQ_EN); 238 - } 239 - 240 - void spacc_irq_cmdx_disable(struct spacc_device *spacc, int cmdx) 241 - { 242 - writel(readl(spacc->regmap + SPACC_REG_IRQ_EN) & 243 - (~SPACC_IRQ_EN_CMD(cmdx)), spacc->regmap + SPACC_REG_IRQ_EN); 244 - } 245 - 246 - void spacc_irq_stat_enable(struct spacc_device *spacc, int stat_cnt) 247 - { 248 - u32 temp; 249 - 250 - temp = readl(spacc->regmap + SPACC_REG_IRQ_CTRL); 251 - if (spacc->config.is_qos) { 252 - temp &= (~SPACC_IRQ_CTRL_STAT_CNT_MASK_QOS); 253 - temp |= SPACC_IRQ_CTRL_STAT_CNT_SET_QOS(stat_cnt); 254 - } else { 255 - temp &= (~SPACC_IRQ_CTRL_STAT_CNT_MASK); 256 - temp |= SPACC_IRQ_CTRL_STAT_CNT_SET(stat_cnt); 257 - } 258 - 259 - writel(temp, spacc->regmap + SPACC_REG_IRQ_CTRL); 260 - writel(readl(spacc->regmap + SPACC_REG_IRQ_EN) | SPACC_IRQ_EN_STAT, 261 - spacc->regmap + SPACC_REG_IRQ_EN); 262 - } 263 - 264 - void spacc_irq_stat_disable(struct spacc_device *spacc) 265 - { 266 - writel(readl(spacc->regmap + SPACC_REG_IRQ_EN) & (~SPACC_IRQ_EN_STAT), 267 - spacc->regmap + SPACC_REG_IRQ_EN); 268 - } 269 - 270 - void spacc_irq_stat_wd_enable(struct spacc_device *spacc) 271 - { 272 - writel(readl(spacc->regmap + SPACC_REG_IRQ_EN) | SPACC_IRQ_EN_STAT_WD, 273 - spacc->regmap + SPACC_REG_IRQ_EN); 274 - } 275 - 276 - void spacc_irq_stat_wd_disable(struct spacc_device *spacc) 277 - { 278 - writel(readl(spacc->regmap + SPACC_REG_IRQ_EN) & 279 - (~SPACC_IRQ_EN_STAT_WD), spacc->regmap + SPACC_REG_IRQ_EN); 280 - } 281 - 282 - void spacc_irq_glbl_enable(struct spacc_device *spacc) 283 - { 284 - writel(readl(spacc->regmap + SPACC_REG_IRQ_EN) | SPACC_IRQ_EN_GLBL, 285 - spacc->regmap + SPACC_REG_IRQ_EN); 286 - } 287 - 288 - void spacc_irq_glbl_disable(struct spacc_device *spacc) 289 - { 290 - writel(readl(spacc->regmap + SPACC_REG_IRQ_EN) & (~SPACC_IRQ_EN_GLBL), 291 - spacc->regmap + SPACC_REG_IRQ_EN); 292 - } 293 - 294 - void spacc_disable_int (struct spacc_device *spacc) 295 - { 296 - writel(0, spacc->regmap + SPACC_REG_IRQ_EN); 297 - } 298 - 299 - /* a function to run callbacks in the IRQ handler */ 300 - irqreturn_t spacc_irq_handler(int irq, void *dev) 301 - { 302 - struct spacc_priv *priv = platform_get_drvdata(to_platform_device(dev)); 303 - struct spacc_device *spacc = &priv->spacc; 304 - 305 - if (spacc->config.oldtimer != spacc->config.timer) { 306 - priv->spacc.config.wd_timer = spacc->config.timer; 307 - spacc_set_wd_count(&priv->spacc, priv->spacc.config.wd_timer); 308 - spacc->config.oldtimer = spacc->config.timer; 309 - } 310 - 311 - /* check irq flags and process as required */ 312 - if (!spacc_process_irq(spacc)) 313 - return IRQ_NONE; 314 - 315 - return IRQ_HANDLED; 316 - }
-653
drivers/crypto/dwc-spacc/spacc_manager.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - 3 - #include <linux/minmax.h> 4 - #include "spacc_core.h" 5 - 6 - #ifndef MIN 7 - #define MIN(x, y) (((x) < (y)) ? (x) : (y)) 8 - #endif 9 - 10 - /* prevent reading past the end of the buffer */ 11 - static void read_from_buf(unsigned char *dst, unsigned char *src, 12 - int off, int n, int max) 13 - { 14 - if (!dst) 15 - return; 16 - 17 - while (off < max && n) { 18 - *dst++ = src[off++]; 19 - --n; 20 - } 21 - } 22 - 23 - static void write_to_buf(unsigned char *dst, const unsigned char *src, 24 - int off, int n, int len) 25 - { 26 - if (!src) 27 - return; 28 - 29 - while (n && (off < len)) { 30 - dst[off++] = *src++; 31 - --n; 32 - } 33 - } 34 - 35 - /* This function is not meant to be called directly, 36 - * it should be called from the job manager 37 - */ 38 - static int spacc_ctx_request(struct spacc_device *spacc, 39 - int ctx_id, int ncontig) 40 - { 41 - int ret; 42 - int x, y, count; 43 - unsigned long lock_flag; 44 - 45 - if (!spacc) 46 - return -1; 47 - 48 - if (ctx_id > spacc->config.num_ctx) 49 - return -1; 50 - 51 - if (ncontig < 1 || ncontig > spacc->config.num_ctx) 52 - return -1; 53 - 54 - ret = CRYPTO_OK; 55 - 56 - spin_lock_irqsave(&spacc->ctx_lock, lock_flag); 57 - /* allocating scheme, look for contiguous contexts. Free contexts have 58 - * a ref_cnt of 0. 59 - * If specific ctx_id is requested, 60 - * test the ncontig and then bump the ref_cnt 61 - */ 62 - if (ctx_id != -1) { 63 - if ((&spacc->ctx[ctx_id])->ncontig != ncontig - 1) 64 - ret = -1; 65 - } else { 66 - /* check to see if ncontig are free 67 - * loop over all available contexts to find the first 68 - * ncontig empty ones 69 - */ 70 - for (x = 0; x <= (spacc->config.num_ctx - ncontig); ) { 71 - count = ncontig; 72 - while (count) { 73 - if ((&spacc->ctx[x + count - 1])->ref_cnt != 0) { 74 - /* incr x to past failed count 75 - * location 76 - */ 77 - x = x + count; 78 - break; 79 - } 80 - count--; 81 - } 82 - if (count != 0) { 83 - ret = -1; 84 - /* test next x */ 85 - } else { 86 - ctx_id = x; 87 - ret = CRYPTO_OK; 88 - break; 89 - } 90 - } 91 - } 92 - 93 - if (ret == CRYPTO_OK) { 94 - /* ctx_id is good so mark used */ 95 - for (y = 0; y < ncontig; y++) 96 - (&spacc->ctx[ctx_id + y])->ref_cnt++; 97 - (&spacc->ctx[ctx_id])->ncontig = ncontig - 1; 98 - } else { 99 - ctx_id = -1; 100 - } 101 - 102 - spin_unlock_irqrestore(&spacc->ctx_lock, lock_flag); 103 - 104 - return ctx_id; 105 - } 106 - 107 - static int spacc_ctx_release(struct spacc_device *spacc, int ctx_id) 108 - { 109 - int y; 110 - int ncontig; 111 - unsigned long lock_flag; 112 - 113 - if (ctx_id < 0 || ctx_id > spacc->config.num_ctx) 114 - return -EINVAL; 115 - 116 - spin_lock_irqsave(&spacc->ctx_lock, lock_flag); 117 - /* release the base context and contiguous block */ 118 - ncontig = (&spacc->ctx[ctx_id])->ncontig; 119 - for (y = 0; y <= ncontig; y++) { 120 - if ((&spacc->ctx[ctx_id + y])->ref_cnt > 0) 121 - (&spacc->ctx[ctx_id + y])->ref_cnt--; 122 - } 123 - 124 - if ((&spacc->ctx[ctx_id])->ref_cnt == 0) { 125 - (&spacc->ctx[ctx_id])->ncontig = 0; 126 - #ifdef CONFIG_CRYPTO_DEV_SPACC_SECURE_MODE 127 - /* TODO: This driver works in harmony with "normal" kernel 128 - * processes so we release the context all the time 129 - * normally this would be done from a "secure" kernel process 130 - * (trustzone/etc). This hack is so that SPACC.0 131 - * cores can both use the same context space. 132 - */ 133 - writel(ctx_id, spacc->regmap + SPACC_REG_SECURE_RELEASE); 134 - #endif 135 - } 136 - 137 - spin_unlock_irqrestore(&spacc->ctx_lock, lock_flag); 138 - 139 - return CRYPTO_OK; 140 - } 141 - 142 - /* Job manager: This will reset all job data, pointers, etc */ 143 - void spacc_job_init_all(struct spacc_device *spacc) 144 - { 145 - int x; 146 - struct spacc_job *job; 147 - 148 - for (x = 0; x < (SPACC_MAX_JOBS); x++) { 149 - job = &spacc->job[x]; 150 - memset(job, 0, sizeof(struct spacc_job)); 151 - 152 - job->job_swid = SPACC_JOB_IDX_UNUSED; 153 - job->job_used = SPACC_JOB_IDX_UNUSED; 154 - spacc->job_lookup[x] = SPACC_JOB_IDX_UNUSED; 155 - } 156 - } 157 - 158 - /* get a new job id and use a specific ctx_idx or -1 for a new one */ 159 - int spacc_job_request(struct spacc_device *spacc, int ctx_idx) 160 - { 161 - int x, ret; 162 - struct spacc_job *job; 163 - unsigned long lock_flag; 164 - 165 - if (!spacc) 166 - return -1; 167 - 168 - spin_lock_irqsave(&spacc->lock, lock_flag); 169 - 170 - /* find the first available job id */ 171 - for (x = 0; x < SPACC_MAX_JOBS; x++) { 172 - job = &spacc->job[x]; 173 - if (job->job_used == SPACC_JOB_IDX_UNUSED) { 174 - job->job_used = x; 175 - break; 176 - } 177 - } 178 - 179 - if (x == SPACC_MAX_JOBS) { 180 - ret = -1; 181 - } else { 182 - /* associate a single context to go with job */ 183 - ret = spacc_ctx_request(spacc, ctx_idx, 1); 184 - if (ret != -1) { 185 - job->ctx_idx = ret; 186 - ret = x; 187 - } 188 - } 189 - 190 - spin_unlock_irqrestore(&spacc->lock, lock_flag); 191 - 192 - return ret; 193 - } 194 - 195 - int spacc_job_release(struct spacc_device *spacc, int job_idx) 196 - { 197 - int ret; 198 - struct spacc_job *job; 199 - unsigned long lock_flag; 200 - 201 - if (!spacc) 202 - return -EINVAL; 203 - 204 - if (job_idx < 0 || job_idx >= SPACC_MAX_JOBS) 205 - return -ENXIO; 206 - 207 - spin_lock_irqsave(&spacc->lock, lock_flag); 208 - 209 - job = &spacc->job[job_idx]; 210 - /* release context that goes with job */ 211 - ret = spacc_ctx_release(spacc, job->ctx_idx); 212 - job->ctx_idx = SPACC_CTX_IDX_UNUSED; 213 - job->job_used = SPACC_JOB_IDX_UNUSED; 214 - /* disable any callback*/ 215 - job->cb = NULL; 216 - 217 - /* NOTE: this leaves ctrl data in memory */ 218 - spin_unlock_irqrestore(&spacc->lock, lock_flag); 219 - 220 - return ret; 221 - } 222 - 223 - int spacc_handle_release(struct spacc_device *spacc, int job_idx) 224 - { 225 - int ret = 0; 226 - struct spacc_job *job; 227 - unsigned long lock_flag; 228 - 229 - if (!spacc) 230 - return -EINVAL; 231 - 232 - if (job_idx < 0 || job_idx >= SPACC_MAX_JOBS) 233 - return -ENXIO; 234 - 235 - spin_lock_irqsave(&spacc->lock, lock_flag); 236 - 237 - job = &spacc->job[job_idx]; 238 - job->job_used = SPACC_JOB_IDX_UNUSED; 239 - job->cb = NULL; /* disable any callback*/ 240 - 241 - /* NOTE: this leaves ctrl data in memory */ 242 - spin_unlock_irqrestore(&spacc->lock, lock_flag); 243 - 244 - return ret; 245 - } 246 - 247 - /* Return a context structure for a job idx or null if invalid */ 248 - struct spacc_ctx *context_lookup_by_job(struct spacc_device *spacc, int job_idx) 249 - { 250 - if (job_idx < 0 || job_idx >= SPACC_MAX_JOBS) 251 - return NULL; 252 - 253 - return &spacc->ctx[(&spacc->job[job_idx])->ctx_idx]; 254 - } 255 - 256 - int spacc_process_jb(struct spacc_device *spacc) 257 - { 258 - int tail, ret; 259 - 260 - /* are there jobs in the buffer? */ 261 - while (spacc->jb_head != spacc->jb_tail) { 262 - tail = spacc->jb_tail; 263 - 264 - if (spacc->job_buffer[tail].active) { 265 - ret = spacc_packet_enqueue_ddt_ex(spacc, 0, 266 - spacc->job_buffer[tail].job_idx, 267 - spacc->job_buffer[tail].src, 268 - spacc->job_buffer[tail].dst, 269 - spacc->job_buffer[tail].proc_sz, 270 - spacc->job_buffer[tail].aad_offset, 271 - spacc->job_buffer[tail].pre_aad_sz, 272 - spacc->job_buffer[tail].post_aad_sz, 273 - spacc->job_buffer[tail].iv_offset, 274 - spacc->job_buffer[tail].prio); 275 - 276 - if (ret != -EBUSY) 277 - spacc->job_buffer[tail].active = 0; 278 - else 279 - return -1; 280 - } 281 - 282 - tail++; 283 - if (tail == SPACC_MAX_JOB_BUFFERS) 284 - tail = 0; 285 - 286 - spacc->jb_tail = tail; 287 - } 288 - 289 - return 0; 290 - } 291 - 292 - /* Write appropriate context data which depends on operation and mode */ 293 - int spacc_write_context(struct spacc_device *spacc, int job_idx, int op, 294 - const unsigned char *key, int ksz, 295 - const unsigned char *iv, int ivsz) 296 - { 297 - int buflen; 298 - int ret = CRYPTO_OK; 299 - unsigned char buf[300]; 300 - struct spacc_ctx *ctx = NULL; 301 - struct spacc_job *job = NULL; 302 - 303 - if (job_idx < 0 || job_idx > SPACC_MAX_JOBS) 304 - return -ENXIO; 305 - 306 - job = &spacc->job[job_idx]; 307 - ctx = context_lookup_by_job(spacc, job_idx); 308 - 309 - if (!job || !ctx) 310 - return -EIO; 311 - 312 - switch (op) { 313 - case SPACC_CRYPTO_OPERATION: 314 - /* get page size and then read so we can do a 315 - * read-modify-write cycle 316 - */ 317 - buflen = MIN(sizeof(buf), 318 - (unsigned int)spacc->config.ciph_page_size); 319 - 320 - pdu_from_dev_s(buf, ctx->ciph_key, buflen >> 2, 321 - spacc->config.spacc_endian); 322 - 323 - switch (job->enc_mode) { 324 - case CRYPTO_MODE_SM4_ECB: 325 - case CRYPTO_MODE_SM4_CBC: 326 - case CRYPTO_MODE_SM4_CFB: 327 - case CRYPTO_MODE_SM4_OFB: 328 - case CRYPTO_MODE_SM4_CTR: 329 - case CRYPTO_MODE_SM4_CCM: 330 - case CRYPTO_MODE_SM4_GCM: 331 - case CRYPTO_MODE_SM4_CS1: 332 - case CRYPTO_MODE_SM4_CS2: 333 - case CRYPTO_MODE_SM4_CS3: 334 - case CRYPTO_MODE_AES_ECB: 335 - case CRYPTO_MODE_AES_CBC: 336 - case CRYPTO_MODE_AES_CS1: 337 - case CRYPTO_MODE_AES_CS2: 338 - case CRYPTO_MODE_AES_CS3: 339 - case CRYPTO_MODE_AES_CFB: 340 - case CRYPTO_MODE_AES_OFB: 341 - case CRYPTO_MODE_AES_CTR: 342 - case CRYPTO_MODE_AES_CCM: 343 - case CRYPTO_MODE_AES_GCM: 344 - write_to_buf(buf, key, 0, ksz, buflen); 345 - if (iv) { 346 - unsigned char one[4] = { 0, 0, 0, 1 }; 347 - unsigned long enc1, enc2; 348 - 349 - enc1 = CRYPTO_MODE_AES_GCM; 350 - enc2 = CRYPTO_MODE_SM4_GCM; 351 - 352 - write_to_buf(buf, iv, 32, ivsz, buflen); 353 - if (ivsz == 12 && 354 - (job->enc_mode == enc1 || 355 - job->enc_mode == enc2)) 356 - write_to_buf(buf, one, 11 * 4, 4, 357 - buflen); 358 - } 359 - break; 360 - case CRYPTO_MODE_SM4_F8: 361 - case CRYPTO_MODE_AES_F8: 362 - if (key) { 363 - write_to_buf(buf, key + ksz, 0, ksz, buflen); 364 - write_to_buf(buf, key, 48, ksz, buflen); 365 - } 366 - write_to_buf(buf, iv, 32, 16, buflen); 367 - break; 368 - case CRYPTO_MODE_SM4_XTS: 369 - case CRYPTO_MODE_AES_XTS: 370 - if (key) { 371 - write_to_buf(buf, key, 0, 372 - ksz >> 1, buflen); 373 - write_to_buf(buf, key + (ksz >> 1), 48, 374 - ksz >> 1, buflen); 375 - /* divide by two since that's 376 - * what we program the hardware 377 - */ 378 - ksz = ksz >> 1; 379 - } 380 - write_to_buf(buf, iv, 32, 16, buflen); 381 - break; 382 - case CRYPTO_MODE_MULTI2_ECB: 383 - case CRYPTO_MODE_MULTI2_CBC: 384 - case CRYPTO_MODE_MULTI2_OFB: 385 - case CRYPTO_MODE_MULTI2_CFB: 386 - write_to_buf(buf, key, 0, ksz, buflen); 387 - write_to_buf(buf, iv, 0x28, ivsz, buflen); 388 - if (ivsz <= 8) { 389 - /*default to 128 rounds*/ 390 - unsigned char rounds[4] = { 0, 0, 0, 128}; 391 - 392 - write_to_buf(buf, rounds, 0x30, 4, buflen); 393 - } 394 - break; 395 - case CRYPTO_MODE_3DES_CBC: 396 - case CRYPTO_MODE_3DES_ECB: 397 - case CRYPTO_MODE_DES_CBC: 398 - case CRYPTO_MODE_DES_ECB: 399 - write_to_buf(buf, iv, 0, 8, buflen); 400 - write_to_buf(buf, key, 8, ksz, buflen); 401 - break; 402 - case CRYPTO_MODE_KASUMI_ECB: 403 - case CRYPTO_MODE_KASUMI_F8: 404 - write_to_buf(buf, iv, 16, 8, buflen); 405 - write_to_buf(buf, key, 0, 16, buflen); 406 - break; 407 - case CRYPTO_MODE_SNOW3G_UEA2: 408 - case CRYPTO_MODE_ZUC_UEA3: 409 - write_to_buf(buf, key, 0, 32, buflen); 410 - break; 411 - case CRYPTO_MODE_CHACHA20_STREAM: 412 - case CRYPTO_MODE_CHACHA20_POLY1305: 413 - write_to_buf(buf, key, 0, ksz, buflen); 414 - write_to_buf(buf, iv, 32, ivsz, buflen); 415 - break; 416 - case CRYPTO_MODE_NULL: 417 - break; 418 - } 419 - 420 - if (key) { 421 - job->ckey_sz = SPACC_SET_CIPHER_KEY_SZ(ksz); 422 - job->first_use = 1; 423 - } 424 - pdu_to_dev_s(ctx->ciph_key, buf, buflen >> 2, 425 - spacc->config.spacc_endian); 426 - break; 427 - 428 - case SPACC_HASH_OPERATION: 429 - /* get page size and then read so we can do a 430 - * read-modify-write cycle 431 - */ 432 - buflen = MIN(sizeof(buf), 433 - (u32)spacc->config.hash_page_size); 434 - pdu_from_dev_s(buf, ctx->hash_key, buflen >> 2, 435 - spacc->config.spacc_endian); 436 - 437 - switch (job->hash_mode) { 438 - case CRYPTO_MODE_MAC_XCBC: 439 - case CRYPTO_MODE_MAC_SM4_XCBC: 440 - if (key) { 441 - write_to_buf(buf, key + (ksz - 32), 32, 32, 442 - buflen); 443 - write_to_buf(buf, key, 0, (ksz - 32), 444 - buflen); 445 - job->hkey_sz = SPACC_SET_HASH_KEY_SZ(ksz - 32); 446 - } 447 - break; 448 - case CRYPTO_MODE_HASH_CRC32: 449 - case CRYPTO_MODE_MAC_SNOW3G_UIA2: 450 - case CRYPTO_MODE_MAC_ZUC_UIA3: 451 - if (key) { 452 - write_to_buf(buf, key, 0, ksz, buflen); 453 - job->hkey_sz = SPACC_SET_HASH_KEY_SZ(ksz); 454 - } 455 - break; 456 - case CRYPTO_MODE_MAC_POLY1305: 457 - write_to_buf(buf, key, 0, ksz, buflen); 458 - write_to_buf(buf, iv, 32, ivsz, buflen); 459 - break; 460 - case CRYPTO_MODE_HASH_CSHAKE128: 461 - case CRYPTO_MODE_HASH_CSHAKE256: 462 - /* use "iv" and "key" to */ 463 - /* pass s-string and n-string */ 464 - write_to_buf(buf, iv, 0, ivsz, buflen); 465 - write_to_buf(buf, key, 466 - spacc->config.string_size, ksz, buflen); 467 - break; 468 - case CRYPTO_MODE_MAC_KMAC128: 469 - case CRYPTO_MODE_MAC_KMAC256: 470 - case CRYPTO_MODE_MAC_KMACXOF128: 471 - case CRYPTO_MODE_MAC_KMACXOF256: 472 - /* use "iv" and "key" to pass s-string & key */ 473 - write_to_buf(buf, iv, 0, ivsz, buflen); 474 - write_to_buf(buf, key, 475 - spacc->config.string_size, ksz, buflen); 476 - job->hkey_sz = SPACC_SET_HASH_KEY_SZ(ksz); 477 - break; 478 - default: 479 - if (key) { 480 - job->hkey_sz = SPACC_SET_HASH_KEY_SZ(ksz); 481 - write_to_buf(buf, key, 0, ksz, buflen); 482 - } 483 - } 484 - pdu_to_dev_s(ctx->hash_key, buf, buflen >> 2, 485 - spacc->config.spacc_endian); 486 - break; 487 - default: 488 - ret = -EINVAL; 489 - } 490 - 491 - return ret; 492 - } 493 - 494 - int spacc_read_context(struct spacc_device *spacc, int job_idx, 495 - int op, unsigned char *key, int ksz, 496 - unsigned char *iv, int ivsz) 497 - { 498 - int buflen; 499 - int ret = CRYPTO_OK; 500 - unsigned char buf[300]; 501 - struct spacc_ctx *ctx = NULL; 502 - struct spacc_job *job = NULL; 503 - 504 - if (job_idx < 0 || job_idx > SPACC_MAX_JOBS) 505 - return -ENXIO; 506 - 507 - job = &spacc->job[job_idx]; 508 - ctx = context_lookup_by_job(spacc, job_idx); 509 - 510 - if (!ctx) 511 - return -EIO; 512 - 513 - switch (op) { 514 - case SPACC_CRYPTO_OPERATION: 515 - buflen = MIN(sizeof(buf), 516 - (u32)spacc->config.ciph_page_size); 517 - pdu_from_dev_s(buf, ctx->ciph_key, buflen >> 2, 518 - spacc->config.spacc_endian); 519 - 520 - switch (job->enc_mode) { 521 - case CRYPTO_MODE_SM4_ECB: 522 - case CRYPTO_MODE_SM4_CBC: 523 - case CRYPTO_MODE_SM4_CFB: 524 - case CRYPTO_MODE_SM4_OFB: 525 - case CRYPTO_MODE_SM4_CTR: 526 - case CRYPTO_MODE_SM4_CCM: 527 - case CRYPTO_MODE_SM4_GCM: 528 - case CRYPTO_MODE_SM4_CS1: 529 - case CRYPTO_MODE_SM4_CS2: 530 - case CRYPTO_MODE_SM4_CS3: 531 - case CRYPTO_MODE_AES_ECB: 532 - case CRYPTO_MODE_AES_CBC: 533 - case CRYPTO_MODE_AES_CS1: 534 - case CRYPTO_MODE_AES_CS2: 535 - case CRYPTO_MODE_AES_CS3: 536 - case CRYPTO_MODE_AES_CFB: 537 - case CRYPTO_MODE_AES_OFB: 538 - case CRYPTO_MODE_AES_CTR: 539 - case CRYPTO_MODE_AES_CCM: 540 - case CRYPTO_MODE_AES_GCM: 541 - read_from_buf(key, buf, 0, ksz, buflen); 542 - read_from_buf(iv, buf, 32, 16, buflen); 543 - break; 544 - case CRYPTO_MODE_CHACHA20_STREAM: 545 - read_from_buf(key, buf, 0, ksz, buflen); 546 - read_from_buf(iv, buf, 32, 16, buflen); 547 - break; 548 - case CRYPTO_MODE_SM4_F8: 549 - case CRYPTO_MODE_AES_F8: 550 - if (key) { 551 - read_from_buf(key + ksz, buf, 0, ksz, buflen); 552 - read_from_buf(key, buf, 48, ksz, buflen); 553 - } 554 - read_from_buf(iv, buf, 32, 16, buflen); 555 - break; 556 - case CRYPTO_MODE_SM4_XTS: 557 - case CRYPTO_MODE_AES_XTS: 558 - if (key) { 559 - read_from_buf(key, buf, 0, ksz >> 1, buflen); 560 - read_from_buf(key + (ksz >> 1), buf, 561 - 48, ksz >> 1, buflen); 562 - } 563 - read_from_buf(iv, buf, 32, 16, buflen); 564 - break; 565 - case CRYPTO_MODE_MULTI2_ECB: 566 - case CRYPTO_MODE_MULTI2_CBC: 567 - case CRYPTO_MODE_MULTI2_OFB: 568 - case CRYPTO_MODE_MULTI2_CFB: 569 - read_from_buf(key, buf, 0, ksz, buflen); 570 - /* Number of rounds at the end of the IV */ 571 - read_from_buf(iv, buf, 0x28, ivsz, buflen); 572 - break; 573 - case CRYPTO_MODE_3DES_CBC: 574 - case CRYPTO_MODE_3DES_ECB: 575 - read_from_buf(iv, buf, 0, 8, buflen); 576 - read_from_buf(key, buf, 8, 24, buflen); 577 - break; 578 - case CRYPTO_MODE_DES_CBC: 579 - case CRYPTO_MODE_DES_ECB: 580 - read_from_buf(iv, buf, 0, 8, buflen); 581 - read_from_buf(key, buf, 8, 8, buflen); 582 - break; 583 - case CRYPTO_MODE_KASUMI_ECB: 584 - case CRYPTO_MODE_KASUMI_F8: 585 - read_from_buf(iv, buf, 16, 8, buflen); 586 - read_from_buf(key, buf, 0, 16, buflen); 587 - break; 588 - case CRYPTO_MODE_SNOW3G_UEA2: 589 - case CRYPTO_MODE_ZUC_UEA3: 590 - read_from_buf(key, buf, 0, 32, buflen); 591 - break; 592 - case CRYPTO_MODE_NULL: 593 - break; 594 - } 595 - break; 596 - 597 - case SPACC_HASH_OPERATION: 598 - buflen = MIN(sizeof(buf), 599 - (u32)spacc->config.hash_page_size); 600 - pdu_from_dev_s(buf, ctx->hash_key, buflen >> 2, 601 - spacc->config.spacc_endian); 602 - 603 - switch (job->hash_mode) { 604 - case CRYPTO_MODE_MAC_XCBC: 605 - case CRYPTO_MODE_MAC_SM4_XCBC: 606 - if (key && ksz <= 64) { 607 - read_from_buf(key + (ksz - 32), buf, 608 - 32, 32, buflen); 609 - read_from_buf(key, buf, 0, ksz - 32, buflen); 610 - } 611 - break; 612 - case CRYPTO_MODE_HASH_CRC32: 613 - read_from_buf(iv, buf, 0, ivsz, buflen); 614 - break; 615 - case CRYPTO_MODE_MAC_SNOW3G_UIA2: 616 - case CRYPTO_MODE_MAC_ZUC_UIA3: 617 - read_from_buf(key, buf, 0, 32, buflen); 618 - break; 619 - default: 620 - read_from_buf(key, buf, 0, ksz, buflen); 621 - } 622 - break; 623 - default: 624 - ret = -EINVAL; 625 - } 626 - 627 - return ret; 628 - } 629 - 630 - /* Context manager: This will reset all reference counts, pointers, etc */ 631 - void spacc_ctx_init_all(struct spacc_device *spacc) 632 - { 633 - int x; 634 - struct spacc_ctx *ctx; 635 - unsigned long lock_flag; 636 - 637 - spin_lock_irqsave(&spacc->ctx_lock, lock_flag); 638 - 639 - /* initialize contexts */ 640 - for (x = 0; x < spacc->config.num_ctx; x++) { 641 - ctx = &spacc->ctx[x]; 642 - 643 - /* sets everything including ref_cnt and ncontig to 0 */ 644 - memset(ctx, 0, sizeof(*ctx)); 645 - 646 - ctx->ciph_key = spacc->regmap + SPACC_CTX_CIPH_KEY + 647 - (x * spacc->config.ciph_page_size); 648 - ctx->hash_key = spacc->regmap + SPACC_CTX_HASH_KEY + 649 - (x * spacc->config.hash_page_size); 650 - } 651 - 652 - spin_unlock_irqrestore(&spacc->ctx_lock, lock_flag); 653 - }
-717
drivers/crypto/dwc-spacc/spacc_skcipher.c
··· 1 - // SPDX-License-Identifier: GPL-2.0 2 - 3 - #include <crypto/ctr.h> 4 - #include <crypto/des.h> 5 - #include <linux/dma-mapping.h> 6 - #include <crypto/scatterwalk.h> 7 - #include <crypto/internal/des.h> 8 - #include <linux/platform_device.h> 9 - 10 - #include "spacc_device.h" 11 - #include "spacc_core.h" 12 - 13 - static LIST_HEAD(spacc_cipher_alg_list); 14 - static DEFINE_MUTEX(spacc_cipher_alg_mutex); 15 - 16 - static struct mode_tab possible_ciphers[] = { 17 - /* {keylen, MODE_TAB_CIPH(name, id, iv_len, blk_len)} */ 18 - 19 - /* SM4 */ 20 - { MODE_TAB_CIPH("cbc(sm4)", SM4_CBC, 16, 16), .keylen[0] = 16, 21 - .chunksize = 16, .walksize = 16, .min_keysize = 16, .max_keysize = 16 }, 22 - { MODE_TAB_CIPH("ecb(sm4)", SM4_ECB, 0, 16), .keylen[0] = 16, 23 - .chunksize = 16, .walksize = 16, .min_keysize = 16, .max_keysize = 16 }, 24 - { MODE_TAB_CIPH("ctr(sm4)", SM4_CTR, 16, 1), .keylen[0] = 16, 25 - .chunksize = 16, .walksize = 16, .min_keysize = 16, .max_keysize = 16 }, 26 - { MODE_TAB_CIPH("xts(sm4)", SM4_XTS, 16, 16), .keylen[0] = 32, 27 - .chunksize = 16, .walksize = 16, .min_keysize = 32, .max_keysize = 32 }, 28 - { MODE_TAB_CIPH("cts(cbc(sm4))", SM4_CS3, 16, 16), .keylen[0] = 16, 29 - .chunksize = 16, .walksize = 16, .min_keysize = 16, .max_keysize = 16 }, 30 - 31 - /* AES */ 32 - { MODE_TAB_CIPH("cbc(aes)", AES_CBC, 16, 16), .keylen = { 16, 24, 32 }, 33 - .chunksize = 16, .walksize = 16, .min_keysize = 16, .max_keysize = 32 }, 34 - { MODE_TAB_CIPH("ecb(aes)", AES_ECB, 0, 16), .keylen = { 16, 24, 32 }, 35 - .chunksize = 16, .walksize = 16, .min_keysize = 16, .max_keysize = 32 }, 36 - { MODE_TAB_CIPH("xts(aes)", AES_XTS, 16, 16), .keylen = { 32, 48, 64 }, 37 - .chunksize = 16, .walksize = 16, .min_keysize = 32, .max_keysize = 64 }, 38 - { MODE_TAB_CIPH("cts(cbc(aes))", AES_CS3, 16, 16), 39 - .keylen = { 16, 24, 32 }, .chunksize = 16, .walksize = 16, 40 - .min_keysize = 16, .max_keysize = 32 }, 41 - { MODE_TAB_CIPH("ctr(aes)", AES_CTR, 16, 1), .keylen = { 16, 24, 32 }, 42 - .chunksize = 16, .walksize = 16, .min_keysize = 16, .max_keysize = 32 }, 43 - 44 - /* CHACHA20 */ 45 - { MODE_TAB_CIPH("chacha20", CHACHA20_STREAM, 16, 1), .keylen[0] = 32, 46 - .chunksize = 64, .walksize = 64, .min_keysize = 32, .max_keysize = 32 }, 47 - 48 - /* DES */ 49 - { MODE_TAB_CIPH("ecb(des)", DES_ECB, 0, 8), .keylen[0] = 8, 50 - .chunksize = 8, .walksize = 8, .min_keysize = 8, .max_keysize = 8}, 51 - { MODE_TAB_CIPH("cbc(des)", DES_CBC, 8, 8), .keylen[0] = 8, 52 - .chunksize = 8, .walksize = 8, .min_keysize = 8, .max_keysize = 8}, 53 - { MODE_TAB_CIPH("ecb(des3_ede)", 3DES_ECB, 0, 8), .keylen[0] = 24, 54 - .chunksize = 8, .walksize = 8, .min_keysize = 24, .max_keysize = 24 }, 55 - { MODE_TAB_CIPH("cbc(des3_ede)", 3DES_CBC, 8, 8), .keylen[0] = 24, 56 - .chunksize = 8, .walksize = 8, .min_keysize = 24, .max_keysize = 24 }, 57 - }; 58 - 59 - static int spacc_skcipher_fallback(unsigned char *name, 60 - struct skcipher_request *req, int enc_dec) 61 - { 62 - int ret = 0; 63 - struct crypto_skcipher *reqtfm = crypto_skcipher_reqtfm(req); 64 - struct spacc_crypto_ctx *tctx = crypto_skcipher_ctx(reqtfm); 65 - struct spacc_crypto_reqctx *ctx = skcipher_request_ctx(req); 66 - 67 - tctx->fb.cipher = crypto_alloc_skcipher(name, 68 - CRYPTO_ALG_TYPE_SKCIPHER, 69 - CRYPTO_ALG_NEED_FALLBACK); 70 - if (IS_ERR(tctx->fb.cipher)) 71 - return PTR_ERR(tctx->fb.cipher); 72 - 73 - crypto_skcipher_set_reqsize(reqtfm, 74 - sizeof(struct spacc_crypto_reqctx) + 75 - crypto_skcipher_reqsize(tctx->fb.cipher)); 76 - ret = crypto_skcipher_setkey(tctx->fb.cipher, tctx->cipher_key, 77 - tctx->key_len); 78 - if (ret) 79 - return ret; 80 - 81 - skcipher_request_set_tfm(&ctx->fb.cipher_req, tctx->fb.cipher); 82 - skcipher_request_set_crypt(&ctx->fb.cipher_req, req->src, req->dst, 83 - req->cryptlen, req->iv); 84 - 85 - if (enc_dec) 86 - ret = crypto_skcipher_decrypt(&ctx->fb.cipher_req); 87 - else 88 - ret = crypto_skcipher_encrypt(&ctx->fb.cipher_req); 89 - 90 - crypto_free_skcipher(tctx->fb.cipher); 91 - tctx->fb.cipher = NULL; 92 - 93 - kfree(tctx->cipher_key); 94 - tctx->cipher_key = NULL; 95 - 96 - return ret; 97 - } 98 - 99 - static void spacc_cipher_cleanup_dma(struct device *dev, 100 - struct skcipher_request *req) 101 - { 102 - struct spacc_crypto_reqctx *ctx = skcipher_request_ctx(req); 103 - struct spacc_crypto_ctx *tctx = ctx->ccb.tctx; 104 - 105 - if (req->dst != req->src) { 106 - if (ctx->src_nents) { 107 - dma_unmap_sg(dev, req->src, ctx->src_nents, 108 - DMA_TO_DEVICE); 109 - pdu_ddt_free(&ctx->src); 110 - } 111 - 112 - if (ctx->dst_nents) { 113 - dma_unmap_sg(dev, req->dst, ctx->dst_nents, 114 - DMA_FROM_DEVICE); 115 - pdu_ddt_free(&ctx->dst); 116 - } 117 - } else { 118 - if (ctx->src_nents) { 119 - dma_unmap_sg(dev, req->src, ctx->src_nents, 120 - DMA_TO_DEVICE); 121 - pdu_ddt_free(&ctx->src); 122 - } 123 - } 124 - 125 - kfree(tctx->cipher_key); 126 - tctx->cipher_key = NULL; 127 - } 128 - 129 - static void spacc_cipher_cb(void *spacc, void *tfm) 130 - { 131 - int err = -1; 132 - struct cipher_cb_data *cb = tfm; 133 - struct spacc_crypto_reqctx *ctx = skcipher_request_ctx(cb->req); 134 - 135 - u32 status_reg = readl(cb->spacc->regmap + SPACC_REG_STATUS); 136 - u32 status_ret = (status_reg >> 24) & 0x03; 137 - 138 - if (ctx->mode == CRYPTO_MODE_DES_CBC || 139 - ctx->mode == CRYPTO_MODE_3DES_CBC) { 140 - spacc_read_context(cb->spacc, cb->tctx->handle, 141 - SPACC_CRYPTO_OPERATION, NULL, 0, 142 - cb->req->iv, 8); 143 - } else if (ctx->mode != CRYPTO_MODE_DES_ECB && 144 - ctx->mode != CRYPTO_MODE_3DES_ECB && 145 - ctx->mode != CRYPTO_MODE_SM4_ECB && 146 - ctx->mode != CRYPTO_MODE_AES_ECB && 147 - ctx->mode != CRYPTO_MODE_SM4_XTS && 148 - ctx->mode != CRYPTO_MODE_KASUMI_ECB) { 149 - if (status_ret == 0x3) { 150 - err = -EINVAL; 151 - goto CALLBACK_ERR; 152 - } 153 - spacc_read_context(cb->spacc, cb->tctx->handle, 154 - SPACC_CRYPTO_OPERATION, NULL, 0, 155 - cb->req->iv, 16); 156 - } 157 - 158 - if (ctx->mode != CRYPTO_MODE_DES_ECB && 159 - ctx->mode != CRYPTO_MODE_DES_CBC && 160 - ctx->mode != CRYPTO_MODE_3DES_ECB && 161 - ctx->mode != CRYPTO_MODE_3DES_CBC) { 162 - if (status_ret == 0x03) { 163 - err = -EINVAL; 164 - goto CALLBACK_ERR; 165 - } 166 - } 167 - 168 - if (ctx->mode == CRYPTO_MODE_SM4_ECB && status_ret == 0x03) { 169 - err = -EINVAL; 170 - goto CALLBACK_ERR; 171 - } 172 - 173 - if (cb->req->dst != cb->req->src) 174 - dma_sync_sg_for_cpu(cb->tctx->dev, cb->req->dst, ctx->dst_nents, 175 - DMA_FROM_DEVICE); 176 - 177 - err = cb->spacc->job[cb->new_handle].job_err; 178 - 179 - CALLBACK_ERR: 180 - spacc_cipher_cleanup_dma(cb->tctx->dev, cb->req); 181 - spacc_close(cb->spacc, cb->new_handle); 182 - skcipher_request_complete(cb->req, err); 183 - } 184 - 185 - static int spacc_cipher_init_dma(struct device *dev, 186 - struct skcipher_request *req) 187 - { 188 - struct spacc_crypto_reqctx *ctx = skcipher_request_ctx(req); 189 - int rc; 190 - 191 - if (req->src == req->dst) { 192 - rc = spacc_sg_to_ddt(dev, req->src, req->cryptlen, &ctx->src, 193 - DMA_TO_DEVICE); 194 - if (rc < 0) { 195 - pdu_ddt_free(&ctx->src); 196 - return rc; 197 - } 198 - ctx->src_nents = rc; 199 - } else { 200 - rc = spacc_sg_to_ddt(dev, req->src, req->cryptlen, &ctx->src, 201 - DMA_TO_DEVICE); 202 - if (rc < 0) { 203 - pdu_ddt_free(&ctx->src); 204 - return rc; 205 - } 206 - ctx->src_nents = rc; 207 - 208 - rc = spacc_sg_to_ddt(dev, req->dst, req->cryptlen, &ctx->dst, 209 - DMA_FROM_DEVICE); 210 - if (rc < 0) { 211 - pdu_ddt_free(&ctx->dst); 212 - return rc; 213 - } 214 - ctx->dst_nents = rc; 215 - } 216 - 217 - return 0; 218 - } 219 - 220 - static int spacc_cipher_cra_init(struct crypto_tfm *tfm) 221 - { 222 - struct spacc_crypto_ctx *tctx = crypto_tfm_ctx(tfm); 223 - const struct spacc_alg *salg = spacc_tfm_skcipher(tfm); 224 - 225 - tctx->keylen = 0; 226 - tctx->cipher_key = NULL; 227 - tctx->handle = -1; 228 - tctx->ctx_valid = false; 229 - tctx->dev = get_device(salg->dev[0]); 230 - 231 - crypto_skcipher_set_reqsize(__crypto_skcipher_cast(tfm), 232 - sizeof(struct spacc_crypto_reqctx)); 233 - 234 - return 0; 235 - } 236 - 237 - static void spacc_cipher_cra_exit(struct crypto_tfm *tfm) 238 - { 239 - struct spacc_crypto_ctx *tctx = crypto_tfm_ctx(tfm); 240 - struct spacc_priv *priv = dev_get_drvdata(tctx->dev); 241 - 242 - 243 - if (tctx->handle >= 0) 244 - spacc_close(&priv->spacc, tctx->handle); 245 - 246 - put_device(tctx->dev); 247 - } 248 - 249 - 250 - static int spacc_check_keylen(const struct spacc_alg *salg, unsigned int keylen) 251 - { 252 - unsigned int i; 253 - 254 - for (i = 0; i < ARRAY_SIZE(salg->mode->keylen); i++) 255 - if (salg->mode->keylen[i] == keylen) 256 - return 0; 257 - 258 - return -EINVAL; 259 - } 260 - 261 - static int spacc_cipher_setkey(struct crypto_skcipher *tfm, const u8 *key, 262 - unsigned int keylen) 263 - { 264 - int ret = 0, rc = 0, err; 265 - const struct spacc_alg *salg = spacc_tfm_skcipher(&tfm->base); 266 - struct spacc_crypto_ctx *tctx = crypto_skcipher_ctx(tfm); 267 - struct spacc_priv *priv = dev_get_drvdata(tctx->dev); 268 - struct spacc_crypto_reqctx *ctx = crypto_skcipher_ctx(tfm); 269 - 270 - err = spacc_check_keylen(salg, keylen); 271 - if (err) 272 - return err; 273 - 274 - ctx->mode = salg->mode->id; 275 - tctx->key_len = keylen; 276 - tctx->cipher_key = kmalloc(keylen, GFP_KERNEL); 277 - memcpy(tctx->cipher_key, key, keylen); 278 - 279 - if (tctx->handle >= 0) { 280 - spacc_close(&priv->spacc, tctx->handle); 281 - put_device(tctx->dev); 282 - tctx->handle = -1; 283 - tctx->dev = NULL; 284 - } 285 - 286 - priv = NULL; 287 - priv = dev_get_drvdata(salg->dev[0]); 288 - tctx->dev = get_device(salg->dev[0]); 289 - ret = spacc_isenabled(&priv->spacc, salg->mode->id, 290 - keylen); 291 - if (ret) 292 - tctx->handle = spacc_open(&priv->spacc, salg->mode->id, 293 - CRYPTO_MODE_NULL, -1, 0, 294 - spacc_cipher_cb, tfm); 295 - 296 - if (tctx->handle < 0) { 297 - put_device(salg->dev[0]); 298 - dev_dbg(salg->dev[0], "failed to open SPAcc context\n"); 299 - return -EINVAL; 300 - } 301 - 302 - /* Weak key Implementation for DES_ECB */ 303 - if (salg->mode->id == CRYPTO_MODE_DES_ECB) { 304 - err = verify_skcipher_des_key(tfm, key); 305 - if (err) 306 - return -EINVAL; 307 - } 308 - 309 - if (salg->mode->id == CRYPTO_MODE_SM4_F8 || 310 - salg->mode->id == CRYPTO_MODE_AES_F8) { 311 - /* f8 mode requires an IV of 128-bits and a key-salt mask, 312 - * equivalent in size to the key. 313 - * AES-F8 or SM4-F8 mode has a SALTKEY prepended to the base 314 - * key. 315 - */ 316 - rc = spacc_write_context(&priv->spacc, tctx->handle, 317 - SPACC_CRYPTO_OPERATION, key, 16, 318 - NULL, 0); 319 - } else { 320 - rc = spacc_write_context(&priv->spacc, tctx->handle, 321 - SPACC_CRYPTO_OPERATION, key, keylen, 322 - NULL, 0); 323 - } 324 - 325 - if (rc < 0) { 326 - dev_dbg(salg->dev[0], "failed with SPAcc write context\n"); 327 - return -EINVAL; 328 - } 329 - 330 - return 0; 331 - } 332 - 333 - static int spacc_cipher_process(struct skcipher_request *req, int enc_dec) 334 - { 335 - u8 ivc1[16]; 336 - unsigned char *name; 337 - unsigned int len = 0; 338 - u32 num_iv = 0, diff; 339 - u64 num_iv64 = 0, diff64; 340 - unsigned char chacha20_iv[16]; 341 - int rc = 0, ret = 0, i = 0, j = 0; 342 - struct crypto_skcipher *reqtfm = crypto_skcipher_reqtfm(req); 343 - struct spacc_crypto_ctx *tctx = crypto_skcipher_ctx(reqtfm); 344 - struct spacc_crypto_reqctx *ctx = skcipher_request_ctx(req); 345 - struct spacc_priv *priv = dev_get_drvdata(tctx->dev); 346 - const struct spacc_alg *salg = spacc_tfm_skcipher(&reqtfm->base); 347 - struct spacc_device *device_h = &priv->spacc; 348 - 349 - len = ctx->spacc_cipher_cryptlen / 16; 350 - 351 - if (req->cryptlen == 0) { 352 - if (salg->mode->id == CRYPTO_MODE_SM4_CS3 || 353 - salg->mode->id == CRYPTO_MODE_SM4_XTS || 354 - salg->mode->id == CRYPTO_MODE_AES_XTS || 355 - salg->mode->id == CRYPTO_MODE_AES_CS3) 356 - return -EINVAL; 357 - else 358 - return 0; 359 - } 360 - 361 - /* Given IV - <1st 4-bytes as counter value> 362 - * <last 12-bytes as nonce> 363 - * Reversing the order of nonce & counter as, 364 - * <1st 12-bytes as nonce> 365 - * <last 4-bytes as counter> 366 - * and then write to HW context, 367 - * ex: 368 - * Given IV - 2a000000000000000000000000000002 369 - * Reverse order - 0000000000000000000000020000002a 370 - */ 371 - if (salg->mode->id == CRYPTO_MODE_CHACHA20_STREAM) { 372 - for (i = 4; i < 16; i++) { 373 - chacha20_iv[j] = req->iv[i]; 374 - j++; 375 - } 376 - 377 - j = j + 3; 378 - 379 - for (i = 0; i <= 3; i++) { 380 - chacha20_iv[j] = req->iv[i]; 381 - j--; 382 - } 383 - memcpy(req->iv, chacha20_iv, 16); 384 - } 385 - 386 - if (salg->mode->id == CRYPTO_MODE_SM4_CFB) { 387 - if (req->cryptlen % 16 != 0) { 388 - name = salg->calg->cra_name; 389 - ret = spacc_skcipher_fallback(name, req, enc_dec); 390 - return ret; 391 - } 392 - } 393 - 394 - if (salg->mode->id == CRYPTO_MODE_SM4_XTS || 395 - salg->mode->id == CRYPTO_MODE_SM4_CS3 || 396 - salg->mode->id == CRYPTO_MODE_AES_XTS || 397 - salg->mode->id == CRYPTO_MODE_AES_CS3) { 398 - if (req->cryptlen == 16) { 399 - name = salg->calg->cra_name; 400 - ret = spacc_skcipher_fallback(name, req, enc_dec); 401 - return ret; 402 - } 403 - } 404 - 405 - if (salg->mode->id == CRYPTO_MODE_AES_CTR || 406 - salg->mode->id == CRYPTO_MODE_SM4_CTR) { 407 - /* copy the IV to local buffer */ 408 - for (i = 0; i < 16; i++) 409 - ivc1[i] = req->iv[i]; 410 - 411 - /* 64-bit counter width */ 412 - if (readl(device_h->regmap + SPACC_REG_VERSION_EXT_3) & (0x3)) { 413 - 414 - for (i = 8; i < 16; i++) { 415 - num_iv64 <<= 8; 416 - num_iv64 |= ivc1[i]; 417 - } 418 - 419 - diff64 = SPACC_CTR_IV_MAX64 - num_iv64; 420 - 421 - if (len > diff64) { 422 - name = salg->calg->cra_name; 423 - ret = spacc_skcipher_fallback(name, 424 - req, enc_dec); 425 - return ret; 426 - } 427 - /* 32-bit counter width */ 428 - } else if (readl(device_h->regmap + SPACC_REG_VERSION_EXT_3) 429 - & (0x2)) { 430 - 431 - for (i = 12; i < 16; i++) { 432 - num_iv <<= 8; 433 - num_iv |= ivc1[i]; 434 - } 435 - 436 - diff = SPACC_CTR_IV_MAX32 - num_iv; 437 - 438 - if (len > diff) { 439 - name = salg->calg->cra_name; 440 - ret = spacc_skcipher_fallback(name, 441 - req, enc_dec); 442 - return ret; 443 - } 444 - /* 16-bit counter width */ 445 - } else if (readl(device_h->regmap + SPACC_REG_VERSION_EXT_3) 446 - & (0x1)) { 447 - 448 - for (i = 14; i < 16; i++) { 449 - num_iv <<= 8; 450 - num_iv |= ivc1[i]; 451 - } 452 - 453 - diff = SPACC_CTR_IV_MAX16 - num_iv; 454 - 455 - if (len > diff) { 456 - name = salg->calg->cra_name; 457 - ret = spacc_skcipher_fallback(name, 458 - req, enc_dec); 459 - return ret; 460 - } 461 - /* 8-bit counter width */ 462 - } else if ((readl(device_h->regmap + SPACC_REG_VERSION_EXT_3) 463 - & 0x7) == 0) { 464 - 465 - for (i = 15; i < 16; i++) { 466 - num_iv <<= 8; 467 - num_iv |= ivc1[i]; 468 - } 469 - 470 - diff = SPACC_CTR_IV_MAX8 - num_iv; 471 - 472 - if (len > diff) { 473 - name = salg->calg->cra_name; 474 - ret = spacc_skcipher_fallback(name, 475 - req, enc_dec); 476 - return ret; 477 - } 478 - } 479 - } 480 - 481 - if (salg->mode->id == CRYPTO_MODE_DES_CBC || 482 - salg->mode->id == CRYPTO_MODE_3DES_CBC) 483 - rc = spacc_write_context(&priv->spacc, tctx->handle, 484 - SPACC_CRYPTO_OPERATION, NULL, 0, 485 - req->iv, 8); 486 - else if (salg->mode->id != CRYPTO_MODE_DES_ECB && 487 - salg->mode->id != CRYPTO_MODE_3DES_ECB && 488 - salg->mode->id != CRYPTO_MODE_SM4_ECB && 489 - salg->mode->id != CRYPTO_MODE_AES_ECB && 490 - salg->mode->id != CRYPTO_MODE_KASUMI_ECB) 491 - rc = spacc_write_context(&priv->spacc, tctx->handle, 492 - SPACC_CRYPTO_OPERATION, NULL, 0, 493 - req->iv, 16); 494 - 495 - if (rc < 0) 496 - pr_err("ERR: spacc_write_context\n"); 497 - 498 - /* Initialize the DMA */ 499 - rc = spacc_cipher_init_dma(tctx->dev, req); 500 - 501 - ctx->ccb.new_handle = spacc_clone_handle(&priv->spacc, tctx->handle, 502 - &ctx->ccb); 503 - if (ctx->ccb.new_handle < 0) { 504 - spacc_cipher_cleanup_dma(tctx->dev, req); 505 - dev_dbg(salg->dev[0], "failed to clone handle\n"); 506 - return -EINVAL; 507 - } 508 - 509 - /* copying the data to clone handle */ 510 - ctx->ccb.tctx = tctx; 511 - ctx->ccb.ctx = ctx; 512 - ctx->ccb.req = req; 513 - ctx->ccb.spacc = &priv->spacc; 514 - 515 - if (salg->mode->id == CRYPTO_MODE_SM4_CS3) { 516 - int handle = ctx->ccb.new_handle; 517 - 518 - if (handle < 0 || handle > SPACC_MAX_JOBS) 519 - return -ENXIO; 520 - 521 - device_h->job[handle].auxinfo_cs_mode = 3; 522 - } 523 - 524 - if (enc_dec) { /* for decrypt */ 525 - rc = spacc_set_operation(&priv->spacc, ctx->ccb.new_handle, 1, 526 - ICV_IGNORE, IP_ICV_IGNORE, 0, 0, 0); 527 - spacc_set_key_exp(&priv->spacc, ctx->ccb.new_handle); 528 - } else { /* for encrypt */ 529 - rc = spacc_set_operation(&priv->spacc, ctx->ccb.new_handle, 0, 530 - ICV_IGNORE, IP_ICV_IGNORE, 0, 0, 0); 531 - } 532 - 533 - rc = spacc_packet_enqueue_ddt(&priv->spacc, ctx->ccb.new_handle, 534 - &ctx->src, 535 - (req->dst == req->src) ? &ctx->src : 536 - &ctx->dst, 537 - req->cryptlen, 538 - 0, 0, 0, 0, 0); 539 - if (rc < 0) { 540 - spacc_cipher_cleanup_dma(tctx->dev, req); 541 - spacc_close(&priv->spacc, ctx->ccb.new_handle); 542 - 543 - if (rc != -EBUSY && rc < 0) { 544 - dev_err(tctx->dev, 545 - "failed to enqueue job, ERR: %d\n", rc); 546 - return rc; 547 - } else if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { 548 - return -EBUSY; 549 - } 550 - } 551 - 552 - priv->spacc.job[tctx->handle].first_use = 0; 553 - priv->spacc.job[tctx->handle].ctrl &= 554 - ~(1UL << priv->spacc.config.ctrl_map[SPACC_CTRL_KEY_EXP]); 555 - 556 - return -EINPROGRESS; 557 - } 558 - 559 - static int spacc_cipher_encrypt(struct skcipher_request *req) 560 - { 561 - int rv = 0; 562 - struct spacc_crypto_reqctx *ctx = skcipher_request_ctx(req); 563 - 564 - ctx->spacc_cipher_cryptlen = req->cryptlen; 565 - 566 - /* enc_dec - 0(encrypt), 1(decrypt) */ 567 - rv = spacc_cipher_process(req, 0); 568 - 569 - return rv; 570 - } 571 - 572 - static int spacc_cipher_decrypt(struct skcipher_request *req) 573 - { 574 - int rv = 0; 575 - struct spacc_crypto_reqctx *ctx = skcipher_request_ctx(req); 576 - 577 - ctx->spacc_cipher_cryptlen = req->cryptlen; 578 - 579 - /* enc_dec - 0(encrypt), 1(decrypt) */ 580 - rv = spacc_cipher_process(req, 1); 581 - 582 - return rv; 583 - } 584 - 585 - static struct skcipher_alg spacc_skcipher_alg = { 586 - .setkey = spacc_cipher_setkey, 587 - .encrypt = spacc_cipher_encrypt, 588 - .decrypt = spacc_cipher_decrypt, 589 - /* 590 - * Chunksize: Equal to the block size except for stream cipher 591 - * such as CTR where it is set to the underlying block size. 592 - * 593 - * Walksize: Equal to the chunk size except in cases where the 594 - * algorithm is considerably more efficient if it can operate on 595 - * multiple chunks in parallel. Should be a multiple of chunksize. 596 - */ 597 - .min_keysize = 16, 598 - .max_keysize = 64, 599 - .ivsize = 16, 600 - .chunksize = 16, 601 - .walksize = 16, 602 - .base = { 603 - .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | 604 - CRYPTO_ALG_ASYNC | 605 - CRYPTO_ALG_ALLOCATES_MEMORY | 606 - CRYPTO_ALG_NEED_FALLBACK, 607 - .cra_blocksize = 16, 608 - .cra_ctxsize = sizeof(struct spacc_crypto_ctx), 609 - .cra_priority = 300, 610 - .cra_init = spacc_cipher_cra_init, 611 - .cra_exit = spacc_cipher_cra_exit, 612 - .cra_module = THIS_MODULE, 613 - }, 614 - }; 615 - 616 - static void spacc_init_calg(struct crypto_alg *calg, 617 - const struct mode_tab *mode) 618 - { 619 - 620 - strscpy(calg->cra_name, mode->name, sizeof(mode->name) - 1); 621 - calg->cra_name[sizeof(mode->name) - 1] = '\0'; 622 - 623 - strscpy(calg->cra_driver_name, "spacc-"); 624 - strcat(calg->cra_driver_name, mode->name); 625 - calg->cra_driver_name[sizeof(calg->cra_driver_name) - 1] = '\0'; 626 - calg->cra_blocksize = mode->blocklen; 627 - } 628 - 629 - static int spacc_register_cipher(struct spacc_alg *salg, 630 - unsigned int algo_idx) 631 - { 632 - int rc; 633 - 634 - salg->calg = &salg->alg.skcipher.base; 635 - salg->alg.skcipher = spacc_skcipher_alg; 636 - 637 - /* this function will assign mode->name to calg->cra_name & 638 - * calg->cra_driver_name 639 - */ 640 - spacc_init_calg(salg->calg, salg->mode); 641 - salg->alg.skcipher.ivsize = salg->mode->ivlen; 642 - salg->alg.skcipher.base.cra_blocksize = salg->mode->blocklen; 643 - 644 - salg->alg.skcipher.chunksize = possible_ciphers[algo_idx].chunksize; 645 - salg->alg.skcipher.walksize = possible_ciphers[algo_idx].walksize; 646 - salg->alg.skcipher.min_keysize = possible_ciphers[algo_idx].min_keysize; 647 - salg->alg.skcipher.max_keysize = possible_ciphers[algo_idx].max_keysize; 648 - 649 - rc = crypto_register_skcipher(&salg->alg.skcipher); 650 - if (rc < 0) 651 - return rc; 652 - 653 - mutex_lock(&spacc_cipher_alg_mutex); 654 - list_add(&salg->list, &spacc_cipher_alg_list); 655 - mutex_unlock(&spacc_cipher_alg_mutex); 656 - 657 - return 0; 658 - } 659 - 660 - int probe_ciphers(struct platform_device *spacc_pdev) 661 - { 662 - int rc; 663 - unsigned int i, y; 664 - int registered = 0; 665 - struct spacc_alg *salg; 666 - struct spacc_priv *priv = dev_get_drvdata(&spacc_pdev->dev); 667 - 668 - for (i = 0; i < ARRAY_SIZE(possible_ciphers); i++) 669 - possible_ciphers[i].valid = 0; 670 - 671 - for (i = 0; i < ARRAY_SIZE(possible_ciphers) && 672 - (possible_ciphers[i].valid == 0); i++) { 673 - for (y = 0; y < 3; y++) { 674 - if (spacc_isenabled(&priv->spacc, 675 - possible_ciphers[i].id & 0xFF, 676 - possible_ciphers[i].keylen[y])) { 677 - salg = kmalloc(sizeof(*salg), GFP_KERNEL); 678 - if (!salg) 679 - return -ENOMEM; 680 - 681 - salg->mode = &possible_ciphers[i]; 682 - salg->dev[0] = &spacc_pdev->dev; 683 - 684 - if (possible_ciphers[i].valid == 0) { 685 - rc = spacc_register_cipher(salg, i); 686 - if (rc < 0) { 687 - kfree(salg); 688 - continue; 689 - } 690 - } 691 - dev_dbg(&spacc_pdev->dev, "registered %s\n", 692 - possible_ciphers[i].name); 693 - registered++; 694 - possible_ciphers[i].valid = 1; 695 - } 696 - } 697 - } 698 - 699 - return registered; 700 - } 701 - 702 - int spacc_unregister_cipher_algs(void) 703 - { 704 - struct spacc_alg *salg, *tmp; 705 - 706 - mutex_lock(&spacc_cipher_alg_mutex); 707 - 708 - list_for_each_entry_safe(salg, tmp, &spacc_cipher_alg_list, list) { 709 - crypto_unregister_skcipher(&salg->alg.skcipher); 710 - list_del(&salg->list); 711 - kfree(salg); 712 - } 713 - 714 - mutex_unlock(&spacc_cipher_alg_mutex); 715 - 716 - return 0; 717 - }