Merge remote-tracking branches 'asoc/topic/inntel', 'asoc/topic/input', 'asoc/topic/max98504' and 'asoc/topic/nau8825' into asoc-next

+9 -4

drivers/input/misc/arizona-haptics.c

··· 37 37 struct arizona_haptics, 38 38 work); 39 39 struct arizona *arizona = haptics->arizona; 40 + struct snd_soc_component *component = 41 + snd_soc_dapm_to_component(arizona->dapm); 40 42 int ret; 41 43 42 44 if (!haptics->arizona->dapm) { ··· 68 66 return; 69 67 } 70 68 71 - ret = snd_soc_dapm_enable_pin(arizona->dapm, "HAPTICS"); 69 + ret = snd_soc_component_enable_pin(component, "HAPTICS"); 72 70 if (ret != 0) { 73 71 dev_err(arizona->dev, "Failed to start HAPTICS: %d\n", 74 72 ret); ··· 83 81 } 84 82 } else { 85 83 /* This disable sequence will be a noop if already enabled */ 86 - ret = snd_soc_dapm_disable_pin(arizona->dapm, "HAPTICS"); 84 + ret = snd_soc_component_disable_pin(component, "HAPTICS"); 87 85 if (ret != 0) { 88 86 dev_err(arizona->dev, "Failed to disable HAPTICS: %d\n", 89 87 ret); ··· 142 140 static void arizona_haptics_close(struct input_dev *input) 143 141 { 144 142 struct arizona_haptics *haptics = input_get_drvdata(input); 143 + struct snd_soc_component *component; 145 144 146 145 cancel_work_sync(&haptics->work); 147 146 148 - if (haptics->arizona->dapm) 149 - snd_soc_dapm_disable_pin(haptics->arizona->dapm, "HAPTICS"); 147 + if (haptics->arizona->dapm) { 148 + component = snd_soc_dapm_to_component(haptics->arizona->dapm); 149 + snd_soc_component_disable_pin(component, "HAPTICS"); 150 + } 150 151 } 151 152 152 153 static int arizona_haptics_probe(struct platform_device *pdev)

+1

sound/soc/codecs/Kconfig

··· 85 85 select SND_SOC_MAX98095 if I2C 86 86 select SND_SOC_MAX98357A if GPIOLIB 87 87 select SND_SOC_MAX98371 if I2C 88 + select SND_SOC_MAX98504 if I2C 88 89 select SND_SOC_MAX9867 if I2C 89 90 select SND_SOC_MAX98925 if I2C 90 91 select SND_SOC_MAX98926 if I2C

+125 -17

sound/soc/codecs/nau8825.c

··· 43 43 #define GAIN_AUGMENT 22500 44 44 #define SIDETONE_BASE 207000 45 45 46 + /* the maximum frequency of CLK_ADC and CLK_DAC */ 47 + #define CLK_DA_AD_MAX 6144000 46 48 47 49 static int nau8825_configure_sysclk(struct nau8825 *nau8825, 48 50 int clk_id, unsigned int freq); ··· 95 93 { 2, 0x1 }, 96 94 { 4, 0x2 }, 97 95 { 8, 0x3 }, 96 + }; 97 + 98 + /* over sampling rate */ 99 + struct nau8825_osr_attr { 100 + unsigned int osr; 101 + unsigned int clk_src; 102 + }; 103 + 104 + static const struct nau8825_osr_attr osr_dac_sel[] = { 105 + { 64, 2 }, /* OSR 64, SRC 1/4 */ 106 + { 256, 0 }, /* OSR 256, SRC 1 */ 107 + { 128, 1 }, /* OSR 128, SRC 1/2 */ 108 + { 0, 0 }, 109 + { 32, 3 }, /* OSR 32, SRC 1/8 */ 110 + }; 111 + 112 + static const struct nau8825_osr_attr osr_adc_sel[] = { 113 + { 32, 3 }, /* OSR 32, SRC 1/8 */ 114 + { 64, 2 }, /* OSR 64, SRC 1/4 */ 115 + { 128, 1 }, /* OSR 128, SRC 1/2 */ 116 + { 256, 0 }, /* OSR 256, SRC 1 */ 98 117 }; 99 118 100 119 static const struct reg_default nau8825_reg_defaults[] = { ··· 1202 1179 {"HPOR", NULL, "Class G"}, 1203 1180 }; 1204 1181 1182 + static int nau8825_clock_check(struct nau8825 *nau8825, 1183 + int stream, int rate, int osr) 1184 + { 1185 + int osrate; 1186 + 1187 + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1188 + if (osr >= ARRAY_SIZE(osr_dac_sel)) 1189 + return -EINVAL; 1190 + osrate = osr_dac_sel[osr].osr; 1191 + } else { 1192 + if (osr >= ARRAY_SIZE(osr_adc_sel)) 1193 + return -EINVAL; 1194 + osrate = osr_adc_sel[osr].osr; 1195 + } 1196 + 1197 + if (!osrate || rate * osr > CLK_DA_AD_MAX) { 1198 + dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); 1199 + return -EINVAL; 1200 + } 1201 + 1202 + return 0; 1203 + } 1204 + 1205 1205 static int nau8825_hw_params(struct snd_pcm_substream *substream, 1206 1206 struct snd_pcm_hw_params *params, 1207 1207 struct snd_soc_dai *dai) 1208 1208 { 1209 1209 struct snd_soc_codec *codec = dai->codec; 1210 1210 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); 1211 - unsigned int val_len = 0; 1211 + unsigned int val_len = 0, osr; 1212 1212 1213 - nau8825_sema_acquire(nau8825, 2 * HZ); 1213 + nau8825_sema_acquire(nau8825, 3 * HZ); 1214 + 1215 + /* CLK_DAC or CLK_ADC = OSR * FS 1216 + * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 1217 + * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1218 + * values must be selected such that the maximum frequency is less 1219 + * than 6.144 MHz. 1220 + */ 1221 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1222 + regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr); 1223 + osr &= NAU8825_DAC_OVERSAMPLE_MASK; 1224 + if (nau8825_clock_check(nau8825, substream->stream, 1225 + params_rate(params), osr)) 1226 + return -EINVAL; 1227 + regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1228 + NAU8825_CLK_DAC_SRC_MASK, 1229 + osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT); 1230 + } else { 1231 + regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr); 1232 + osr &= NAU8825_ADC_SYNC_DOWN_MASK; 1233 + if (nau8825_clock_check(nau8825, substream->stream, 1234 + params_rate(params), osr)) 1235 + return -EINVAL; 1236 + regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1237 + NAU8825_CLK_ADC_SRC_MASK, 1238 + osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT); 1239 + } 1214 1240 1215 1241 switch (params_width(params)) { 1216 1242 case 16: ··· 1293 1221 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); 1294 1222 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1295 1223 1296 - nau8825_sema_acquire(nau8825, 2 * HZ); 1224 + nau8825_sema_acquire(nau8825, 3 * HZ); 1297 1225 1298 1226 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1299 1227 case SND_SOC_DAIFMT_CBM_CFM: ··· 1846 1774 * (audible hiss). Set it to something better. 1847 1775 */ 1848 1776 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE, 1849 - NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128); 1777 + NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN, 1778 + NAU8825_ADC_SYNC_DOWN_64); 1850 1779 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 1851 - NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128); 1780 + NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64); 1852 1781 /* Disable DACR/L power */ 1853 1782 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, 1854 1783 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, ··· 1884 1811 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); 1885 1812 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 1886 1813 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); 1814 + /* Disable short Frame Sync detection logic */ 1815 + regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT, 1816 + NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET); 1887 1817 } 1888 1818 1889 1819 static const struct regmap_config nau8825_regmap_config = { ··· 1995 1919 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1996 1920 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK, 1997 1921 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src); 1922 + /* Make DSP operate at high speed for better performance. */ 1998 1923 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 1999 - NAU8825_FLL_RATIO_MASK, fll_param->ratio); 1924 + NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK, 1925 + fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT)); 2000 1926 /* FLL 16-bit fractional input */ 2001 1927 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac); 2002 1928 /* FLL 10-bit integer input */ ··· 2014 1936 regmap_update_bits(nau8825->regmap, 2015 1937 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); 2016 1938 if (fll_param->fll_frac) { 1939 + /* set FLL loop filter enable and cutoff frequency at 500Khz */ 2017 1940 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2018 1941 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2019 1942 NAU8825_FLL_FTR_SW_MASK, 2020 1943 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2021 1944 NAU8825_FLL_FTR_SW_FILTER); 2022 1945 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2023 - NAU8825_SDM_EN, NAU8825_SDM_EN); 1946 + NAU8825_SDM_EN | NAU8825_CUTOFF500, 1947 + NAU8825_SDM_EN | NAU8825_CUTOFF500); 2024 1948 } else { 1949 + /* disable FLL loop filter and cutoff frequency */ 2025 1950 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2026 1951 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2027 1952 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU); 2028 - regmap_update_bits(nau8825->regmap, 2029 - NAU8825_REG_FLL6, NAU8825_SDM_EN, 0); 1953 + regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 1954 + NAU8825_SDM_EN | NAU8825_CUTOFF500, 0); 2030 1955 } 2031 1956 } 2032 1957 ··· 2095 2014 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); 2096 2015 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2097 2016 NAU8825_DCO_EN, 0); 2017 + /* Make DSP operate as default setting for power saving. */ 2018 + regmap_update_bits(regmap, NAU8825_REG_FLL1, 2019 + NAU8825_ICTRL_LATCH_MASK, 0); 2098 2020 } 2099 2021 2100 2022 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, ··· 2122 2038 * fered by cross talk process, the driver make the playback 2123 2039 * preparation halted until cross talk process finish. 2124 2040 */ 2125 - nau8825_sema_acquire(nau8825, 2 * HZ); 2041 + nau8825_sema_acquire(nau8825, 3 * HZ); 2126 2042 nau8825_configure_mclk_as_sysclk(regmap); 2127 2043 /* MCLK not changed by clock tree */ 2128 2044 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, ··· 2141 2057 NAU8825_DCO_EN, NAU8825_DCO_EN); 2142 2058 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2143 2059 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2144 - /* Decrease the VCO frequency for power saving */ 2060 + /* Decrease the VCO frequency and make DSP operate 2061 + * as default setting for power saving. 2062 + */ 2145 2063 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2146 2064 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 2147 2065 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2066 + NAU8825_ICTRL_LATCH_MASK | 2148 2067 NAU8825_FLL_RATIO_MASK, 0x10); 2149 2068 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2150 2069 NAU8825_SDM_EN, NAU8825_SDM_EN); ··· 2170 2083 * fered by cross talk process, the driver make the playback 2171 2084 * preparation halted until cross talk process finish. 2172 2085 */ 2173 - nau8825_sema_acquire(nau8825, 2 * HZ); 2086 + nau8825_sema_acquire(nau8825, 3 * HZ); 2087 + /* Higher FLL reference input frequency can only set lower 2088 + * gain error, such as 0000 for input reference from MCLK 2089 + * 12.288Mhz. 2090 + */ 2174 2091 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2175 - NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK); 2092 + NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2093 + NAU8825_FLL_CLK_SRC_MCLK | 0); 2176 2094 /* Release the semaphone. */ 2177 2095 nau8825_sema_release(nau8825); 2178 2096 ··· 2192 2100 * fered by cross talk process, the driver make the playback 2193 2101 * preparation halted until cross talk process finish. 2194 2102 */ 2195 - nau8825_sema_acquire(nau8825, 2 * HZ); 2103 + nau8825_sema_acquire(nau8825, 3 * HZ); 2104 + /* If FLL reference input is from low frequency source, 2105 + * higher error gain can apply such as 0xf which has 2106 + * the most sensitive gain error correction threshold, 2107 + * Therefore, FLL has the most accurate DCO to 2108 + * target frequency. 2109 + */ 2196 2110 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2197 - NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK); 2111 + NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2112 + NAU8825_FLL_CLK_SRC_BLK | 2113 + (0xf << NAU8825_GAIN_ERR_SFT)); 2198 2114 /* Release the semaphone. */ 2199 2115 nau8825_sema_release(nau8825); 2200 2116 ··· 2218 2118 * fered by cross talk process, the driver make the playback 2219 2119 * preparation halted until cross talk process finish. 2220 2120 */ 2221 - nau8825_sema_acquire(nau8825, 2 * HZ); 2121 + nau8825_sema_acquire(nau8825, 3 * HZ); 2122 + /* If FLL reference input is from low frequency source, 2123 + * higher error gain can apply such as 0xf which has 2124 + * the most sensitive gain error correction threshold, 2125 + * Therefore, FLL has the most accurate DCO to 2126 + * target frequency. 2127 + */ 2222 2128 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2223 - NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS); 2129 + NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2130 + NAU8825_FLL_CLK_SRC_FS | 2131 + (0xf << NAU8825_GAIN_ERR_SFT)); 2224 2132 /* Release the semaphone. */ 2225 2133 nau8825_sema_release(nau8825); 2226 2134

+16

sound/soc/codecs/nau8825.h

··· 115 115 #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) 116 116 #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) 117 117 #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) 118 + #define NAU8825_CLK_ADC_SRC_SFT 6 119 + #define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT) 120 + #define NAU8825_CLK_DAC_SRC_SFT 4 121 + #define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT) 118 122 #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) 119 123 120 124 /* FLL1 (0x04) */ 125 + #define NAU8825_ICTRL_LATCH_SFT 10 126 + #define NAU8825_ICTRL_LATCH_MASK (0x7 << NAU8825_ICTRL_LATCH_SFT) 121 127 #define NAU8825_FLL_RATIO_MASK (0x7f << 0) 122 128 123 129 /* FLL3 (0x06) */ 130 + #define NAU8825_GAIN_ERR_SFT 12 131 + #define NAU8825_GAIN_ERR_MASK (0xf << NAU8825_GAIN_ERR_SFT) 124 132 #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) 125 133 #define NAU8825_FLL_CLK_SRC_SFT 10 126 134 #define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT) ··· 152 144 /* FLL6 (0x9) */ 153 145 #define NAU8825_DCO_EN (0x1 << 15) 154 146 #define NAU8825_SDM_EN (0x1 << 14) 147 + #define NAU8825_CUTOFF500 (0x1 << 13) 155 148 156 149 /* HSD_CTRL (0xc) */ 157 150 #define NAU8825_HSD_AUTO_MODE (1 << 6) ··· 255 246 #define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT) 256 247 #define NAU8825_I2S_BLK_DIV_MASK 0x7 257 248 249 + /* LEFT_TIME_SLOT (0x1e) */ 250 + #define NAU8825_FS_ERR_CMP_SEL_SFT 14 251 + #define NAU8825_FS_ERR_CMP_SEL_MASK (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT) 252 + #define NAU8825_DIS_FS_SHORT_DET (1 << 13) 253 + 258 254 /* BIQ_CTRL (0x20) */ 259 255 #define NAU8825_BIQ_WRT_SFT 4 260 256 #define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT) ··· 269 255 #define NAU8825_BIQ_PATH_DAC (1 << NAU8825_BIQ_PATH_SFT) 270 256 271 257 /* ADC_RATE (0x2b) */ 258 + #define NAU8825_ADC_SINC4_SFT 4 259 + #define NAU8825_ADC_SINC4_EN (1 << NAU8825_ADC_SINC4_SFT) 272 260 #define NAU8825_ADC_SYNC_DOWN_SFT 0 273 261 #define NAU8825_ADC_SYNC_DOWN_MASK 0x3 274 262 #define NAU8825_ADC_SYNC_DOWN_32 0