tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rproc-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
Pull remoteproc updates from Bjorn Andersson:
"Support for controlling the second core in Mediatek's SCP dual-core
setup is introduced.
Support for audio, compute and modem DSPs on Qualcomm SM6375, and the
audio DSP in SC7180 are introduced. The peripheral NoC clock is
dropped from MSM8996 modem DSP, as this is handled through the
interconnect provider.
In the zynqmp driver the setup for TCM memory, and device address
translation thereof, when operating in lockstep mode is corrected.
A few bug fixes and cleanups are introduces across the ST and STM32
remoteproc drivers"
* tag 'rproc-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (28 commits)
remoteproc: st: Fix sometimes uninitialized ret in st_rproc_probe()
remoteproc: st: Use device_get_match_data()
remoteproc: zynqmp: Change tcm address translation method
remoteproc: mediatek: Refactor single core check and fix retrocompatibility
remoteproc: qcom: q6v5-mss: Remove PNoC clock from 8996 MSS
dt-bindings: remoteproc: qcom,msm8996-mss-pil: Remove PNoC clock
dt-bindings: remoteproc: qcom,adsp: Remove AGGRE2 clock
remoteproc: qcom: pas: Add SM6375 MPSS
remoteproc: qcom: pas: Add SM6375 ADSP & CDSP
dt-bindings: remoteproc: qcom,sm6375-pas: Document remoteprocs
dt-bindings: remoteproc: pru: Add Interrupt property
remoteproc: qcom: pas: Add sc7180 adsp
dt-bindings: remoteproc: qcom: sc7180-pas: Add ADSP compatible
arm64: dts: mediatek: Update the node name of SCP rpmsg subnode
remoteproc: zynqmp: fix TCM carveouts in lockstep mode
remoteproc: mediatek: Refine ipi handler error message
remoteproc: mediatek: Report watchdog crash to all cores
remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout
remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset
remoteproc: mediatek: Remove dependency of MT8195 SCP L2TCM power control on dual-core SCP
...
+933
-249
+156
-20
Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
+156
-20
Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
···
21
21
- mediatek,mt8188-scp
22
22
- mediatek,mt8192-scp
23
23
- mediatek,mt8195-scp
24
+
- mediatek,mt8195-scp-dual
24
25
25
26
reg:
26
27
description:
···
32
31
33
32
reg-names:
34
33
minItems: 2
35
-
items:
36
-
- const: sram
37
-
- const: cfg
38
-
- const: l1tcm
34
+
maxItems: 3
39
35
40
36
clocks:
41
37
description:
···
55
57
56
58
memory-region:
57
59
maxItems: 1
60
+
61
+
cros-ec-rpmsg:
62
+
$ref: /schemas/mfd/google,cros-ec.yaml
63
+
description:
64
+
This subnode represents the rpmsg device. The properties
65
+
of this node are defined by the individual bindings for
66
+
the rpmsg devices.
67
+
68
+
required:
69
+
- mediatek,rpmsg-name
70
+
71
+
unevaluatedProperties: false
72
+
73
+
'#address-cells':
74
+
const: 1
75
+
76
+
'#size-cells':
77
+
const: 1
78
+
79
+
ranges:
80
+
description:
81
+
Standard ranges definition providing address translations for
82
+
local SCP SRAM address spaces to bus addresses.
83
+
84
+
patternProperties:
85
+
"^scp@[a-f0-9]+$":
86
+
type: object
87
+
description:
88
+
The MediaTek SCP integrated to SoC might be a multi-core version.
89
+
The other cores are represented as child nodes of the boot core.
90
+
There are some integration differences for the IP like the usage of
91
+
address translator for translating SoC bus addresses into address space
92
+
for the processor.
93
+
94
+
Each SCP core has own cache memory. The SRAM and L1TCM are shared by
95
+
cores. The power of cache, SRAM and L1TCM power should be enabled
96
+
before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
97
+
on differnt SoCs.
98
+
99
+
The SCP cores do not use an MMU, but has a set of registers to
100
+
control the translations between 32-bit CPU addresses into system bus
101
+
addresses. Cache and memory access settings are provided through a
102
+
Memory Protection Unit (MPU), programmable only from the SCP.
103
+
104
+
properties:
105
+
compatible:
106
+
enum:
107
+
- mediatek,scp-core
108
+
109
+
reg:
110
+
description: The base address and size of SRAM.
111
+
maxItems: 1
112
+
113
+
reg-names:
114
+
const: sram
115
+
116
+
interrupts:
117
+
maxItems: 1
118
+
119
+
firmware-name:
120
+
$ref: /schemas/types.yaml#/definitions/string
121
+
description:
122
+
If present, name (or relative path) of the file within the
123
+
firmware search path containing the firmware image used when
124
+
initializing sub cores of multi-core SCP.
125
+
126
+
memory-region:
127
+
maxItems: 1
128
+
129
+
cros-ec-rpmsg:
130
+
$ref: /schemas/mfd/google,cros-ec.yaml
131
+
description:
132
+
This subnode represents the rpmsg device. The properties
133
+
of this node are defined by the individual bindings for
134
+
the rpmsg devices.
135
+
136
+
required:
137
+
- mediatek,rpmsg-name
138
+
139
+
unevaluatedProperties: false
140
+
141
+
required:
142
+
- compatible
143
+
- reg
144
+
- reg-names
145
+
146
+
additionalProperties: false
58
147
59
148
required:
60
149
- compatible
···
172
87
reg:
173
88
maxItems: 2
174
89
reg-names:
90
+
items:
91
+
- const: sram
92
+
- const: cfg
93
+
- if:
94
+
properties:
95
+
compatible:
96
+
enum:
97
+
- mediatek,mt8192-scp
98
+
- mediatek,mt8195-scp
99
+
then:
100
+
properties:
101
+
reg:
102
+
maxItems: 3
103
+
reg-names:
104
+
items:
105
+
- const: sram
106
+
- const: cfg
107
+
- const: l1tcm
108
+
- if:
109
+
properties:
110
+
compatible:
111
+
enum:
112
+
- mediatek,mt8195-scp-dual
113
+
then:
114
+
properties:
115
+
reg:
175
116
maxItems: 2
117
+
reg-names:
118
+
items:
119
+
- const: cfg
120
+
- const: l1tcm
176
121
177
-
additionalProperties:
178
-
type: object
179
-
description:
180
-
Subnodes of the SCP represent rpmsg devices. The names of the devices
181
-
are not important. The properties of these nodes are defined by the
182
-
individual bindings for the rpmsg devices.
183
-
properties:
184
-
mediatek,rpmsg-name:
185
-
$ref: /schemas/types.yaml#/definitions/string-array
186
-
description:
187
-
Contains the name for the rpmsg device. Used to match
188
-
the subnode to rpmsg device announced by SCP.
189
-
190
-
required:
191
-
- mediatek,rpmsg-name
122
+
additionalProperties: false
192
123
193
124
examples:
194
125
- |
···
219
118
clocks = <&infracfg CLK_INFRA_SCPSYS>;
220
119
clock-names = "main";
221
120
222
-
cros_ec {
121
+
cros-ec-rpmsg {
122
+
compatible = "google,cros-ec-rpmsg";
223
123
mediatek,rpmsg-name = "cros-ec-rpmsg";
124
+
};
125
+
};
126
+
127
+
- |
128
+
scp@10500000 {
129
+
compatible = "mediatek,mt8195-scp-dual";
130
+
reg = <0x10720000 0xe0000>,
131
+
<0x10700000 0x8000>;
132
+
reg-names = "cfg", "l1tcm";
133
+
134
+
#address-cells = <1>;
135
+
#size-cells = <1>;
136
+
ranges = <0 0x10500000 0x100000>;
137
+
138
+
scp@0 {
139
+
compatible = "mediatek,scp-core";
140
+
reg = <0x0 0xa0000>;
141
+
reg-names = "sram";
142
+
143
+
cros-ec-rpmsg {
144
+
compatible = "google,cros-ec-rpmsg";
145
+
mediatek,rpmsg-name = "cros-ec-rpmsg";
146
+
};
147
+
};
148
+
149
+
scp@a0000 {
150
+
compatible = "mediatek,scp-core";
151
+
reg = <0xa0000 0x20000>;
152
+
reg-names = "sram";
153
+
154
+
cros-ec-rpmsg {
155
+
compatible = "google,cros-ec-rpmsg";
156
+
mediatek,rpmsg-name = "cros-ec-rpmsg";
157
+
};
224
158
};
225
159
};
+2
-18
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+2
-18
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
···
66
66
- qcom,msm8953-adsp-pil
67
67
- qcom,msm8974-adsp-pil
68
68
- qcom,msm8996-adsp-pil
69
+
- qcom,msm8996-slpi-pil
69
70
- qcom,msm8998-adsp-pas
71
+
- qcom,msm8998-slpi-pas
70
72
- qcom,sdm845-adsp-pas
71
73
- qcom,sdm845-cdsp-pas
72
74
- qcom,sdm845-slpi-pas
···
80
78
clock-names:
81
79
items:
82
80
- const: xo
83
-
84
-
- if:
85
-
properties:
86
-
compatible:
87
-
contains:
88
-
enum:
89
-
- qcom,msm8996-slpi-pil
90
-
- qcom,msm8998-slpi-pas
91
-
then:
92
-
properties:
93
-
clocks:
94
-
items:
95
-
- description: XO clock
96
-
- description: AGGRE2 clock
97
-
clock-names:
98
-
items:
99
-
- const: xo
100
-
- const: aggre2
101
81
102
82
- if:
103
83
properties:
-2
Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
-2
Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
···
220
220
- description: GCC MSS GPLL0 clock
221
221
- description: GCC MSS SNOC_AXI clock
222
222
- description: GCC MSS MNOC_AXI clock
223
-
- description: RPM PNOC clock
224
223
- description: RPM QDSS clock
225
224
clock-names:
226
225
items:
···
230
231
- const: gpll0_mss
231
232
- const: snoc_axi
232
233
- const: mnoc_axi
233
-
- const: pnoc
234
234
- const: qdss
235
235
glink-edge: false
236
236
required:
+56
-25
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml
+56
-25
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml
···
16
16
properties:
17
17
compatible:
18
18
enum:
19
+
- qcom,sc7180-adsp-pas
19
20
- qcom,sc7180-mpss-pas
20
21
- qcom,sc7280-mpss-pas
21
22
···
30
29
clock-names:
31
30
items:
32
31
- const: xo
33
-
34
-
interrupts:
35
-
minItems: 6
36
-
37
-
interrupt-names:
38
-
minItems: 6
39
-
40
-
power-domains:
41
-
minItems: 2
42
-
items:
43
-
- description: CX power domain
44
-
- description: MX power domain
45
-
- description: MSS power domain
46
-
47
-
power-domain-names:
48
-
minItems: 2
49
-
items:
50
-
- const: cx
51
-
- const: mx
52
-
- const: mss
53
32
54
33
memory-region:
55
34
maxItems: 1
···
56
75
properties:
57
76
compatible:
58
77
enum:
78
+
- qcom,sc7180-adsp-pas
79
+
then:
80
+
properties:
81
+
interrupts:
82
+
maxItems: 5
83
+
interrupt-names:
84
+
maxItems: 5
85
+
else:
86
+
properties:
87
+
interrupts:
88
+
minItems: 6
89
+
interrupt-names:
90
+
minItems: 6
91
+
92
+
- if:
93
+
properties:
94
+
compatible:
95
+
enum:
96
+
- qcom,sc7180-adsp-pas
97
+
then:
98
+
properties:
99
+
power-domains:
100
+
items:
101
+
- description: LCX power domain
102
+
- description: LMX power domain
103
+
power-domain-names:
104
+
items:
105
+
- const: lcx
106
+
- const: lmx
107
+
108
+
- if:
109
+
properties:
110
+
compatible:
111
+
enum:
59
112
- qcom,sc7180-mpss-pas
60
113
then:
61
114
properties:
62
115
power-domains:
63
-
minItems: 3
116
+
items:
117
+
- description: CX power domain
118
+
- description: MX power domain
119
+
- description: MSS power domain
64
120
power-domain-names:
65
-
minItems: 3
66
-
else:
121
+
items:
122
+
- const: cx
123
+
- const: mx
124
+
- const: mss
125
+
126
+
- if:
127
+
properties:
128
+
compatible:
129
+
enum:
130
+
- qcom,sc7280-mpss-pas
131
+
then:
67
132
properties:
68
133
power-domains:
69
-
maxItems: 2
134
+
items:
135
+
- description: CX power domain
136
+
- description: MX power domain
70
137
power-domain-names:
71
-
maxItems: 2
138
+
items:
139
+
- const: cx
140
+
- const: mx
72
141
73
142
unevaluatedProperties: false
74
143
+145
Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml
+145
Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,sm6375-pas.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM6375 Peripheral Authentication Service
8
+
9
+
maintainers:
10
+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
+
12
+
description:
13
+
Qualcomm SM6375 SoC Peripheral Authentication Service loads and boots
14
+
firmware on the Qualcomm DSP Hexagon cores.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,sm6375-adsp-pas
20
+
- qcom,sm6375-cdsp-pas
21
+
- qcom,sm6375-mpss-pas
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: XO clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: xo
33
+
34
+
memory-region:
35
+
maxItems: 1
36
+
description: Reference to the reserved-memory for the Hexagon core
37
+
38
+
firmware-name:
39
+
$ref: /schemas/types.yaml#/definitions/string
40
+
description: Firmware name for the Hexagon core
41
+
42
+
smd-edge: false
43
+
44
+
required:
45
+
- compatible
46
+
- reg
47
+
48
+
allOf:
49
+
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
50
+
- if:
51
+
properties:
52
+
compatible:
53
+
enum:
54
+
- qcom,sm6375-adsp-pas
55
+
- qcom,sm6375-cdsp-pas
56
+
then:
57
+
properties:
58
+
interrupts:
59
+
maxItems: 5
60
+
interrupt-names:
61
+
maxItems: 5
62
+
else:
63
+
properties:
64
+
interrupts:
65
+
minItems: 6
66
+
interrupt-names:
67
+
minItems: 6
68
+
69
+
- if:
70
+
properties:
71
+
compatible:
72
+
enum:
73
+
- qcom,sm6375-adsp-pas
74
+
then:
75
+
properties:
76
+
power-domains:
77
+
items:
78
+
- description: LCX power domain
79
+
- description: LMX power domain
80
+
power-domain-names:
81
+
items:
82
+
- const: lcx
83
+
- const: lmx
84
+
85
+
- if:
86
+
properties:
87
+
compatible:
88
+
enum:
89
+
- qcom,sm6375-cdsp-pas
90
+
- qcom,sm6375-mpss-pas
91
+
then:
92
+
properties:
93
+
power-domains:
94
+
items:
95
+
- description: CX power domain
96
+
power-domain-names:
97
+
items:
98
+
- const: cx
99
+
100
+
unevaluatedProperties: false
101
+
102
+
examples:
103
+
- |
104
+
#include <dt-bindings/clock/qcom,rpmcc.h>
105
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
106
+
#include <dt-bindings/mailbox/qcom-ipcc.h>
107
+
#include <dt-bindings/power/qcom-rpmpd.h>
108
+
109
+
remoteproc_adsp: remoteproc@a400000 {
110
+
compatible = "qcom,sm6375-adsp-pas";
111
+
reg = <0x0a400000 0x100>;
112
+
113
+
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
114
+
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
115
+
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
116
+
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
117
+
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
118
+
interrupt-names = "wdog", "fatal", "ready",
119
+
"handover", "stop-ack";
120
+
121
+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
122
+
clock-names = "xo";
123
+
124
+
power-domains = <&rpmpd SM6375_VDD_LPI_CX>,
125
+
<&rpmpd SM6375_VDD_LPI_MX>;
126
+
power-domain-names = "lcx", "lmx";
127
+
128
+
memory-region = <&pil_adsp_mem>;
129
+
130
+
qcom,smem-states = <&smp2p_adsp_out 0>;
131
+
qcom,smem-state-names = "stop";
132
+
133
+
glink-edge {
134
+
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
135
+
IPCC_MPROC_SIGNAL_GLINK_QMP
136
+
IRQ_TYPE_EDGE_RISING>;
137
+
mboxes = <&ipcc IPCC_CLIENT_LPASS
138
+
IPCC_MPROC_SIGNAL_GLINK_QMP>;
139
+
140
+
label = "lpass";
141
+
qcom,remote-pid = <2>;
142
+
143
+
/* ... */
144
+
};
145
+
};
+23
Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml
+23
Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml
···
66
66
Should contain the name of the default firmware image
67
67
file located on the firmware search path.
68
68
69
+
interrupts:
70
+
maxItems: 1
71
+
description:
72
+
Interrupt specifiers enable the virtio/rpmsg communication between MPU
73
+
and the PRU/RTU cores. For the values of the interrupt cells please refer
74
+
to interrupt-controller/ti,pruss-intc.yaml schema.
75
+
76
+
interrupt-names:
77
+
items:
78
+
- const: vring
79
+
69
80
if:
70
81
properties:
71
82
compatible:
···
182
171
<0x22400 0x100>;
183
172
reg-names = "iram", "control", "debug";
184
173
firmware-name = "am65x-pru0_0-fw";
174
+
interrupt-parent = <&icssg0_intc>;
175
+
interrupts = <16 2 2>;
176
+
interrupt-names = "vring";
185
177
};
186
178
187
179
rtu0_0: rtu@4000 {
···
194
180
<0x23400 0x100>;
195
181
reg-names = "iram", "control", "debug";
196
182
firmware-name = "am65x-rtu0_0-fw";
183
+
interrupt-parent = <&icssg0_intc>;
184
+
interrupts = <20 4 4>;
185
+
interrupt-names = "vring";
197
186
};
198
187
199
188
tx_pru0_0: txpru@a000 {
···
215
198
<0x24400 0x100>;
216
199
reg-names = "iram", "control", "debug";
217
200
firmware-name = "am65x-pru0_1-fw";
201
+
interrupt-parent = <&icssg0_intc>;
202
+
interrupts = <18 3 3>;
203
+
interrupt-names = "vring";
218
204
};
219
205
220
206
rtu0_1: rtu@6000 {
···
227
207
<0x23c00 0x100>;
228
208
reg-names = "iram", "control", "debug";
229
209
firmware-name = "am65x-rtu0_1-fw";
210
+
interrupt-parent = <&icssg0_intc>;
211
+
interrupts = <22 5 5>;
212
+
interrupt-names = "vring";
230
213
};
231
214
232
215
tx_pru0_1: txpru@c000 {
+1
-1
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+35
-4
drivers/remoteproc/mtk_common.h
+35
-4
drivers/remoteproc/mtk_common.h
···
47
47
#define MT8192_SCP2SPM_IPC_CLR 0x4094
48
48
#define MT8192_GIPC_IN_SET 0x4098
49
49
#define MT8192_HOST_IPC_INT_BIT BIT(0)
50
+
#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4)
50
51
51
52
#define MT8192_CORE0_SW_RSTN_CLR 0x10000
52
53
#define MT8192_CORE0_SW_RSTN_SET 0x10004
···
55
54
#define MT8192_CORE0_WDT_IRQ 0x10030
56
55
#define MT8192_CORE0_WDT_CFG 0x10034
57
56
57
+
#define MT8195_SYS_STATUS 0x4004
58
+
#define MT8195_CORE0_WDT BIT(16)
59
+
#define MT8195_CORE1_WDT BIT(17)
60
+
58
61
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
62
+
63
+
#define MT8195_CPU1_SRAM_PD 0x1084
64
+
#define MT8195_SSHUB2APMCU_IPC_SET 0x4088
65
+
#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C
66
+
#define MT8195_CORE1_SW_RSTN_CLR 0x20000
67
+
#define MT8195_CORE1_SW_RSTN_SET 0x20004
68
+
#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
69
+
#define MT8195_CORE1_WDT_IRQ 0x20030
70
+
#define MT8195_CORE1_WDT_CFG 0x20034
71
+
72
+
#define MT8195_SEC_CTRL 0x85000
73
+
#define MT8195_CORE_OFFSET_ENABLE_D BIT(13)
74
+
#define MT8195_CORE_OFFSET_ENABLE_I BIT(12)
75
+
#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0
76
+
#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4
77
+
#define MT8195_L2TCM_OFFSET 0x850d0
59
78
60
79
#define SCP_FW_VER_LEN 32
61
80
#define SCP_SHARE_BUFFER_SIZE 288
···
112
91
size_t ipi_buf_offset;
113
92
};
114
93
94
+
struct mtk_scp_of_cluster {
95
+
void __iomem *reg_base;
96
+
void __iomem *l1tcm_base;
97
+
size_t l1tcm_size;
98
+
phys_addr_t l1tcm_phys;
99
+
struct list_head mtk_scp_list;
100
+
/* Prevent concurrent operations of this structure and L2TCM power control. */
101
+
struct mutex cluster_lock;
102
+
u32 l2tcm_refcnt;
103
+
};
104
+
115
105
struct mtk_scp {
116
106
struct device *dev;
117
107
struct rproc *rproc;
118
108
struct clk *clk;
119
-
void __iomem *reg_base;
120
109
void __iomem *sram_base;
121
110
size_t sram_size;
122
111
phys_addr_t sram_phys;
123
-
void __iomem *l1tcm_base;
124
-
size_t l1tcm_size;
125
-
phys_addr_t l1tcm_phys;
126
112
127
113
const struct mtk_scp_of_data *data;
128
114
···
147
119
size_t dram_size;
148
120
149
121
struct rproc_subdev *rpmsg_subdev;
122
+
123
+
struct list_head elem;
124
+
struct mtk_scp_of_cluster *cluster;
150
125
};
151
126
152
127
/**
+428
-108
drivers/remoteproc/mtk_scp.c
+428
-108
drivers/remoteproc/mtk_scp.c
···
68
68
69
69
static void scp_wdt_handler(struct mtk_scp *scp, u32 scp_to_host)
70
70
{
71
+
struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
72
+
struct mtk_scp *scp_node;
73
+
71
74
dev_err(scp->dev, "SCP watchdog timeout! 0x%x", scp_to_host);
72
-
rproc_report_crash(scp->rproc, RPROC_WATCHDOG);
75
+
76
+
/* report watchdog timeout to all cores */
77
+
list_for_each_entry(scp_node, &scp_cluster->mtk_scp_list, elem)
78
+
rproc_report_crash(scp_node->rproc, RPROC_WATCHDOG);
73
79
}
74
80
75
81
static void scp_init_ipi_handler(void *data, unsigned int len, void *priv)
···
112
106
scp_ipi_lock(scp, id);
113
107
handler = ipi_desc[id].handler;
114
108
if (!handler) {
115
-
dev_err(scp->dev, "No such ipi id = %d\n", id);
109
+
dev_err(scp->dev, "No handler for ipi id = %d\n", id);
116
110
scp_ipi_unlock(scp, id);
117
111
return;
118
112
}
···
158
152
{
159
153
u32 val;
160
154
161
-
val = readl(scp->reg_base + MT8183_SW_RSTN);
155
+
val = readl(scp->cluster->reg_base + MT8183_SW_RSTN);
162
156
val &= ~MT8183_SW_RSTN_BIT;
163
-
writel(val, scp->reg_base + MT8183_SW_RSTN);
157
+
writel(val, scp->cluster->reg_base + MT8183_SW_RSTN);
164
158
}
165
159
166
160
static void mt8183_scp_reset_deassert(struct mtk_scp *scp)
167
161
{
168
162
u32 val;
169
163
170
-
val = readl(scp->reg_base + MT8183_SW_RSTN);
164
+
val = readl(scp->cluster->reg_base + MT8183_SW_RSTN);
171
165
val |= MT8183_SW_RSTN_BIT;
172
-
writel(val, scp->reg_base + MT8183_SW_RSTN);
166
+
writel(val, scp->cluster->reg_base + MT8183_SW_RSTN);
173
167
}
174
168
175
169
static void mt8192_scp_reset_assert(struct mtk_scp *scp)
176
170
{
177
-
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
171
+
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
178
172
}
179
173
180
174
static void mt8192_scp_reset_deassert(struct mtk_scp *scp)
181
175
{
182
-
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR);
176
+
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_CLR);
177
+
}
178
+
179
+
static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp)
180
+
{
181
+
writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_SET);
182
+
}
183
+
184
+
static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp)
185
+
{
186
+
writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_CLR);
183
187
}
184
188
185
189
static void mt8183_scp_irq_handler(struct mtk_scp *scp)
186
190
{
187
191
u32 scp_to_host;
188
192
189
-
scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST);
193
+
scp_to_host = readl(scp->cluster->reg_base + MT8183_SCP_TO_HOST);
190
194
if (scp_to_host & MT8183_SCP_IPC_INT_BIT)
191
195
scp_ipi_handler(scp);
192
196
else
···
204
188
205
189
/* SCP won't send another interrupt until we set SCP_TO_HOST to 0. */
206
190
writel(MT8183_SCP_IPC_INT_BIT | MT8183_SCP_WDT_INT_BIT,
207
-
scp->reg_base + MT8183_SCP_TO_HOST);
191
+
scp->cluster->reg_base + MT8183_SCP_TO_HOST);
208
192
}
209
193
210
194
static void mt8192_scp_irq_handler(struct mtk_scp *scp)
211
195
{
212
196
u32 scp_to_host;
213
197
214
-
scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET);
198
+
scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET);
215
199
216
200
if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
217
201
scp_ipi_handler(scp);
···
221
205
* MT8192_SCP2APMCU_IPC.
222
206
*/
223
207
writel(MT8192_SCP_IPC_INT_BIT,
224
-
scp->reg_base + MT8192_SCP2APMCU_IPC_CLR);
208
+
scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR);
225
209
} else {
226
210
scp_wdt_handler(scp, scp_to_host);
227
-
writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ);
211
+
writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
228
212
}
213
+
}
214
+
215
+
static void mt8195_scp_irq_handler(struct mtk_scp *scp)
216
+
{
217
+
u32 scp_to_host;
218
+
219
+
scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET);
220
+
221
+
if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
222
+
scp_ipi_handler(scp);
223
+
} else {
224
+
u32 reason = readl(scp->cluster->reg_base + MT8195_SYS_STATUS);
225
+
226
+
if (reason & MT8195_CORE0_WDT)
227
+
writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
228
+
229
+
if (reason & MT8195_CORE1_WDT)
230
+
writel(1, scp->cluster->reg_base + MT8195_CORE1_WDT_IRQ);
231
+
232
+
scp_wdt_handler(scp, reason);
233
+
}
234
+
235
+
writel(scp_to_host, scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR);
236
+
}
237
+
238
+
static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp)
239
+
{
240
+
u32 scp_to_host;
241
+
242
+
scp_to_host = readl(scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_SET);
243
+
244
+
if (scp_to_host & MT8192_SCP_IPC_INT_BIT)
245
+
scp_ipi_handler(scp);
246
+
247
+
writel(scp_to_host, scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_CLR);
229
248
}
230
249
231
250
static irqreturn_t scp_irq_handler(int irq, void *priv)
···
392
341
static int mt8183_scp_before_load(struct mtk_scp *scp)
393
342
{
394
343
/* Clear SCP to host interrupt */
395
-
writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
344
+
writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOST);
396
345
397
346
/* Reset clocks before loading FW */
398
-
writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
399
-
writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
347
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL);
348
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL);
400
349
401
350
/* Initialize TCM before loading FW. */
402
-
writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
403
-
writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
351
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD);
352
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
404
353
405
354
/* Turn on the power of SCP's SRAM before using it. */
406
-
writel(0x0, scp->reg_base + MT8183_SCP_SRAM_PDN);
355
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_SRAM_PDN);
407
356
408
357
/*
409
358
* Set I-cache and D-cache size before loading SCP FW.
410
359
* SCP SRAM logical address may change when cache size setting differs.
411
360
*/
412
361
writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB,
413
-
scp->reg_base + MT8183_SCP_CACHE_CON);
414
-
writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);
362
+
scp->cluster->reg_base + MT8183_SCP_CACHE_CON);
363
+
writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCACHE_CON);
415
364
416
365
return 0;
417
366
}
···
437
386
static int mt8186_scp_before_load(struct mtk_scp *scp)
438
387
{
439
388
/* Clear SCP to host interrupt */
440
-
writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
389
+
writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOST);
441
390
442
391
/* Reset clocks before loading FW */
443
-
writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);
444
-
writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
392
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL);
393
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL);
445
394
446
395
/* Turn on the power of SCP's SRAM before using it. Enable 1 block per time*/
447
-
scp_sram_power_on(scp->reg_base + MT8183_SCP_SRAM_PDN, 0);
396
+
scp_sram_power_on(scp->cluster->reg_base + MT8183_SCP_SRAM_PDN, 0);
448
397
449
398
/* Initialize TCM before loading FW. */
450
-
writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
451
-
writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
452
-
writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1);
453
-
writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2);
399
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD);
400
+
writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
401
+
writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_P1);
402
+
writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_p2);
454
403
455
404
/*
456
405
* Set I-cache and D-cache size before loading SCP FW.
457
406
* SCP SRAM logical address may change when cache size setting differs.
458
407
*/
459
408
writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB,
460
-
scp->reg_base + MT8183_SCP_CACHE_CON);
461
-
writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON);
409
+
scp->cluster->reg_base + MT8183_SCP_CACHE_CON);
410
+
writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCACHE_CON);
462
411
463
412
return 0;
464
413
}
···
466
415
static int mt8192_scp_before_load(struct mtk_scp *scp)
467
416
{
468
417
/* clear SPM interrupt, SCP2SPM_IPC_CLR */
469
-
writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
418
+
writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
470
419
471
-
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
420
+
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
472
421
473
422
/* enable SRAM clock */
474
-
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
475
-
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
476
-
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
477
-
scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
478
-
scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
423
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
424
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
425
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
426
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
427
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
479
428
480
429
/* enable MPU for all memory regions */
481
-
writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
430
+
writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
431
+
432
+
return 0;
433
+
}
434
+
435
+
static int mt8195_scp_l2tcm_on(struct mtk_scp *scp)
436
+
{
437
+
struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
438
+
439
+
mutex_lock(&scp_cluster->cluster_lock);
440
+
441
+
if (scp_cluster->l2tcm_refcnt == 0) {
442
+
/* clear SPM interrupt, SCP2SPM_IPC_CLR */
443
+
writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
444
+
445
+
/* Power on L2TCM */
446
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
447
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
448
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
449
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN,
450
+
MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
451
+
}
452
+
453
+
scp_cluster->l2tcm_refcnt += 1;
454
+
455
+
mutex_unlock(&scp_cluster->cluster_lock);
482
456
483
457
return 0;
484
458
}
485
459
486
460
static int mt8195_scp_before_load(struct mtk_scp *scp)
487
461
{
488
-
/* clear SPM interrupt, SCP2SPM_IPC_CLR */
489
-
writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
462
+
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
490
463
491
-
writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
464
+
mt8195_scp_l2tcm_on(scp);
492
465
493
-
/* enable SRAM clock */
494
-
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
495
-
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
496
-
scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
497
-
scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
498
-
MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
499
-
scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
466
+
scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
500
467
501
468
/* enable MPU for all memory regions */
502
-
writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
469
+
writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
470
+
471
+
return 0;
472
+
}
473
+
474
+
static int mt8195_scp_c1_before_load(struct mtk_scp *scp)
475
+
{
476
+
u32 sec_ctrl;
477
+
struct mtk_scp *scp_c0;
478
+
struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
479
+
480
+
scp->data->scp_reset_assert(scp);
481
+
482
+
mt8195_scp_l2tcm_on(scp);
483
+
484
+
scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0);
485
+
486
+
/* enable MPU for all memory regions */
487
+
writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF);
488
+
489
+
/*
490
+
* The L2TCM_OFFSET_RANGE and L2TCM_OFFSET shift the destination address
491
+
* on SRAM when SCP core 1 accesses SRAM.
492
+
*
493
+
* This configuration solves booting the SCP core 0 and core 1 from
494
+
* different SRAM address because core 0 and core 1 both boot from
495
+
* the head of SRAM by default. this must be configured before boot SCP core 1.
496
+
*
497
+
* The value of L2TCM_OFFSET_RANGE is from the viewpoint of SCP core 1.
498
+
* When SCP core 1 issues address within the range (L2TCM_OFFSET_RANGE),
499
+
* the address will be added with a fixed offset (L2TCM_OFFSET) on the bus.
500
+
* The shift action is tranparent to software.
501
+
*/
502
+
writel(0, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW);
503
+
writel(scp->sram_size, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH);
504
+
505
+
scp_c0 = list_first_entry(&scp_cluster->mtk_scp_list, struct mtk_scp, elem);
506
+
writel(scp->sram_phys - scp_c0->sram_phys, scp->cluster->reg_base + MT8195_L2TCM_OFFSET);
507
+
508
+
/* enable SRAM offset when fetching instruction and data */
509
+
sec_ctrl = readl(scp->cluster->reg_base + MT8195_SEC_CTRL);
510
+
sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D;
511
+
writel(sec_ctrl, scp->cluster->reg_base + MT8195_SEC_CTRL);
503
512
504
513
return 0;
505
514
}
···
678
567
}
679
568
680
569
/* optional memory region */
681
-
if (scp->l1tcm_size &&
682
-
da >= scp->l1tcm_phys &&
683
-
(da + len) <= scp->l1tcm_phys + scp->l1tcm_size) {
684
-
offset = da - scp->l1tcm_phys;
685
-
return (void __force *)scp->l1tcm_base + offset;
570
+
if (scp->cluster->l1tcm_size &&
571
+
da >= scp->cluster->l1tcm_phys &&
572
+
(da + len) <= scp->cluster->l1tcm_phys + scp->cluster->l1tcm_size) {
573
+
offset = da - scp->cluster->l1tcm_phys;
574
+
return (void __force *)scp->cluster->l1tcm_base + offset;
686
575
}
687
576
688
577
/* optional memory region */
···
706
595
static void mt8183_scp_stop(struct mtk_scp *scp)
707
596
{
708
597
/* Disable SCP watchdog */
709
-
writel(0, scp->reg_base + MT8183_WDT_CFG);
598
+
writel(0, scp->cluster->reg_base + MT8183_WDT_CFG);
710
599
}
711
600
712
601
static void mt8192_scp_stop(struct mtk_scp *scp)
713
602
{
714
603
/* Disable SRAM clock */
715
-
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
716
-
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
717
-
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
718
-
scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
719
-
scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
604
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
605
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
606
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
607
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
608
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
720
609
721
610
/* Disable SCP watchdog */
722
-
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
611
+
writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG);
612
+
}
613
+
614
+
static void mt8195_scp_l2tcm_off(struct mtk_scp *scp)
615
+
{
616
+
struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
617
+
618
+
mutex_lock(&scp_cluster->cluster_lock);
619
+
620
+
if (scp_cluster->l2tcm_refcnt > 0)
621
+
scp_cluster->l2tcm_refcnt -= 1;
622
+
623
+
if (scp_cluster->l2tcm_refcnt == 0) {
624
+
/* Power off L2TCM */
625
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
626
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
627
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
628
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN,
629
+
MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
630
+
}
631
+
632
+
mutex_unlock(&scp_cluster->cluster_lock);
723
633
}
724
634
725
635
static void mt8195_scp_stop(struct mtk_scp *scp)
726
636
{
727
-
/* Disable SRAM clock */
728
-
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
729
-
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
730
-
scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
731
-
scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
732
-
MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
733
-
scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
637
+
mt8195_scp_l2tcm_off(scp);
638
+
639
+
scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
734
640
735
641
/* Disable SCP watchdog */
736
-
writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
642
+
writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG);
643
+
}
644
+
645
+
static void mt8195_scp_c1_stop(struct mtk_scp *scp)
646
+
{
647
+
mt8195_scp_l2tcm_off(scp);
648
+
649
+
/* Power off CPU SRAM */
650
+
scp_sram_power_off(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0);
651
+
652
+
/* Disable SCP watchdog */
653
+
writel(0, scp->cluster->reg_base + MT8195_CORE1_WDT_CFG);
737
654
}
738
655
739
656
static int scp_stop(struct rproc *rproc)
···
950
811
}
951
812
}
952
813
953
-
static int scp_probe(struct platform_device *pdev)
814
+
static struct mtk_scp *scp_rproc_init(struct platform_device *pdev,
815
+
struct mtk_scp_of_cluster *scp_cluster,
816
+
const struct mtk_scp_of_data *of_data)
954
817
{
955
818
struct device *dev = &pdev->dev;
956
819
struct device_node *np = dev->of_node;
···
964
823
965
824
ret = rproc_of_parse_firmware(dev, 0, &fw_name);
966
825
if (ret < 0 && ret != -EINVAL)
967
-
return ret;
826
+
return ERR_PTR(ret);
968
827
969
828
rproc = devm_rproc_alloc(dev, np->name, &scp_ops, fw_name, sizeof(*scp));
970
-
if (!rproc)
971
-
return dev_err_probe(dev, -ENOMEM, "unable to allocate remoteproc\n");
829
+
if (!rproc) {
830
+
dev_err(dev, "unable to allocate remoteproc\n");
831
+
return ERR_PTR(-ENOMEM);
832
+
}
972
833
973
834
scp = rproc->priv;
974
835
scp->rproc = rproc;
975
836
scp->dev = dev;
976
-
scp->data = of_device_get_match_data(dev);
837
+
scp->data = of_data;
838
+
scp->cluster = scp_cluster;
977
839
platform_set_drvdata(pdev, scp);
978
840
979
841
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
980
842
scp->sram_base = devm_ioremap_resource(dev, res);
981
-
if (IS_ERR(scp->sram_base))
982
-
return dev_err_probe(dev, PTR_ERR(scp->sram_base),
983
-
"Failed to parse and map sram memory\n");
843
+
if (IS_ERR(scp->sram_base)) {
844
+
dev_err(dev, "Failed to parse and map sram memory\n");
845
+
return ERR_CAST(scp->sram_base);
846
+
}
984
847
985
848
scp->sram_size = resource_size(res);
986
849
scp->sram_phys = res->start;
987
850
988
-
/* l1tcm is an optional memory region */
989
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm");
990
-
scp->l1tcm_base = devm_ioremap_resource(dev, res);
991
-
if (IS_ERR(scp->l1tcm_base)) {
992
-
ret = PTR_ERR(scp->l1tcm_base);
993
-
if (ret != -EINVAL) {
994
-
return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n");
995
-
}
996
-
} else {
997
-
scp->l1tcm_size = resource_size(res);
998
-
scp->l1tcm_phys = res->start;
999
-
}
1000
-
1001
-
scp->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
1002
-
if (IS_ERR(scp->reg_base))
1003
-
return dev_err_probe(dev, PTR_ERR(scp->reg_base),
1004
-
"Failed to parse and map cfg memory\n");
1005
-
1006
851
ret = scp->data->scp_clk_get(scp);
1007
852
if (ret)
1008
-
return ret;
853
+
return ERR_PTR(ret);
1009
854
1010
855
ret = scp_map_memory_region(scp);
1011
856
if (ret)
1012
-
return ret;
857
+
return ERR_PTR(ret);
1013
858
1014
859
mutex_init(&scp->send_lock);
1015
860
for (i = 0; i < SCP_IPI_MAX; i++)
···
1022
895
goto remove_subdev;
1023
896
}
1024
897
1025
-
ret = rproc_add(rproc);
1026
-
if (ret)
1027
-
goto remove_subdev;
1028
-
1029
-
return 0;
898
+
return scp;
1030
899
1031
900
remove_subdev:
1032
901
scp_remove_rpmsg_subdev(scp);
···
1033
910
mutex_destroy(&scp->ipi_desc[i].lock);
1034
911
mutex_destroy(&scp->send_lock);
1035
912
1036
-
return ret;
913
+
return ERR_PTR(ret);
1037
914
}
1038
915
1039
-
static void scp_remove(struct platform_device *pdev)
916
+
static void scp_free(struct mtk_scp *scp)
1040
917
{
1041
-
struct mtk_scp *scp = platform_get_drvdata(pdev);
1042
918
int i;
1043
919
1044
-
rproc_del(scp->rproc);
1045
920
scp_remove_rpmsg_subdev(scp);
1046
921
scp_ipi_unregister(scp, SCP_IPI_INIT);
1047
922
scp_unmap_memory_region(scp);
1048
923
for (i = 0; i < SCP_IPI_MAX; i++)
1049
924
mutex_destroy(&scp->ipi_desc[i].lock);
1050
925
mutex_destroy(&scp->send_lock);
926
+
}
927
+
928
+
static int scp_add_single_core(struct platform_device *pdev,
929
+
struct mtk_scp_of_cluster *scp_cluster)
930
+
{
931
+
struct device *dev = &pdev->dev;
932
+
struct list_head *scp_list = &scp_cluster->mtk_scp_list;
933
+
struct mtk_scp *scp;
934
+
int ret;
935
+
936
+
scp = scp_rproc_init(pdev, scp_cluster, of_device_get_match_data(dev));
937
+
if (IS_ERR(scp))
938
+
return PTR_ERR(scp);
939
+
940
+
ret = rproc_add(scp->rproc);
941
+
if (ret) {
942
+
dev_err(dev, "Failed to add rproc\n");
943
+
scp_free(scp);
944
+
return ret;
945
+
}
946
+
947
+
list_add_tail(&scp->elem, scp_list);
948
+
949
+
return 0;
950
+
}
951
+
952
+
static int scp_add_multi_core(struct platform_device *pdev,
953
+
struct mtk_scp_of_cluster *scp_cluster)
954
+
{
955
+
struct device *dev = &pdev->dev;
956
+
struct device_node *np = dev_of_node(dev);
957
+
struct platform_device *cpdev;
958
+
struct device_node *child;
959
+
struct list_head *scp_list = &scp_cluster->mtk_scp_list;
960
+
const struct mtk_scp_of_data **cluster_of_data;
961
+
struct mtk_scp *scp, *temp;
962
+
int core_id = 0;
963
+
int ret;
964
+
965
+
cluster_of_data = (const struct mtk_scp_of_data **)of_device_get_match_data(dev);
966
+
967
+
for_each_available_child_of_node(np, child) {
968
+
if (!cluster_of_data[core_id]) {
969
+
ret = -EINVAL;
970
+
dev_err(dev, "Not support core %d\n", core_id);
971
+
of_node_put(child);
972
+
goto init_fail;
973
+
}
974
+
975
+
cpdev = of_find_device_by_node(child);
976
+
if (!cpdev) {
977
+
ret = -ENODEV;
978
+
dev_err(dev, "Not found platform device for core %d\n", core_id);
979
+
of_node_put(child);
980
+
goto init_fail;
981
+
}
982
+
983
+
scp = scp_rproc_init(cpdev, scp_cluster, cluster_of_data[core_id]);
984
+
put_device(&cpdev->dev);
985
+
if (IS_ERR(scp)) {
986
+
ret = PTR_ERR(scp);
987
+
dev_err(dev, "Failed to initialize core %d rproc\n", core_id);
988
+
of_node_put(child);
989
+
goto init_fail;
990
+
}
991
+
992
+
ret = rproc_add(scp->rproc);
993
+
if (ret) {
994
+
dev_err(dev, "Failed to add rproc of core %d\n", core_id);
995
+
of_node_put(child);
996
+
scp_free(scp);
997
+
goto init_fail;
998
+
}
999
+
1000
+
list_add_tail(&scp->elem, scp_list);
1001
+
core_id++;
1002
+
}
1003
+
1004
+
/*
1005
+
* Here we are setting the platform device for @pdev to the last @scp that was
1006
+
* created, which is needed because (1) scp_rproc_init() is calling
1007
+
* platform_set_drvdata() on the child platform devices and (2) we need a handle to
1008
+
* the cluster list in scp_remove().
1009
+
*/
1010
+
platform_set_drvdata(pdev, scp);
1011
+
1012
+
return 0;
1013
+
1014
+
init_fail:
1015
+
list_for_each_entry_safe_reverse(scp, temp, scp_list, elem) {
1016
+
list_del(&scp->elem);
1017
+
rproc_del(scp->rproc);
1018
+
scp_free(scp);
1019
+
}
1020
+
1021
+
return ret;
1022
+
}
1023
+
1024
+
static bool scp_is_single_core(struct platform_device *pdev)
1025
+
{
1026
+
struct device *dev = &pdev->dev;
1027
+
struct device_node *np = dev_of_node(dev);
1028
+
struct device_node *child;
1029
+
int num_cores = 0;
1030
+
1031
+
for_each_child_of_node(np, child)
1032
+
if (of_device_is_compatible(child, "mediatek,scp-core"))
1033
+
num_cores++;
1034
+
1035
+
return num_cores < 2;
1036
+
}
1037
+
1038
+
static int scp_cluster_init(struct platform_device *pdev, struct mtk_scp_of_cluster *scp_cluster)
1039
+
{
1040
+
int ret;
1041
+
1042
+
if (scp_is_single_core(pdev))
1043
+
ret = scp_add_single_core(pdev, scp_cluster);
1044
+
else
1045
+
ret = scp_add_multi_core(pdev, scp_cluster);
1046
+
1047
+
return ret;
1048
+
}
1049
+
1050
+
static int scp_probe(struct platform_device *pdev)
1051
+
{
1052
+
struct device *dev = &pdev->dev;
1053
+
struct mtk_scp_of_cluster *scp_cluster;
1054
+
struct resource *res;
1055
+
int ret;
1056
+
1057
+
scp_cluster = devm_kzalloc(dev, sizeof(*scp_cluster), GFP_KERNEL);
1058
+
if (!scp_cluster)
1059
+
return -ENOMEM;
1060
+
1061
+
scp_cluster->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
1062
+
if (IS_ERR(scp_cluster->reg_base))
1063
+
return dev_err_probe(dev, PTR_ERR(scp_cluster->reg_base),
1064
+
"Failed to parse and map cfg memory\n");
1065
+
1066
+
/* l1tcm is an optional memory region */
1067
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm");
1068
+
scp_cluster->l1tcm_base = devm_ioremap_resource(dev, res);
1069
+
if (IS_ERR(scp_cluster->l1tcm_base)) {
1070
+
ret = PTR_ERR(scp_cluster->l1tcm_base);
1071
+
if (ret != -EINVAL)
1072
+
return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n");
1073
+
1074
+
scp_cluster->l1tcm_base = NULL;
1075
+
} else {
1076
+
scp_cluster->l1tcm_size = resource_size(res);
1077
+
scp_cluster->l1tcm_phys = res->start;
1078
+
}
1079
+
1080
+
INIT_LIST_HEAD(&scp_cluster->mtk_scp_list);
1081
+
mutex_init(&scp_cluster->cluster_lock);
1082
+
1083
+
ret = devm_of_platform_populate(dev);
1084
+
if (ret)
1085
+
return dev_err_probe(dev, ret, "Failed to populate platform devices\n");
1086
+
1087
+
ret = scp_cluster_init(pdev, scp_cluster);
1088
+
if (ret)
1089
+
return ret;
1090
+
1091
+
return 0;
1092
+
}
1093
+
1094
+
static void scp_remove(struct platform_device *pdev)
1095
+
{
1096
+
struct mtk_scp *scp = platform_get_drvdata(pdev);
1097
+
struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
1098
+
struct mtk_scp *temp;
1099
+
1100
+
list_for_each_entry_safe_reverse(scp, temp, &scp_cluster->mtk_scp_list, elem) {
1101
+
list_del(&scp->elem);
1102
+
rproc_del(scp->rproc);
1103
+
scp_free(scp);
1104
+
}
1105
+
mutex_destroy(&scp_cluster->cluster_lock);
1051
1106
}
1052
1107
1053
1108
static const struct mtk_scp_of_data mt8183_of_data = {
···
1281
980
static const struct mtk_scp_of_data mt8195_of_data = {
1282
981
.scp_clk_get = mt8195_scp_clk_get,
1283
982
.scp_before_load = mt8195_scp_before_load,
1284
-
.scp_irq_handler = mt8192_scp_irq_handler,
983
+
.scp_irq_handler = mt8195_scp_irq_handler,
1285
984
.scp_reset_assert = mt8192_scp_reset_assert,
1286
985
.scp_reset_deassert = mt8192_scp_reset_deassert,
1287
986
.scp_stop = mt8195_scp_stop,
···
1290
989
.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
1291
990
};
1292
991
992
+
static const struct mtk_scp_of_data mt8195_of_data_c1 = {
993
+
.scp_clk_get = mt8195_scp_clk_get,
994
+
.scp_before_load = mt8195_scp_c1_before_load,
995
+
.scp_irq_handler = mt8195_scp_c1_irq_handler,
996
+
.scp_reset_assert = mt8195_scp_c1_reset_assert,
997
+
.scp_reset_deassert = mt8195_scp_c1_reset_deassert,
998
+
.scp_stop = mt8195_scp_c1_stop,
999
+
.scp_da_to_va = mt8192_scp_da_to_va,
1000
+
.host_to_scp_reg = MT8192_GIPC_IN_SET,
1001
+
.host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT,
1002
+
};
1003
+
1004
+
static const struct mtk_scp_of_data *mt8195_of_data_cores[] = {
1005
+
&mt8195_of_data,
1006
+
&mt8195_of_data_c1,
1007
+
NULL
1008
+
};
1009
+
1293
1010
static const struct of_device_id mtk_scp_of_match[] = {
1294
1011
{ .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data },
1295
1012
{ .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data },
1296
1013
{ .compatible = "mediatek,mt8188-scp", .data = &mt8188_of_data },
1297
1014
{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data },
1298
1015
{ .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data },
1016
+
{ .compatible = "mediatek,mt8195-scp-dual", .data = &mt8195_of_data_cores },
1299
1017
{},
1300
1018
};
1301
1019
MODULE_DEVICE_TABLE(of, mtk_scp_of_match);
+2
-2
drivers/remoteproc/mtk_scp_ipi.c
+2
-2
drivers/remoteproc/mtk_scp_ipi.c
···
177
177
mutex_lock(&scp->send_lock);
178
178
179
179
/* Wait until SCP receives the last command */
180
-
ret = readl_poll_timeout_atomic(scp->reg_base + scp->data->host_to_scp_reg,
180
+
ret = readl_poll_timeout_atomic(scp->cluster->reg_base + scp->data->host_to_scp_reg,
181
181
val, !val, 0, SCP_TIMEOUT_US);
182
182
if (ret) {
183
183
dev_err(scp->dev, "%s: IPI timeout!\n", __func__);
···
192
192
scp->ipi_id_ack[id] = false;
193
193
/* send the command to SCP */
194
194
writel(scp->data->host_to_scp_int_bit,
195
-
scp->reg_base + scp->data->host_to_scp_reg);
195
+
scp->cluster->reg_base + scp->data->host_to_scp_reg);
196
196
197
197
if (wait) {
198
198
/* wait for SCP's ACK */
-1
drivers/remoteproc/qcom_q6v5_mss.c
-1
drivers/remoteproc/qcom_q6v5_mss.c
+19
drivers/remoteproc/qcom_q6v5_pas.c
+19
drivers/remoteproc/qcom_q6v5_pas.c
···
813
813
.ssctl_id = 0x14,
814
814
};
815
815
816
+
static const struct adsp_data sm6375_mpss_resource = {
817
+
.crash_reason_smem = 421,
818
+
.firmware_name = "modem.mdt",
819
+
.pas_id = 4,
820
+
.minidump_id = 3,
821
+
.auto_boot = false,
822
+
.proxy_pd_names = (char*[]){
823
+
"cx",
824
+
NULL
825
+
},
826
+
.ssr_name = "mpss",
827
+
.sysmon_name = "modem",
828
+
.ssctl_id = 0x12,
829
+
};
830
+
816
831
static const struct adsp_data sm8150_adsp_resource = {
817
832
.crash_reason_smem = 423,
818
833
.firmware_name = "adsp.mdt",
···
1176
1161
{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
1177
1162
{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
1178
1163
{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
1164
+
{ .compatible = "qcom,sc7180-adsp-pas", .data = &sm8250_adsp_resource},
1179
1165
{ .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
1180
1166
{ .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init},
1181
1167
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource},
···
1196
1180
{ .compatible = "qcom,sm6350-adsp-pas", .data = &sm6350_adsp_resource},
1197
1181
{ .compatible = "qcom,sm6350-cdsp-pas", .data = &sm6350_cdsp_resource},
1198
1182
{ .compatible = "qcom,sm6350-mpss-pas", .data = &mpss_resource_init},
1183
+
{ .compatible = "qcom,sm6375-adsp-pas", .data = &sm6350_adsp_resource},
1184
+
{ .compatible = "qcom,sm6375-cdsp-pas", .data = &sm8150_cdsp_resource},
1185
+
{ .compatible = "qcom,sm6375-mpss-pas", .data = &sm6375_mpss_resource},
1199
1186
{ .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
1200
1187
{ .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
1201
1188
{ .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init},
+6
-10
drivers/remoteproc/st_remoteproc.c
+6
-10
drivers/remoteproc/st_remoteproc.c
···
16
16
#include <linux/mfd/syscon.h>
17
17
#include <linux/module.h>
18
18
#include <linux/of.h>
19
-
#include <linux/of_address.h>
20
-
#include <linux/of_device.h>
21
19
#include <linux/of_reserved_mem.h>
22
20
#include <linux/platform_device.h>
21
+
#include <linux/property.h>
23
22
#include <linux/regmap.h>
24
23
#include <linux/remoteproc.h>
25
24
#include <linux/reset.h>
···
340
341
static int st_rproc_probe(struct platform_device *pdev)
341
342
{
342
343
struct device *dev = &pdev->dev;
343
-
const struct of_device_id *match;
344
344
struct st_rproc *ddata;
345
345
struct device_node *np = dev->of_node;
346
346
struct rproc *rproc;
···
347
349
int enabled;
348
350
int ret, i;
349
351
350
-
match = of_match_device(st_rproc_match, dev);
351
-
if (!match || !match->data) {
352
-
dev_err(dev, "No device match found\n");
353
-
return -ENODEV;
354
-
}
355
-
356
352
rproc = rproc_alloc(dev, np->name, &st_rproc_ops, NULL, sizeof(*ddata));
357
353
if (!rproc)
358
354
return -ENOMEM;
359
355
360
356
rproc->has_iommu = false;
361
357
ddata = rproc->priv;
362
-
ddata->config = (struct st_rproc_config *)match->data;
358
+
ddata->config = (struct st_rproc_config *)device_get_match_data(dev);
359
+
if (!ddata->config) {
360
+
ret = -ENODEV;
361
+
goto free_rproc;
362
+
}
363
363
364
364
platform_set_drvdata(pdev, rproc);
365
365
+2
-2
drivers/remoteproc/stm32_rproc.c
+2
-2
drivers/remoteproc/stm32_rproc.c
···
712
712
unsigned int tzen;
713
713
int err, irq;
714
714
715
-
irq = platform_get_irq(pdev, 0);
715
+
irq = platform_get_irq_optional(pdev, 0);
716
716
if (irq == -EPROBE_DEFER)
717
-
return dev_err_probe(dev, irq, "failed to get interrupt\n");
717
+
return irq;
718
718
719
719
if (irq > 0) {
720
720
err = devm_request_irq(dev, irq, stm32_rproc_wdg, 0,
+57
-55
drivers/remoteproc/xlnx_r5_remoteproc.c
+57
-55
drivers/remoteproc/xlnx_r5_remoteproc.c
···
39
39
* struct mem_bank_data - Memory Bank description
40
40
*
41
41
* @addr: Start address of memory bank
42
+
* @da: device address
42
43
* @size: Size of Memory bank
43
44
* @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
44
45
* @bank_name: name of the bank for remoteproc framework
45
46
*/
46
47
struct mem_bank_data {
47
48
phys_addr_t addr;
49
+
u32 da;
48
50
size_t size;
49
51
u32 pm_domain_id;
50
52
char *bank_name;
···
77
75
* Hardcoded TCM bank values. This will be removed once TCM bindings are
78
76
* accepted for system-dt specifications and upstreamed in linux kernel
79
77
*/
80
-
static const struct mem_bank_data zynqmp_tcm_banks[] = {
81
-
{0xffe00000UL, 0x10000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 64KB each */
82
-
{0xffe20000UL, 0x10000UL, PD_R5_0_BTCM, "btcm0"},
83
-
{0xffe90000UL, 0x10000UL, PD_R5_1_ATCM, "atcm1"},
84
-
{0xffeb0000UL, 0x10000UL, PD_R5_1_BTCM, "btcm1"},
78
+
static const struct mem_bank_data zynqmp_tcm_banks_split[] = {
79
+
{0xffe00000UL, 0x0, 0x10000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 64KB each */
80
+
{0xffe20000UL, 0x20000, 0x10000UL, PD_R5_0_BTCM, "btcm0"},
81
+
{0xffe90000UL, 0x0, 0x10000UL, PD_R5_1_ATCM, "atcm1"},
82
+
{0xffeb0000UL, 0x20000, 0x10000UL, PD_R5_1_BTCM, "btcm1"},
83
+
};
84
+
85
+
/* In lockstep mode cluster combines each 64KB TCM and makes 128KB TCM */
86
+
static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = {
87
+
{0xffe00000UL, 0x0, 0x20000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 128KB each */
88
+
{0xffe20000UL, 0x20000, 0x20000UL, PD_R5_0_BTCM, "btcm0"},
89
+
{0, 0, 0, PD_R5_1_ATCM, ""},
90
+
{0, 0, 0, PD_R5_1_BTCM, ""},
85
91
};
86
92
87
93
/**
···
536
526
/* clear TCMs */
537
527
memset_io(va, 0, mem->len);
538
528
539
-
/*
540
-
* The R5s expect their TCM banks to be at address 0x0 and 0x2000,
541
-
* while on the Linux side they are at 0xffexxxxx.
542
-
*
543
-
* Zero out the high 12 bits of the address. This will give
544
-
* expected values for TCM Banks 0A and 0B (0x0 and 0x20000).
545
-
*/
546
-
mem->da &= 0x000fffff;
547
-
548
-
/*
549
-
* TCM Banks 1A and 1B still have to be translated.
550
-
*
551
-
* Below handle these two banks' absolute addresses (0xffe90000 and
552
-
* 0xffeb0000) and convert to the expected relative addresses
553
-
* (0x0 and 0x20000).
554
-
*/
555
-
if (mem->da == 0x90000 || mem->da == 0xB0000)
556
-
mem->da -= 0x90000;
557
-
558
-
/* if translated TCM bank address is not valid report error */
559
-
if (mem->da != 0x0 && mem->da != 0x20000) {
560
-
dev_err(&rproc->dev, "invalid TCM address: %x\n", mem->da);
561
-
return -EINVAL;
562
-
}
563
529
return 0;
564
530
}
565
531
···
557
571
u32 pm_domain_id;
558
572
size_t bank_size;
559
573
char *bank_name;
574
+
u32 da;
560
575
561
576
r5_core = rproc->priv;
562
577
dev = r5_core->dev;
···
570
583
*/
571
584
for (i = 0; i < num_banks; i++) {
572
585
bank_addr = r5_core->tcm_banks[i]->addr;
586
+
da = r5_core->tcm_banks[i]->da;
573
587
bank_name = r5_core->tcm_banks[i]->bank_name;
574
588
bank_size = r5_core->tcm_banks[i]->size;
575
589
pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
···
583
595
goto release_tcm_split;
584
596
}
585
597
586
-
dev_dbg(dev, "TCM carveout split mode %s addr=%llx, size=0x%lx",
587
-
bank_name, bank_addr, bank_size);
598
+
dev_dbg(dev, "TCM carveout split mode %s addr=%llx, da=0x%x, size=0x%lx",
599
+
bank_name, bank_addr, da, bank_size);
588
600
589
601
rproc_mem = rproc_mem_entry_init(dev, NULL, bank_addr,
590
-
bank_size, bank_addr,
602
+
bank_size, da,
591
603
tcm_mem_map, tcm_mem_unmap,
592
604
bank_name);
593
605
if (!rproc_mem) {
···
628
640
struct device *dev;
629
641
u32 pm_domain_id;
630
642
char *bank_name;
643
+
u32 da;
631
644
632
645
r5_core = rproc->priv;
633
646
dev = r5_core->dev;
···
639
650
/*
640
651
* In lockstep mode, TCM is contiguous memory block
641
652
* However, each TCM block still needs to be enabled individually.
642
-
* So, Enable each TCM block individually, but add their size
643
-
* to create contiguous memory region.
653
+
* So, Enable each TCM block individually.
654
+
* Although ATCM and BTCM is contiguous memory block, add two separate
655
+
* carveouts for both.
644
656
*/
645
-
bank_addr = r5_core->tcm_banks[0]->addr;
646
-
bank_name = r5_core->tcm_banks[0]->bank_name;
647
-
648
657
for (i = 0; i < num_banks; i++) {
649
-
bank_size += r5_core->tcm_banks[i]->size;
650
658
pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
651
659
652
660
/* Turn on each TCM bank individually */
···
654
668
dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id);
655
669
goto release_tcm_lockstep;
656
670
}
671
+
672
+
bank_size = r5_core->tcm_banks[i]->size;
673
+
if (bank_size == 0)
674
+
continue;
675
+
676
+
bank_addr = r5_core->tcm_banks[i]->addr;
677
+
da = r5_core->tcm_banks[i]->da;
678
+
bank_name = r5_core->tcm_banks[i]->bank_name;
679
+
680
+
/* Register TCM address range, TCM map and unmap functions */
681
+
rproc_mem = rproc_mem_entry_init(dev, NULL, bank_addr,
682
+
bank_size, da,
683
+
tcm_mem_map, tcm_mem_unmap,
684
+
bank_name);
685
+
if (!rproc_mem) {
686
+
ret = -ENOMEM;
687
+
zynqmp_pm_release_node(pm_domain_id);
688
+
goto release_tcm_lockstep;
689
+
}
690
+
691
+
/* If registration is success, add carveouts */
692
+
rproc_add_carveout(rproc, rproc_mem);
693
+
694
+
dev_dbg(dev, "TCM carveout lockstep mode %s addr=0x%llx, da=0x%x, size=0x%lx",
695
+
bank_name, bank_addr, da, bank_size);
657
696
}
658
-
659
-
dev_dbg(dev, "TCM add carveout lockstep mode %s addr=0x%llx, size=0x%lx",
660
-
bank_name, bank_addr, bank_size);
661
-
662
-
/* Register TCM address range, TCM map and unmap functions */
663
-
rproc_mem = rproc_mem_entry_init(dev, NULL, bank_addr,
664
-
bank_size, bank_addr,
665
-
tcm_mem_map, tcm_mem_unmap,
666
-
bank_name);
667
-
if (!rproc_mem) {
668
-
ret = -ENOMEM;
669
-
goto release_tcm_lockstep;
670
-
}
671
-
672
-
/* If registration is success, add carveouts */
673
-
rproc_add_carveout(rproc, rproc_mem);
674
697
675
698
return 0;
676
699
···
890
895
*/
891
896
static int zynqmp_r5_get_tcm_node(struct zynqmp_r5_cluster *cluster)
892
897
{
898
+
const struct mem_bank_data *zynqmp_tcm_banks;
893
899
struct device *dev = cluster->dev;
894
900
struct zynqmp_r5_core *r5_core;
895
901
int tcm_bank_count, tcm_node;
896
902
int i, j;
897
903
898
-
tcm_bank_count = ARRAY_SIZE(zynqmp_tcm_banks);
904
+
if (cluster->mode == SPLIT_MODE) {
905
+
zynqmp_tcm_banks = zynqmp_tcm_banks_split;
906
+
tcm_bank_count = ARRAY_SIZE(zynqmp_tcm_banks_split);
907
+
} else {
908
+
zynqmp_tcm_banks = zynqmp_tcm_banks_lockstep;
909
+
tcm_bank_count = ARRAY_SIZE(zynqmp_tcm_banks_lockstep);
910
+
}
899
911
900
912
/* count per core tcm banks */
901
913
tcm_bank_count = tcm_bank_count / cluster->core_count;