Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: Force enable 3DLUT DMA check for dcn401 in DML

[WHY]
Currently TR0 (trip 0) is not properly budgeting for urgent latency in
DML2.1. This results in overly aggressive prefetch schedules that are
vulnerable to request return jitter, resulting in severe underflow at
the start of the frame.

[HOW]
Forcing 3DLUT DMA check to enable causes urgent latency to be budgeted
properly into the prefetch schedule, avoiding the vulnerability.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Dillon Varone and committed by
Alex Deucher
b8dc6ca0 51d334d6

+6 -2
+4 -2
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
··· 816 816 817 817 if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { 818 818 plane->tdlut.setup_for_tdlut = true; 819 + 819 820 switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.layout) { 820 821 case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: 821 822 case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: ··· 826 825 plane->tdlut.tdlut_addressing_mode = dml2_tdlut_simple_linear; 827 826 break; 828 827 } 828 + 829 829 switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.size) { 830 830 case DC_CM2_GPU_MEM_SIZE_171717: 831 831 plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube; ··· 835 833 //plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined 836 834 break; 837 835 } 838 - } else 839 - plane->tdlut.setup_for_tdlut = false; 836 + } 837 + plane->tdlut.setup_for_tdlut |= dml_ctx->config.force_tdlut_enable; 840 838 841 839 plane->dynamic_meta_data.enable = false; 842 840 plane->dynamic_meta_data.lines_before_active_required = 0;
+1
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
··· 236 236 237 237 bool use_clock_dc_limits; 238 238 bool gpuvm_enable; 239 + bool force_tdlut_enable; 239 240 struct dml2_soc_bb *bb_from_dmub; 240 241 }; 241 242
+1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
··· 2099 2099 dc->dml2_options.use_native_soc_bb_construction = true; 2100 2100 dc->dml2_options.minimize_dispclk_using_odm = true; 2101 2101 dc->dml2_options.map_dc_pipes_with_callbacks = true; 2102 + dc->dml2_options.force_tdlut_enable = true; 2102 2103 2103 2104 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); 2104 2105 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;