MIPS: Loongson: Remove set_irq_trigger_mode()

set_irq_trigger_mode() is not needed on all platforms so remove it
and move the related source code to mach_init_irq().

This will allow gdium to share the common irq.c without adding an empty
set_irq_trigger_mode().

Signed-off-by: Wu Zhangjin <[e-mail]>
Cc: [e-mail]
Patchwork: https://patchwork.linux-mips.org/patch/1493/
Signed-off-by: Ralf Baechle <[e-mail]>

arch/mips/include/asm/mach-loongson/loongson.h

···
 /* irq operation functions */
 extern void bonito_irqdispatch(void);
 extern void __init bonito_irq_init(void);
-extern void __init set_irq_trigger_mode(void);
 extern void __init mach_init_irq(void);
 extern void mach_irq_dispatch(unsigned int pending);
 extern int mach_i8259_irq(void);

arch/mips/loongson/common/irq.c

···
 	 */
 	clear_c0_status(ST0_IM | ST0_BEV);
 
-	/* setting irq trigger mode */
-	set_irq_trigger_mode();
-
 	/* no steer */
 	LOONGSON_INTSTEER = 0;
 

arch/mips/loongson/fuloong-2e/irq.c

···
 	.name = "cascade",
 };
 
-void __init set_irq_trigger_mode(void)
-{
-	/* most bonito irq should be level triggered */
-	LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
-	    LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
-}
-
 void __init mach_init_irq(void)
 {
 	/* init all controller
···
 	 *   16-23        ------> mips cpu interrupt
 	 *   32-63        ------> bonito irq
 	 */
+
+	/* most bonito irq should be level triggered */
+	LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
+	    LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
 
 	/* Sets the first-level interrupt dispatcher. */
 	mips_cpu_irq_init();

arch/mips/loongson/lemote-2f/irq.c

···
 		spurious_interrupt();
 }
 
-void __init set_irq_trigger_mode(void)
-{
-	/* setup cs5536 as high level trigger */
-	LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
-	LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
-}
-
 static irqreturn_t ip6_action(int cpl, void *dev_id)
 {
 	return IRQ_HANDLED;
···
 	 *   16-23        ------> mips cpu interrupt
 	 *   32-63        ------> bonito irq
 	 */
+
+	/* setup cs5536 as high level trigger */
+	LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
+	LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
 
 	/* Sets the first-level interrupt dispatcher. */
 	mips_cpu_irq_init();