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ARM: mediatek: dts: Add uart to mt6592
This patch adds the uart ports and the uart clock to Mediateks
mt6592 SoC.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+38
+38
arch/arm/boot/dts/mt6592.dtsi
+38
arch/arm/boot/dts/mt6592.dtsi
···
78
78
#clock-cells = <0>;
79
79
};
80
80
81
+
uart_clk: dummy26m {
82
+
compatible = "fixed-clock";
83
+
clock-frequency = <26000000>;
84
+
#clock-cells = <0>;
85
+
};
86
+
81
87
timer: timer@10008000 {
82
88
compatible = "mediatek,mt6577-timer";
83
89
reg = <0x10008000 0x80>;
···
107
101
interrupt-parent = <&gic>;
108
102
reg = <0x10211000 0x1000>,
109
103
<0x10212000 0x1000>;
104
+
};
105
+
106
+
uart0: serial@11002000 {
107
+
compatible = "mediatek,mt6577-uart";
108
+
reg = <0x11002000 0x400>;
109
+
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
110
+
clocks = <&uart_clk>;
111
+
status = "disabled";
112
+
};
113
+
114
+
uart1: serial@11003000 {
115
+
compatible = "mediatek,mt6577-uart";
116
+
reg = <0x11003000 0x400>;
117
+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
118
+
clocks = <&uart_clk>;
119
+
status = "disabled";
120
+
};
121
+
122
+
uart2: serial@11004000 {
123
+
compatible = "mediatek,mt6577-uart";
124
+
reg = <0x11004000 0x400>;
125
+
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
126
+
clocks = <&uart_clk>;
127
+
status = "disabled";
128
+
};
129
+
130
+
uart3: serial@11005000 {
131
+
compatible = "mediatek,mt6577-uart";
132
+
reg = <0x11005000 0x400>;
133
+
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
134
+
clocks = <&uart_clk>;
135
+
status = "disabled";
110
136
};
111
137
};