drm/amd/pp: use soc15 common macros instead of vega10 specific

+3 -4

drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

··· 34 34 #include "rv_ppsmc.h" 35 35 #include "smu10_hwmgr.h" 36 36 #include "power_state.h" 37 - #include "pp_soc15.h" 37 + #include "soc15_common.h" 38 38 39 39 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5 40 40 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */ ··· 947 947 948 948 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr) 949 949 { 950 - uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0, 951 - mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP); 952 - uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset); 950 + struct amdgpu_device *adev = hwmgr->adev; 951 + uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); 953 952 int cur_temp = 954 953 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT; 955 954

+5 -11

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

··· 36 36 #include "smu9.h" 37 37 #include "smu9_driver_if.h" 38 38 #include "vega10_inc.h" 39 - #include "pp_soc15.h" 39 + #include "soc15_common.h" 40 40 #include "pppcielanes.h" 41 41 #include "vega10_hwmgr.h" 42 42 #include "vega10_processpptables.h" ··· 754 754 uint32_t config_telemetry = 0; 755 755 struct pp_atomfwctrl_voltage_table vol_table; 756 756 struct amdgpu_device *adev = hwmgr->adev; 757 - uint32_t reg; 758 757 759 758 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); 760 759 if (data == NULL) ··· 859 860 advanceFanControlParameters.usFanPWMMinLimit * 860 861 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 861 862 862 - reg = soc15_get_register_offset(DF_HWID, 0, 863 - mmDF_CS_AON0_DramBaseAddress0_BASE_IDX, 864 - mmDF_CS_AON0_DramBaseAddress0); 865 - data->mem_channels = (cgs_read_register(hwmgr->device, reg) & 863 + data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & 866 864 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> 867 865 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 868 866 PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), ··· 3804 3808 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 3805 3809 void *value, int *size) 3806 3810 { 3811 + struct amdgpu_device *adev = hwmgr->adev; 3807 3812 uint32_t sclk_idx, mclk_idx, activity_percent = 0; 3808 3813 struct vega10_hwmgr *data = hwmgr->backend; 3809 3814 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3810 3815 int ret = 0; 3811 - uint32_t reg, val_vid; 3816 + uint32_t val_vid; 3812 3817 3813 3818 switch (idx) { 3814 3819 case AMDGPU_PP_SENSOR_GFX_SCLK: ··· 3859 3862 } 3860 3863 break; 3861 3864 case AMDGPU_PP_SENSOR_VDDGFX: 3862 - reg = soc15_get_register_offset(SMUIO_HWID, 0, 3863 - mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX, 3864 - mmSMUSVI0_PLANE0_CURRENTVID); 3865 - val_vid = (cgs_read_register(hwmgr->device, reg) & 3865 + val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & 3866 3866 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >> 3867 3867 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT; 3868 3868 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);

+20 -30

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c

··· 27 27 #include "vega10_ppsmc.h" 28 28 #include "vega10_inc.h" 29 29 #include "pp_debug.h" 30 - #include "pp_soc15.h" 30 + #include "soc15_common.h" 31 31 32 32 static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] = 33 33 { ··· 888 888 if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) { 889 889 if (PP_CAP(PHM_PlatformCaps_SQRamping)) { 890 890 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); 891 - data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en); 892 - data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en); 891 + data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en); 892 + data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en); 893 893 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data); 894 894 } 895 895 896 896 if (PP_CAP(PHM_PlatformCaps_DBRamping)) { 897 897 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL); 898 - data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en); 899 - data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en); 898 + data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en); 899 + data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en); 900 900 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data); 901 901 } 902 902 903 903 if (PP_CAP(PHM_PlatformCaps_TDRamping)) { 904 904 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); 905 - data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en); 906 - data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en); 905 + data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en); 906 + data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en); 907 907 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data); 908 908 } 909 909 910 910 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { 911 911 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL); 912 - data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en); 913 - data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en); 912 + data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en); 913 + data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en); 914 914 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data); 915 915 } 916 916 917 917 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { 918 918 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL); 919 - data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en); 920 - data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en); 919 + data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en); 920 + data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en); 921 921 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data); 922 922 } 923 923 } ··· 933 933 struct amdgpu_device *adev = hwmgr->adev; 934 934 int result; 935 935 uint32_t num_se = 0, count, data; 936 - uint32_t reg; 937 936 938 937 num_se = adev->gfx.config.max_shader_engines; 939 938 940 939 adev->gfx.rlc.funcs->enter_safe_mode(adev); 941 940 942 941 mutex_lock(&adev->grbm_idx_mutex); 943 - reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 944 942 for (count = 0; count < num_se; count++) { 945 943 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 946 - cgs_write_register(hwmgr->device, reg, data); 944 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 947 945 948 946 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); 949 947 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); ··· 956 958 if (0 != result) 957 959 break; 958 960 } 959 - cgs_write_register(hwmgr->device, reg, 0xE0000000); 961 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 960 962 mutex_unlock(&adev->grbm_idx_mutex); 961 963 962 964 vega10_didt_set_mask(hwmgr, true); ··· 984 986 struct amdgpu_device *adev = hwmgr->adev; 985 987 int result; 986 988 uint32_t num_se = 0, count, data; 987 - uint32_t reg; 988 989 989 990 num_se = adev->gfx.config.max_shader_engines; 990 991 991 992 adev->gfx.rlc.funcs->enter_safe_mode(adev); 992 993 993 994 mutex_lock(&adev->grbm_idx_mutex); 994 - reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 995 995 for (count = 0; count < num_se; count++) { 996 996 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 997 - cgs_write_register(hwmgr->device, reg, data); 997 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 998 998 999 999 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); 1000 1000 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); ··· 1001 1005 if (0 != result) 1002 1006 break; 1003 1007 } 1004 - cgs_write_register(hwmgr->device, reg, 0xE0000000); 1008 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1005 1009 mutex_unlock(&adev->grbm_idx_mutex); 1006 1010 1007 1011 vega10_didt_set_mask(hwmgr, true); ··· 1045 1049 struct amdgpu_device *adev = hwmgr->adev; 1046 1050 int result; 1047 1051 uint32_t num_se = 0, count, data; 1048 - uint32_t reg; 1049 1052 1050 1053 num_se = adev->gfx.config.max_shader_engines; 1051 1054 1052 1055 adev->gfx.rlc.funcs->enter_safe_mode(adev); 1053 1056 1054 1057 mutex_lock(&adev->grbm_idx_mutex); 1055 - reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 1056 1058 for (count = 0; count < num_se; count++) { 1057 1059 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1058 - cgs_write_register(hwmgr->device, reg, data); 1060 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1059 1061 result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1060 1062 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1061 1063 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); ··· 1064 1070 if (0 != result) 1065 1071 break; 1066 1072 } 1067 - cgs_write_register(hwmgr->device, reg, 0xE0000000); 1073 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1068 1074 mutex_unlock(&adev->grbm_idx_mutex); 1069 1075 1070 1076 vega10_didt_set_mask(hwmgr, true); ··· 1093 1099 int result; 1094 1100 uint32_t num_se = 0; 1095 1101 uint32_t count, data; 1096 - uint32_t reg; 1097 1102 1098 1103 num_se = adev->gfx.config.max_shader_engines; 1099 1104 ··· 1101 1108 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); 1102 1109 1103 1110 mutex_lock(&adev->grbm_idx_mutex); 1104 - reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 1105 1111 for (count = 0; count < num_se; count++) { 1106 1112 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1107 - cgs_write_register(hwmgr->device, reg, data); 1113 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1108 1114 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1109 1115 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1110 1116 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); ··· 1112 1120 if (0 != result) 1113 1121 break; 1114 1122 } 1115 - cgs_write_register(hwmgr->device, reg, 0xE0000000); 1123 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1116 1124 mutex_unlock(&adev->grbm_idx_mutex); 1117 1125 1118 1126 vega10_didt_set_mask(hwmgr, true); ··· 1157 1165 static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) 1158 1166 { 1159 1167 struct amdgpu_device *adev = hwmgr->adev; 1160 - uint32_t reg; 1161 1168 int result; 1162 1169 1163 1170 adev->gfx.rlc.funcs->enter_safe_mode(adev); 1164 1171 1165 1172 mutex_lock(&adev->grbm_idx_mutex); 1166 - reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 1167 - cgs_write_register(hwmgr->device, reg, 0xE0000000); 1173 + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1168 1174 mutex_unlock(&adev->grbm_idx_mutex); 1169 1175 1170 1176 result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);

+41 -66

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

··· 25 25 #include "vega10_hwmgr.h" 26 26 #include "vega10_ppsmc.h" 27 27 #include "vega10_inc.h" 28 - #include "pp_soc15.h" 28 + #include "soc15_common.h" 29 29 #include "pp_debug.h" 30 30 31 31 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) ··· 89 89 90 90 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) 91 91 { 92 + struct amdgpu_device *adev = hwmgr->adev; 92 93 struct vega10_hwmgr *data = hwmgr->backend; 93 94 uint32_t tach_period; 94 95 uint32_t crystal_clock_freq; ··· 101 100 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 102 101 result = vega10_get_current_rpm(hwmgr, speed); 103 102 } else { 104 - uint32_t reg = soc15_get_register_offset(THM_HWID, 0, 105 - mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS); 106 103 tach_period = 107 - CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg), 104 + REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), 108 105 CG_TACH_STATUS, 109 106 TACH_PERIOD); 110 107 ··· 126 127 */ 127 128 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 128 129 { 129 - uint32_t reg; 130 - 131 - reg = soc15_get_register_offset(THM_HWID, 0, 132 - mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2); 130 + struct amdgpu_device *adev = hwmgr->adev; 133 131 134 132 if (hwmgr->fan_ctrl_is_in_default_mode) { 135 133 hwmgr->fan_ctrl_default_mode = 136 - CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg), 134 + REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 137 135 CG_FDO_CTRL2, FDO_PWM_MODE); 138 136 hwmgr->tmin = 139 - CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg), 137 + REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 140 138 CG_FDO_CTRL2, TMIN); 141 139 hwmgr->fan_ctrl_is_in_default_mode = false; 142 140 } 143 141 144 - cgs_write_register(hwmgr->device, reg, 145 - CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), 142 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 143 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 146 144 CG_FDO_CTRL2, TMIN, 0)); 147 - cgs_write_register(hwmgr->device, reg, 148 - CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), 145 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 146 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 149 147 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 150 148 151 149 return 0; ··· 155 159 */ 156 160 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) 157 161 { 158 - uint32_t reg; 159 - 160 - reg = soc15_get_register_offset(THM_HWID, 0, 161 - mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2); 162 + struct amdgpu_device *adev = hwmgr->adev; 162 163 163 164 if (!hwmgr->fan_ctrl_is_in_default_mode) { 164 - cgs_write_register(hwmgr->device, reg, 165 - CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), 165 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 166 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 166 167 CG_FDO_CTRL2, FDO_PWM_MODE, 167 168 hwmgr->fan_ctrl_default_mode)); 168 - cgs_write_register(hwmgr->device, reg, 169 - CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), 169 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 170 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 170 171 CG_FDO_CTRL2, TMIN, 171 172 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT)); 172 173 hwmgr->fan_ctrl_is_in_default_mode = true; ··· 250 257 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, 251 258 uint32_t speed) 252 259 { 260 + struct amdgpu_device *adev = hwmgr->adev; 253 261 uint32_t duty100; 254 262 uint32_t duty; 255 263 uint64_t tmp64; 256 - uint32_t reg; 257 264 258 265 if (hwmgr->thermal_controller.fanInfo.bNoFan) 259 266 return 0; ··· 264 271 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 265 272 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 266 273 267 - reg = soc15_get_register_offset(THM_HWID, 0, 268 - mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1); 269 - 270 - duty100 = CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg), 274 + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 271 275 CG_FDO_CTRL1, FMAX_DUTY100); 272 276 273 277 if (duty100 == 0) ··· 274 284 do_div(tmp64, 100); 275 285 duty = (uint32_t)tmp64; 276 286 277 - reg = soc15_get_register_offset(THM_HWID, 0, 278 - mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0); 279 - cgs_write_register(hwmgr->device, reg, 280 - CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), 287 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, 288 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), 281 289 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 282 290 283 291 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); ··· 305 317 */ 306 318 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) 307 319 { 320 + struct amdgpu_device *adev = hwmgr->adev; 308 321 uint32_t tach_period; 309 322 uint32_t crystal_clock_freq; 310 323 int result = 0; 311 - uint32_t reg; 312 324 313 325 if (hwmgr->thermal_controller.fanInfo.bNoFan || 314 326 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || ··· 321 333 if (!result) { 322 334 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 323 335 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 324 - reg = soc15_get_register_offset(THM_HWID, 0, 325 - mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS); 326 - cgs_write_register(hwmgr->device, reg, 327 - CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), 336 + WREG32_SOC15(THM, 0, mmCG_TACH_STATUS, 337 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), 328 338 CG_TACH_STATUS, TACH_PERIOD, 329 339 tach_period)); 330 340 } ··· 336 350 */ 337 351 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr) 338 352 { 353 + struct amdgpu_device *adev = hwmgr->adev; 339 354 int temp; 340 - uint32_t reg; 341 355 342 - reg = soc15_get_register_offset(THM_HWID, 0, 343 - mmCG_MULT_THERMAL_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS); 344 - 345 - temp = cgs_read_register(hwmgr->device, reg); 356 + temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); 346 357 347 358 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 348 359 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; ··· 362 379 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, 363 380 struct PP_TemperatureRange *range) 364 381 { 382 + struct amdgpu_device *adev = hwmgr->adev; 365 383 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP * 366 384 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 367 385 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP * 368 386 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 369 - uint32_t val, reg; 387 + uint32_t val; 370 388 371 389 if (low < range->min) 372 390 low = range->min; ··· 377 393 if (low > high) 378 394 return -EINVAL; 379 395 380 - reg = soc15_get_register_offset(THM_HWID, 0, 381 - mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL); 396 + val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 382 397 383 - val = cgs_read_register(hwmgr->device, reg); 384 - 385 - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 386 - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 387 - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); 388 - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); 398 + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 399 + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 400 + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); 401 + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); 389 402 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) & 390 403 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) & 391 404 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK); 392 405 393 - cgs_write_register(hwmgr->device, reg, val); 406 + WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 394 407 395 408 return 0; 396 409 } ··· 399 418 */ 400 419 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) 401 420 { 402 - uint32_t reg; 421 + struct amdgpu_device *adev = hwmgr->adev; 403 422 404 423 if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { 405 - reg = soc15_get_register_offset(THM_HWID, 0, 406 - mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL); 407 - cgs_write_register(hwmgr->device, reg, 408 - CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), 424 + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, 425 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), 409 426 CG_TACH_CTRL, EDGE_PER_REV, 410 427 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1)); 411 428 } 412 429 413 - reg = soc15_get_register_offset(THM_HWID, 0, 414 - mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2); 415 - cgs_write_register(hwmgr->device, reg, 416 - CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), 430 + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 431 + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 417 432 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28)); 418 433 419 434 return 0; ··· 422 445 */ 423 446 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) 424 447 { 448 + struct amdgpu_device *adev = hwmgr->adev; 425 449 struct vega10_hwmgr *data = hwmgr->backend; 426 450 uint32_t val = 0; 427 - uint32_t reg; 428 451 429 452 if (data->smu_features[GNLD_FW_CTF].supported) { 430 453 if (data->smu_features[GNLD_FW_CTF].enabled) ··· 442 465 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 443 466 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 444 467 445 - reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA); 446 - cgs_write_register(hwmgr->device, reg, val); 468 + WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); 447 469 448 470 return 0; 449 471 } ··· 453 477 */ 454 478 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) 455 479 { 480 + struct amdgpu_device *adev = hwmgr->adev; 456 481 struct vega10_hwmgr *data = hwmgr->backend; 457 - uint32_t reg; 458 482 459 483 if (data->smu_features[GNLD_FW_CTF].supported) { 460 484 if (!data->smu_features[GNLD_FW_CTF].enabled) ··· 469 493 data->smu_features[GNLD_FW_CTF].enabled = false; 470 494 } 471 495 472 - reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA); 473 - cgs_write_register(hwmgr->device, reg, 0); 496 + WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); 474 497 475 498 return 0; 476 499 }

-1

drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

··· 34 34 #include "atomfirmware.h" 35 35 #include "cgs_common.h" 36 36 #include "vega12_inc.h" 37 - #include "pp_soc15.h" 38 37 #include "pppcielanes.h" 39 38 #include "vega12_hwmgr.h" 40 39 #include "vega12_processpptables.h"

+15 -22

drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c

··· 26 26 #include "vega12_smumgr.h" 27 27 #include "vega12_ppsmc.h" 28 28 #include "vega12_inc.h" 29 - #include "pp_soc15.h" 29 + #include "soc15_common.h" 30 30 #include "pp_debug.h" 31 31 32 32 static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) ··· 147 147 */ 148 148 int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr) 149 149 { 150 + struct amdgpu_device *adev = hwmgr->adev; 150 151 int temp = 0; 151 - uint32_t reg; 152 152 153 - reg = soc15_get_register_offset(THM_HWID, 0, 154 - mmCG_MULT_THERMAL_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS); 155 - 156 - temp = cgs_read_register(hwmgr->device, reg); 153 + temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); 157 154 158 155 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 159 156 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; ··· 172 175 static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, 173 176 struct PP_TemperatureRange *range) 174 177 { 178 + struct amdgpu_device *adev = hwmgr->adev; 175 179 int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP * 176 180 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 177 181 int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP * 178 182 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 179 - uint32_t val, reg; 183 + uint32_t val; 180 184 181 185 if (low < range->min) 182 186 low = range->min; ··· 187 189 if (low > high) 188 190 return -EINVAL; 189 191 190 - reg = soc15_get_register_offset(THM_HWID, 0, 191 - mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL); 192 + val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 192 193 193 - val = cgs_read_register(hwmgr->device, reg); 194 - 195 - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 196 - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 197 - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); 198 - val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); 194 + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 195 + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 196 + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); 197 + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)); 199 198 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 200 199 201 - cgs_write_register(hwmgr->device, reg, val); 200 + WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 202 201 203 202 return 0; 204 203 } ··· 207 212 */ 208 213 static int vega12_thermal_enable_alert(struct pp_hwmgr *hwmgr) 209 214 { 215 + struct amdgpu_device *adev = hwmgr->adev; 210 216 uint32_t val = 0; 211 - uint32_t reg; 212 217 213 218 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 214 219 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 215 220 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 216 221 217 - reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA); 218 - cgs_write_register(hwmgr->device, reg, val); 222 + WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); 219 223 220 224 return 0; 221 225 } ··· 225 231 */ 226 232 int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr) 227 233 { 228 - uint32_t reg; 234 + struct amdgpu_device *adev = hwmgr->adev; 229 235 230 - reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA); 231 - cgs_write_register(hwmgr->device, reg, 0); 236 + WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); 232 237 233 238 return 0; 234 239 }

-52

drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h

··· 1 - /* 2 - * Copyright 2016 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included in 12 - * all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 - * OTHER DEALINGS IN THE SOFTWARE. 21 - * 22 - */ 23 - #ifndef PP_SOC15_H 24 - #define PP_SOC15_H 25 - 26 - #include "soc15_hw_ip.h" 27 - #include "vega10_ip_offset.h" 28 - 29 - inline static uint32_t soc15_get_register_offset( 30 - uint32_t hw_id, 31 - uint32_t inst, 32 - uint32_t segment, 33 - uint32_t offset) 34 - { 35 - uint32_t reg = 0; 36 - 37 - if (hw_id == THM_HWID) 38 - reg = THM_BASE.instance[inst].segment[segment] + offset; 39 - else if (hw_id == NBIF_HWID) 40 - reg = NBIF_BASE.instance[inst].segment[segment] + offset; 41 - else if (hw_id == MP1_HWID) 42 - reg = MP1_BASE.instance[inst].segment[segment] + offset; 43 - else if (hw_id == DF_HWID) 44 - reg = DF_BASE.instance[inst].segment[segment] + offset; 45 - else if (hw_id == GC_HWID) 46 - reg = GC_BASE.instance[inst].segment[segment] + offset; 47 - else if (hw_id == SMUIO_HWID) 48 - reg = SMUIO_BASE.instance[inst].segment[segment] + offset; 49 - return reg; 50 - } 51 - 52 - #endif

+13 -24

drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c

··· 23 23 24 24 #include "smumgr.h" 25 25 #include "smu10_inc.h" 26 - #include "pp_soc15.h" 26 + #include "soc15_common.h" 27 27 #include "smu10_smumgr.h" 28 28 #include "ppatomctrl.h" 29 29 #include "rv_ppsmc.h" ··· 49 49 50 50 static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr) 51 51 { 52 + struct amdgpu_device *adev = hwmgr->adev; 52 53 uint32_t reg; 53 54 54 - reg = soc15_get_register_offset(MP1_HWID, 0, 55 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 55 + reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 56 56 57 57 phm_wait_for_register_unequal(hwmgr, reg, 58 58 0, MP1_C2PMSG_90__CONTENT_MASK); 59 59 60 - return cgs_read_register(hwmgr->device, reg); 60 + return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); 61 61 } 62 62 63 63 static int smu10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, 64 64 uint16_t msg) 65 65 { 66 - uint32_t reg; 66 + struct amdgpu_device *adev = hwmgr->adev; 67 67 68 - reg = soc15_get_register_offset(MP1_HWID, 0, 69 - mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); 70 - cgs_write_register(hwmgr->device, reg, msg); 68 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); 71 69 72 70 return 0; 73 71 } 74 72 75 73 static int smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr) 76 74 { 77 - uint32_t reg; 75 + struct amdgpu_device *adev = hwmgr->adev; 78 76 79 - reg = soc15_get_register_offset(MP1_HWID, 0, 80 - mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 81 - 82 - return cgs_read_register(hwmgr->device, reg); 77 + return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); 83 78 } 84 79 85 80 static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) 86 81 { 87 - uint32_t reg; 82 + struct amdgpu_device *adev = hwmgr->adev; 88 83 89 84 smu10_wait_for_response(hwmgr); 90 85 91 - reg = soc15_get_register_offset(MP1_HWID, 0, 92 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 93 - cgs_write_register(hwmgr->device, reg, 0); 86 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 94 87 95 88 smu10_send_msg_to_smc_without_waiting(hwmgr, msg); 96 89 ··· 97 104 static int smu10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, 98 105 uint16_t msg, uint32_t parameter) 99 106 { 100 - uint32_t reg; 107 + struct amdgpu_device *adev = hwmgr->adev; 101 108 102 109 smu10_wait_for_response(hwmgr); 103 110 104 - reg = soc15_get_register_offset(MP1_HWID, 0, 105 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 106 - cgs_write_register(hwmgr->device, reg, 0); 111 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 107 112 108 - reg = soc15_get_register_offset(MP1_HWID, 0, 109 - mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 110 - cgs_write_register(hwmgr->device, reg, parameter); 113 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); 111 114 112 115 smu10_send_msg_to_smc_without_waiting(hwmgr, msg); 113 116

+17 -33

drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c

··· 23 23 24 24 #include "smumgr.h" 25 25 #include "vega10_inc.h" 26 - #include "pp_soc15.h" 26 + #include "soc15_common.h" 27 27 #include "vega10_smumgr.h" 28 28 #include "vega10_hwmgr.h" 29 29 #include "vega10_ppsmc.h" ··· 54 54 55 55 static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr) 56 56 { 57 - uint32_t mp1_fw_flags, reg; 57 + struct amdgpu_device *adev = hwmgr->adev; 58 + uint32_t mp1_fw_flags; 58 59 59 - reg = soc15_get_register_offset(NBIF_HWID, 0, 60 - mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); 61 - 62 - cgs_write_register(hwmgr->device, reg, 60 + WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2, 63 61 (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); 64 62 65 - reg = soc15_get_register_offset(NBIF_HWID, 0, 66 - mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); 67 - 68 - mp1_fw_flags = cgs_read_register(hwmgr->device, reg); 63 + mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2); 69 64 70 65 if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) 71 66 return true; ··· 76 81 */ 77 82 static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr) 78 83 { 84 + struct amdgpu_device *adev = hwmgr->adev; 79 85 uint32_t reg; 80 86 uint32_t ret; 81 87 82 - reg = soc15_get_register_offset(MP1_HWID, 0, 83 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 88 + reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 84 89 85 90 ret = phm_wait_for_register_unequal(hwmgr, reg, 86 91 0, MP1_C2PMSG_90__CONTENT_MASK); ··· 88 93 if (ret) 89 94 pr_err("No response from smu\n"); 90 95 91 - return cgs_read_register(hwmgr->device, reg); 96 + return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); 92 97 } 93 98 94 99 /* ··· 100 105 static int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, 101 106 uint16_t msg) 102 107 { 103 - uint32_t reg; 108 + struct amdgpu_device *adev = hwmgr->adev; 104 109 105 - reg = soc15_get_register_offset(MP1_HWID, 0, 106 - mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); 107 - cgs_write_register(hwmgr->device, reg, msg); 110 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); 108 111 109 112 return 0; 110 113 } ··· 115 122 */ 116 123 static int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) 117 124 { 118 - uint32_t reg; 125 + struct amdgpu_device *adev = hwmgr->adev; 119 126 uint32_t ret; 120 127 121 128 vega10_wait_for_response(hwmgr); 122 129 123 - reg = soc15_get_register_offset(MP1_HWID, 0, 124 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 125 - cgs_write_register(hwmgr->device, reg, 0); 130 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 126 131 127 132 vega10_send_msg_to_smc_without_waiting(hwmgr, msg); 128 133 ··· 141 150 static int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, 142 151 uint16_t msg, uint32_t parameter) 143 152 { 144 - uint32_t reg; 153 + struct amdgpu_device *adev = hwmgr->adev; 145 154 uint32_t ret; 146 155 147 156 vega10_wait_for_response(hwmgr); 148 157 149 - reg = soc15_get_register_offset(MP1_HWID, 0, 150 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 151 - cgs_write_register(hwmgr->device, reg, 0); 158 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 152 159 153 - reg = soc15_get_register_offset(MP1_HWID, 0, 154 - mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 155 - cgs_write_register(hwmgr->device, reg, parameter); 160 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); 156 161 157 162 vega10_send_msg_to_smc_without_waiting(hwmgr, msg); 158 163 ··· 161 174 162 175 static int vega10_get_argument(struct pp_hwmgr *hwmgr) 163 176 { 164 - uint32_t reg; 177 + struct amdgpu_device *adev = hwmgr->adev; 165 178 166 - reg = soc15_get_register_offset(MP1_HWID, 0, 167 - mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 168 - 169 - return cgs_read_register(hwmgr->device, reg); 179 + return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); 170 180 } 171 181 172 182 static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,

+19 -37

drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c

··· 23 23 24 24 #include "smumgr.h" 25 25 #include "vega12_inc.h" 26 - #include "pp_soc15.h" 26 + #include "soc15_common.h" 27 27 #include "vega12_smumgr.h" 28 28 #include "vega12_ppsmc.h" 29 29 #include "vega12/smu9_driver_if.h" ··· 44 44 45 45 static bool vega12_is_smc_ram_running(struct pp_hwmgr *hwmgr) 46 46 { 47 - uint32_t mp1_fw_flags, reg; 47 + struct amdgpu_device *adev = hwmgr->adev; 48 + uint32_t mp1_fw_flags; 48 49 49 - reg = soc15_get_register_offset(NBIF_HWID, 0, 50 - mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2); 51 - 52 - cgs_write_register(hwmgr->device, reg, 50 + WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2, 53 51 (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); 54 52 55 - reg = soc15_get_register_offset(NBIF_HWID, 0, 56 - mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2); 57 - 58 - mp1_fw_flags = cgs_read_register(hwmgr->device, reg); 53 + mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2); 59 54 60 55 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 61 56 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) ··· 67 72 */ 68 73 static uint32_t vega12_wait_for_response(struct pp_hwmgr *hwmgr) 69 74 { 75 + struct amdgpu_device *adev = hwmgr->adev; 70 76 uint32_t reg; 71 77 72 - reg = soc15_get_register_offset(MP1_HWID, 0, 73 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 78 + reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 74 79 75 80 phm_wait_for_register_unequal(hwmgr, reg, 76 81 0, MP1_C2PMSG_90__CONTENT_MASK); 77 82 78 - return cgs_read_register(hwmgr->device, reg); 83 + return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); 79 84 } 80 85 81 86 /* ··· 87 92 int vega12_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, 88 93 uint16_t msg) 89 94 { 90 - uint32_t reg; 95 + struct amdgpu_device *adev = hwmgr->adev; 91 96 92 - reg = soc15_get_register_offset(MP1_HWID, 0, 93 - mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); 94 - cgs_write_register(hwmgr->device, reg, msg); 97 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); 95 98 96 99 return 0; 97 100 } ··· 102 109 */ 103 110 int vega12_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) 104 111 { 105 - uint32_t reg; 112 + struct amdgpu_device *adev = hwmgr->adev; 106 113 107 114 vega12_wait_for_response(hwmgr); 108 115 109 - reg = soc15_get_register_offset(MP1_HWID, 0, 110 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 111 - cgs_write_register(hwmgr->device, reg, 0); 116 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 112 117 113 118 vega12_send_msg_to_smc_without_waiting(hwmgr, msg); 114 119 ··· 126 135 int vega12_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, 127 136 uint16_t msg, uint32_t parameter) 128 137 { 129 - uint32_t reg; 138 + struct amdgpu_device *adev = hwmgr->adev; 130 139 131 140 vega12_wait_for_response(hwmgr); 132 141 133 - reg = soc15_get_register_offset(MP1_HWID, 0, 134 - mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90); 135 - cgs_write_register(hwmgr->device, reg, 0); 142 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 136 143 137 - reg = soc15_get_register_offset(MP1_HWID, 0, 138 - mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 139 - cgs_write_register(hwmgr->device, reg, parameter); 144 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); 140 145 141 146 vega12_send_msg_to_smc_without_waiting(hwmgr, msg); 142 147 ··· 153 166 int vega12_send_msg_to_smc_with_parameter_without_waiting( 154 167 struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) 155 168 { 156 - uint32_t reg; 169 + struct amdgpu_device *adev = hwmgr->adev; 157 170 158 - reg = soc15_get_register_offset(MP1_HWID, 0, 159 - mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66); 160 - cgs_write_register(hwmgr->device, reg, parameter); 171 + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, parameter); 161 172 162 173 return vega12_send_msg_to_smc_without_waiting(hwmgr, msg); 163 174 } ··· 168 183 */ 169 184 int vega12_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg) 170 185 { 171 - uint32_t reg; 186 + struct amdgpu_device *adev = hwmgr->adev; 172 187 173 - reg = soc15_get_register_offset(MP1_HWID, 0, 174 - mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82); 175 - 176 - *arg = cgs_read_register(hwmgr->device, reg); 188 + *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); 177 189 178 190 return 0; 179 191 }