PCI: read revision ID by default · tjh.dev/kernel@b8a3a52

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

PCI: read revision ID by default

Currently there are 97 occurrences where drivers need the pci
revision ID. We can do this once for all devices. Even the pci
subsystem needs the revision several times for quirks. The extra
u8 member pads out nicely in the pci_dev struct.

Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

authored by

Auke Kok and committed by

Greg Kroah-Hartman 19 years ago b8a3a521 56906c61

4 changed files

expand all

arch

powerpc

kernel

pci_64.c

sparc64

kernel

pci.c

drivers

pci

probe.c

include

linux

pci.h

arch/powerpc/kernel/pci_64.c

··· 367 367 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), 368 368 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 369 369 dev->class = get_int_prop(node, "class-code", 0); 370 + dev->revision = get_int_prop(node, "revision-id", 0); 370 371 371 372 DBG(" class: 0x%x\n", dev->class); 373 + DBG(" revision: 0x%x\n", dev->revision); 372 374 373 375 dev->current_state = 4; /* unknown power state */ 374 376 dev->error_state = pci_channel_io_normal;

arch/sparc64/kernel/pci.c

··· 448 448 */ 449 449 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 450 450 dev->class = class >> 8; 451 + dev->revision = class & 0xff; 451 452 452 453 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), 453 454 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));

drivers/pci/probe.c

··· 702 702 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 703 703 704 704 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 705 + dev->revision = class & 0xff; 705 706 class >>= 8; /* upper 3 bytes */ 706 707 dev->class = class; 707 708 class >>= 8;

include/linux/pci.h

··· 139 139 unsigned short subsystem_vendor; 140 140 unsigned short subsystem_device; 141 141 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 142 + u8 revision; /* PCI revision, low byte of class word */ 142 143 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 143 144 u8 rom_base_reg; /* which config register controls the ROM */ 144 145 u8 pin; /* which interrupt pin this device uses */