Merge tag 'tty-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

+2 -2

drivers/tty/serial/Kconfig

··· 47 47 48 48 config SERIAL_AMBA_PL011 49 49 tristate "ARM AMBA PL011 serial port support" 50 - depends on ARM_AMBA || SOC_ZX296702 50 + depends on ARM_AMBA 51 51 select SERIAL_CORE 52 52 help 53 53 This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have 54 54 an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M 55 - here. Say Y or M if you have SOC_ZX296702. 55 + here. 56 56 57 57 If unsure, say N. 58 58

+123 -380

drivers/tty/serial/amba-pl011.c

··· 74 74 /* There is by now at least one vendor with differing details, so handle it */ 75 75 struct vendor_data { 76 76 unsigned int ifls; 77 - unsigned int fr_busy; 78 - unsigned int fr_dsr; 79 - unsigned int fr_cts; 80 - unsigned int fr_ri; 81 77 unsigned int lcrh_tx; 82 78 unsigned int lcrh_rx; 83 - u16 *reg_lut; 84 79 bool oversampling; 85 80 bool dma_threshold; 86 81 bool cts_event_workaround; ··· 85 90 unsigned int (*get_fifosize)(struct amba_device *dev); 86 91 }; 87 92 88 - /* Max address offset of register in use is 0x48 */ 89 - #define REG_NR (0x48 >> 2) 90 - #define IDX(x) (x >> 2) 91 - enum reg_idx { 92 - REG_DR = IDX(UART01x_DR), 93 - REG_RSR = IDX(UART01x_RSR), 94 - REG_ST_DMAWM = IDX(ST_UART011_DMAWM), 95 - REG_FR = IDX(UART01x_FR), 96 - REG_ST_LCRH_RX = IDX(ST_UART011_LCRH_RX), 97 - REG_ILPR = IDX(UART01x_ILPR), 98 - REG_IBRD = IDX(UART011_IBRD), 99 - REG_FBRD = IDX(UART011_FBRD), 100 - REG_LCRH = IDX(UART011_LCRH), 101 - REG_CR = IDX(UART011_CR), 102 - REG_IFLS = IDX(UART011_IFLS), 103 - REG_IMSC = IDX(UART011_IMSC), 104 - REG_RIS = IDX(UART011_RIS), 105 - REG_MIS = IDX(UART011_MIS), 106 - REG_ICR = IDX(UART011_ICR), 107 - REG_DMACR = IDX(UART011_DMACR), 108 - }; 109 - 110 - static u16 arm_reg[] = { 111 - [REG_DR] = UART01x_DR, 112 - [REG_RSR] = UART01x_RSR, 113 - [REG_ST_DMAWM] = ~0, 114 - [REG_FR] = UART01x_FR, 115 - [REG_ST_LCRH_RX] = ~0, 116 - [REG_ILPR] = UART01x_ILPR, 117 - [REG_IBRD] = UART011_IBRD, 118 - [REG_FBRD] = UART011_FBRD, 119 - [REG_LCRH] = UART011_LCRH, 120 - [REG_CR] = UART011_CR, 121 - [REG_IFLS] = UART011_IFLS, 122 - [REG_IMSC] = UART011_IMSC, 123 - [REG_RIS] = UART011_RIS, 124 - [REG_MIS] = UART011_MIS, 125 - [REG_ICR] = UART011_ICR, 126 - [REG_DMACR] = UART011_DMACR, 127 - }; 128 - 129 - #ifdef CONFIG_ARM_AMBA 130 93 static unsigned int get_fifosize_arm(struct amba_device *dev) 131 94 { 132 95 return amba_rev(dev) < 3 ? 16 : 32; ··· 92 139 93 140 static struct vendor_data vendor_arm = { 94 141 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 95 - .fr_busy = UART01x_FR_BUSY, 96 - .fr_dsr = UART01x_FR_DSR, 97 - .fr_cts = UART01x_FR_CTS, 98 - .fr_ri = UART011_FR_RI, 99 - .lcrh_tx = REG_LCRH, 100 - .lcrh_rx = REG_LCRH, 101 - .reg_lut = arm_reg, 142 + .lcrh_tx = UART011_LCRH, 143 + .lcrh_rx = UART011_LCRH, 102 144 .oversampling = false, 103 145 .dma_threshold = false, 104 146 .cts_event_workaround = false, ··· 101 153 .fixed_options = false, 102 154 .get_fifosize = get_fifosize_arm, 103 155 }; 104 - #endif 105 156 106 157 static struct vendor_data vendor_sbsa = { 107 - .fr_busy = UART01x_FR_BUSY, 108 - .fr_dsr = UART01x_FR_DSR, 109 - .fr_cts = UART01x_FR_CTS, 110 - .fr_ri = UART011_FR_RI, 111 - .reg_lut = arm_reg, 112 158 .oversampling = false, 113 159 .dma_threshold = false, 114 160 .cts_event_workaround = false, 115 161 .always_enabled = true, 116 162 .fixed_options = true, 117 - }; 118 - 119 - #ifdef CONFIG_ARM_AMBA 120 - static u16 st_reg[] = { 121 - [REG_DR] = UART01x_DR, 122 - [REG_RSR] = UART01x_RSR, 123 - [REG_ST_DMAWM] = ST_UART011_DMAWM, 124 - [REG_FR] = UART01x_FR, 125 - [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX, 126 - [REG_ILPR] = UART01x_ILPR, 127 - [REG_IBRD] = UART011_IBRD, 128 - [REG_FBRD] = UART011_FBRD, 129 - [REG_LCRH] = UART011_LCRH, 130 - [REG_CR] = UART011_CR, 131 - [REG_IFLS] = UART011_IFLS, 132 - [REG_IMSC] = UART011_IMSC, 133 - [REG_RIS] = UART011_RIS, 134 - [REG_MIS] = UART011_MIS, 135 - [REG_ICR] = UART011_ICR, 136 - [REG_DMACR] = UART011_DMACR, 137 163 }; 138 164 139 165 static unsigned int get_fifosize_st(struct amba_device *dev) ··· 117 195 118 196 static struct vendor_data vendor_st = { 119 197 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 120 - .fr_busy = UART01x_FR_BUSY, 121 - .fr_dsr = UART01x_FR_DSR, 122 - .fr_cts = UART01x_FR_CTS, 123 - .fr_ri = UART011_FR_RI, 124 - .lcrh_tx = REG_LCRH, 125 - .lcrh_rx = REG_ST_LCRH_RX, 126 - .reg_lut = st_reg, 198 + .lcrh_tx = ST_UART011_LCRH_TX, 199 + .lcrh_rx = ST_UART011_LCRH_RX, 127 200 .oversampling = true, 128 201 .dma_threshold = true, 129 202 .cts_event_workaround = true, ··· 126 209 .fixed_options = false, 127 210 .get_fifosize = get_fifosize_st, 128 211 }; 129 - #endif 130 - 131 - #ifdef CONFIG_SOC_ZX296702 132 - static u16 zte_reg[] = { 133 - [REG_DR] = ZX_UART01x_DR, 134 - [REG_RSR] = UART01x_RSR, 135 - [REG_ST_DMAWM] = ST_UART011_DMAWM, 136 - [REG_FR] = ZX_UART01x_FR, 137 - [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX, 138 - [REG_ILPR] = UART01x_ILPR, 139 - [REG_IBRD] = UART011_IBRD, 140 - [REG_FBRD] = UART011_FBRD, 141 - [REG_LCRH] = ZX_UART011_LCRH_TX, 142 - [REG_CR] = ZX_UART011_CR, 143 - [REG_IFLS] = ZX_UART011_IFLS, 144 - [REG_IMSC] = ZX_UART011_IMSC, 145 - [REG_RIS] = ZX_UART011_RIS, 146 - [REG_MIS] = ZX_UART011_MIS, 147 - [REG_ICR] = ZX_UART011_ICR, 148 - [REG_DMACR] = ZX_UART011_DMACR, 149 - }; 150 - 151 - static struct vendor_data vendor_zte = { 152 - .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 153 - .fr_busy = ZX_UART01x_FR_BUSY, 154 - .fr_dsr = ZX_UART01x_FR_DSR, 155 - .fr_cts = ZX_UART01x_FR_CTS, 156 - .fr_ri = ZX_UART011_FR_RI, 157 - .lcrh_tx = REG_LCRH, 158 - .lcrh_rx = REG_ST_LCRH_RX, 159 - .reg_lut = zte_reg, 160 - .oversampling = false, 161 - .dma_threshold = false, 162 - .cts_event_workaround = false, 163 - .fixed_options = false, 164 - }; 165 - #endif 166 212 167 213 /* Deals with DMA transactions */ 168 214 ··· 164 284 struct uart_port port; 165 285 struct clk *clk; 166 286 const struct vendor_data *vendor; 167 - u16 *reg_lut; 168 287 unsigned int dmacr; /* dma control reg */ 169 288 unsigned int im; /* interrupt mask */ 170 289 unsigned int old_status; 171 290 unsigned int fifosize; /* vendor-specific */ 172 - unsigned int fr_busy; /* vendor-specific */ 173 - unsigned int fr_dsr; /* vendor-specific */ 174 - unsigned int fr_cts; /* vendor-specific */ 175 - unsigned int fr_ri; /* vendor-specific */ 176 291 unsigned int lcrh_tx; /* vendor-specific */ 177 292 unsigned int lcrh_rx; /* vendor-specific */ 178 293 unsigned int old_cr; /* state during shutdown */ ··· 184 309 #endif 185 310 }; 186 311 187 - static bool is_implemented(struct uart_amba_port *uap, unsigned int reg) 188 - { 189 - return uap->reg_lut[reg] != (u16)~0; 190 - } 191 - 192 - static unsigned int pl011_readw(struct uart_amba_port *uap, int index) 193 - { 194 - WARN_ON(index > REG_NR); 195 - return readw_relaxed(uap->port.membase + uap->reg_lut[index]); 196 - } 197 - 198 - static void pl011_writew(struct uart_amba_port *uap, int val, int index) 199 - { 200 - WARN_ON(index > REG_NR); 201 - writew_relaxed(val, uap->port.membase + uap->reg_lut[index]); 202 - } 203 - 204 - static void pl011_writeb(struct uart_amba_port *uap, u8 val, int index) 205 - { 206 - WARN_ON(index > REG_NR); 207 - writeb_relaxed(val, uap->port.membase + uap->reg_lut[index]); 208 - } 209 - 210 312 /* 211 313 * Reads up to 256 characters from the FIFO or until it's empty and 212 314 * inserts them into the TTY layer. Returns the number of characters ··· 196 344 int fifotaken = 0; 197 345 198 346 while (max_count--) { 199 - status = pl011_readw(uap, REG_FR); 347 + status = readw(uap->port.membase + UART01x_FR); 200 348 if (status & UART01x_FR_RXFE) 201 349 break; 202 350 203 351 /* Take chars from the FIFO and update status */ 204 - ch = pl011_readw(uap, REG_DR) | 352 + ch = readw(uap->port.membase + UART01x_DR) | 205 353 UART_DUMMY_DR_RX; 206 354 flag = TTY_NORMAL; 207 355 uap->port.icount.rx++; ··· 284 432 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 285 433 struct device *dev = uap->port.dev; 286 434 struct dma_slave_config tx_conf = { 287 - .dst_addr = uap->port.mapbase + uap->reg_lut[REG_DR], 435 + .dst_addr = uap->port.mapbase + UART01x_DR, 288 436 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 289 437 .direction = DMA_MEM_TO_DEV, 290 438 .dst_maxburst = uap->fifosize >> 1, ··· 339 487 340 488 if (chan) { 341 489 struct dma_slave_config rx_conf = { 342 - .src_addr = uap->port.mapbase + uap->reg_lut[REG_DR], 490 + .src_addr = uap->port.mapbase + UART01x_DR, 343 491 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 344 492 .direction = DMA_DEV_TO_MEM, 345 493 .src_maxburst = uap->fifosize >> 2, ··· 438 586 439 587 dmacr = uap->dmacr; 440 588 uap->dmacr = dmacr & ~UART011_TXDMAE; 441 - pl011_writew(uap, uap->dmacr, REG_DMACR); 589 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 442 590 443 591 /* 444 592 * If TX DMA was disabled, it means that we've stopped the DMA for ··· 552 700 dma_dev->device_issue_pending(chan); 553 701 554 702 uap->dmacr |= UART011_TXDMAE; 555 - pl011_writew(uap, uap->dmacr, REG_DMACR); 703 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 556 704 uap->dmatx.queued = true; 557 705 558 706 /* ··· 588 736 */ 589 737 if (uap->dmatx.queued) { 590 738 uap->dmacr |= UART011_TXDMAE; 591 - pl011_writew(uap, uap->dmacr, REG_DMACR); 739 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 592 740 uap->im &= ~UART011_TXIM; 593 - pl011_writew(uap, uap->im, REG_IMSC); 741 + writew(uap->im, uap->port.membase + UART011_IMSC); 594 742 return true; 595 743 } 596 744 ··· 600 748 */ 601 749 if (pl011_dma_tx_refill(uap) > 0) { 602 750 uap->im &= ~UART011_TXIM; 603 - pl011_writew(uap, uap->im, REG_IMSC); 751 + writew(uap->im, uap->port.membase + UART011_IMSC); 604 752 return true; 605 753 } 606 754 return false; ··· 614 762 { 615 763 if (uap->dmatx.queued) { 616 764 uap->dmacr &= ~UART011_TXDMAE; 617 - pl011_writew(uap, uap->dmacr, REG_DMACR); 765 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 618 766 } 619 767 } 620 768 ··· 640 788 if (!uap->dmatx.queued) { 641 789 if (pl011_dma_tx_refill(uap) > 0) { 642 790 uap->im &= ~UART011_TXIM; 643 - pl011_writew(uap, uap->im, REG_IMSC); 791 + writew(uap->im, uap->port.membase + 792 + UART011_IMSC); 644 793 } else 645 794 ret = false; 646 795 } else if (!(uap->dmacr & UART011_TXDMAE)) { 647 796 uap->dmacr |= UART011_TXDMAE; 648 - pl011_writew(uap, uap->dmacr, REG_DMACR); 797 + writew(uap->dmacr, 798 + uap->port.membase + UART011_DMACR); 649 799 } 650 800 return ret; 651 801 } ··· 658 804 */ 659 805 dmacr = uap->dmacr; 660 806 uap->dmacr &= ~UART011_TXDMAE; 661 - pl011_writew(uap, uap->dmacr, REG_DMACR); 807 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 662 808 663 - if (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) { 809 + if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { 664 810 /* 665 811 * No space in the FIFO, so enable the transmit interrupt 666 812 * so we know when there is space. Note that once we've ··· 669 815 return false; 670 816 } 671 817 672 - pl011_writew(uap, uap->port.x_char, REG_DR); 818 + writew(uap->port.x_char, uap->port.membase + UART01x_DR); 673 819 uap->port.icount.tx++; 674 820 uap->port.x_char = 0; 675 821 676 822 /* Success - restore the DMA state */ 677 823 uap->dmacr = dmacr; 678 - pl011_writew(uap, dmacr, REG_DMACR); 824 + writew(dmacr, uap->port.membase + UART011_DMACR); 679 825 680 826 return true; 681 827 } ··· 703 849 DMA_TO_DEVICE); 704 850 uap->dmatx.queued = false; 705 851 uap->dmacr &= ~UART011_TXDMAE; 706 - pl011_writew(uap, uap->dmacr, REG_DMACR); 852 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 707 853 } 708 854 } 709 855 ··· 743 889 dma_async_issue_pending(rxchan); 744 890 745 891 uap->dmacr |= UART011_RXDMAE; 746 - pl011_writew(uap, uap->dmacr, REG_DMACR); 892 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 747 893 uap->dmarx.running = true; 748 894 749 895 uap->im &= ~UART011_RXIM; 750 - pl011_writew(uap, uap->im, REG_IMSC); 896 + writew(uap->im, uap->port.membase + UART011_IMSC); 751 897 752 898 return 0; 753 899 } ··· 805 951 */ 806 952 if (dma_count == pending && readfifo) { 807 953 /* Clear any error flags */ 808 - pl011_writew(uap, 809 - UART011_OEIS | UART011_BEIS | UART011_PEIS 810 - | UART011_FEIS, REG_ICR); 954 + writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, 955 + uap->port.membase + UART011_ICR); 811 956 812 957 /* 813 958 * If we read all the DMA'd characters, and we had an ··· 854 1001 855 1002 /* Disable RX DMA - incoming data will wait in the FIFO */ 856 1003 uap->dmacr &= ~UART011_RXDMAE; 857 - pl011_writew(uap, uap->dmacr, REG_DMACR); 1004 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 858 1005 uap->dmarx.running = false; 859 1006 860 1007 pending = sgbuf->sg.length - state.residue; ··· 874 1021 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 875 1022 "fall back to interrupt mode\n"); 876 1023 uap->im |= UART011_RXIM; 877 - pl011_writew(uap, uap->im, REG_IMSC); 1024 + writew(uap->im, uap->port.membase + UART011_IMSC); 878 1025 } 879 1026 } 880 1027 ··· 922 1069 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 923 1070 "fall back to interrupt mode\n"); 924 1071 uap->im |= UART011_RXIM; 925 - pl011_writew(uap, uap->im, REG_IMSC); 1072 + writew(uap->im, uap->port.membase + UART011_IMSC); 926 1073 } 927 1074 } 928 1075 ··· 935 1082 { 936 1083 /* FIXME. Just disable the DMA enable */ 937 1084 uap->dmacr &= ~UART011_RXDMAE; 938 - pl011_writew(uap, uap->dmacr, REG_DMACR); 1085 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 939 1086 } 940 1087 941 1088 /* ··· 979 1126 spin_lock_irqsave(&uap->port.lock, flags); 980 1127 pl011_dma_rx_stop(uap); 981 1128 uap->im |= UART011_RXIM; 982 - pl011_writew(uap, uap->im, REG_IMSC); 1129 + writew(uap->im, uap->port.membase + UART011_IMSC); 983 1130 spin_unlock_irqrestore(&uap->port.lock, flags); 984 1131 985 1132 uap->dmarx.running = false; ··· 1041 1188 skip_rx: 1042 1189 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1043 1190 uap->dmacr |= UART011_DMAONERR; 1044 - pl011_writew(uap, uap->dmacr, REG_DMACR); 1191 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 1045 1192 1046 1193 /* 1047 1194 * ST Micro variants has some specific dma burst threshold ··· 1049 1196 * be issued above/below 16 bytes. 1050 1197 */ 1051 1198 if (uap->vendor->dma_threshold) 1052 - pl011_writew(uap, 1053 - ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1054 - REG_ST_DMAWM); 1199 + writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1200 + uap->port.membase + ST_UART011_DMAWM); 1055 1201 1056 1202 if (uap->using_rx_dma) { 1057 1203 if (pl011_dma_rx_trigger_dma(uap)) ··· 1075 1223 return; 1076 1224 1077 1225 /* Disable RX and TX DMA */ 1078 - while (pl011_readw(uap, REG_FR) & uap->fr_busy) 1226 + while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) 1079 1227 barrier(); 1080 1228 1081 1229 spin_lock_irq(&uap->port.lock); 1082 1230 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1083 - pl011_writew(uap, uap->dmacr, REG_DMACR); 1231 + writew(uap->dmacr, uap->port.membase + UART011_DMACR); 1084 1232 spin_unlock_irq(&uap->port.lock); 1085 1233 1086 1234 if (uap->using_tx_dma) { ··· 1181 1329 container_of(port, struct uart_amba_port, port); 1182 1330 1183 1331 uap->im &= ~UART011_TXIM; 1184 - pl011_writew(uap, uap->im, REG_IMSC); 1332 + writew(uap->im, uap->port.membase + UART011_IMSC); 1185 1333 pl011_dma_tx_stop(uap); 1186 1334 } 1187 1335 ··· 1191 1339 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1192 1340 { 1193 1341 uap->im |= UART011_TXIM; 1194 - pl011_writew(uap, uap->im, REG_IMSC); 1342 + writew(uap->im, uap->port.membase + UART011_IMSC); 1195 1343 pl011_tx_chars(uap, false); 1196 1344 } 1197 1345 ··· 1211 1359 1212 1360 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1213 1361 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1214 - pl011_writew(uap, uap->im, REG_IMSC); 1362 + writew(uap->im, uap->port.membase + UART011_IMSC); 1215 1363 1216 1364 pl011_dma_rx_stop(uap); 1217 1365 } ··· 1222 1370 container_of(port, struct uart_amba_port, port); 1223 1371 1224 1372 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1225 - pl011_writew(uap, uap->im, REG_IMSC); 1373 + writew(uap->im, uap->port.membase + UART011_IMSC); 1226 1374 } 1227 1375 1228 1376 static void pl011_rx_chars(struct uart_amba_port *uap) ··· 1242 1390 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1243 1391 "fall back to interrupt mode again\n"); 1244 1392 uap->im |= UART011_RXIM; 1245 - pl011_writew(uap, uap->im, REG_IMSC); 1393 + writew(uap->im, uap->port.membase + UART011_IMSC); 1246 1394 } else { 1247 1395 #ifdef CONFIG_DMA_ENGINE 1248 1396 /* Start Rx DMA poll */ ··· 1263 1411 bool from_irq) 1264 1412 { 1265 1413 if (unlikely(!from_irq) && 1266 - pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 1414 + readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) 1267 1415 return false; /* unable to transmit character */ 1268 1416 1269 - pl011_writew(uap, c, REG_DR); 1417 + writew(c, uap->port.membase + UART01x_DR); 1270 1418 uap->port.icount.tx++; 1271 1419 1272 1420 return true; ··· 1313 1461 { 1314 1462 unsigned int status, delta; 1315 1463 1316 - status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1464 + status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 1317 1465 1318 1466 delta = status ^ uap->old_status; 1319 1467 uap->old_status = status; ··· 1324 1472 if (delta & UART01x_FR_DCD) 1325 1473 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1326 1474 1327 - if (delta & uap->fr_dsr) 1475 + if (delta & UART01x_FR_DSR) 1328 1476 uap->port.icount.dsr++; 1329 1477 1330 - if (delta & uap->fr_cts) 1331 - uart_handle_cts_change(&uap->port, status & uap->fr_cts); 1478 + if (delta & UART01x_FR_CTS) 1479 + uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 1332 1480 1333 1481 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1334 1482 } ··· 1341 1489 return; 1342 1490 1343 1491 /* workaround to make sure that all bits are unlocked.. */ 1344 - pl011_writew(uap, 0x00, REG_ICR); 1492 + writew(0x00, uap->port.membase + UART011_ICR); 1345 1493 1346 1494 /* 1347 1495 * WA: introduce 26ns(1 uart clk) delay before W1C; 1348 1496 * single apb access will incur 2 pclk(133.12Mhz) delay, 1349 1497 * so add 2 dummy reads 1350 1498 */ 1351 - dummy_read = pl011_readw(uap, REG_ICR); 1352 - dummy_read = pl011_readw(uap, REG_ICR); 1499 + dummy_read = readw(uap->port.membase + UART011_ICR); 1500 + dummy_read = readw(uap->port.membase + UART011_ICR); 1353 1501 } 1354 1502 1355 1503 static irqreturn_t pl011_int(int irq, void *dev_id) ··· 1361 1509 int handled = 0; 1362 1510 1363 1511 spin_lock_irqsave(&uap->port.lock, flags); 1364 - imsc = pl011_readw(uap, REG_IMSC); 1365 - status = pl011_readw(uap, REG_RIS) & imsc; 1512 + imsc = readw(uap->port.membase + UART011_IMSC); 1513 + status = readw(uap->port.membase + UART011_RIS) & imsc; 1366 1514 if (status) { 1367 1515 do { 1368 1516 check_apply_cts_event_workaround(uap); 1369 - pl011_writew(uap, status & ~(UART011_TXIS|UART011_RTIS| 1370 - UART011_RXIS), REG_ICR); 1517 + 1518 + writew(status & ~(UART011_TXIS|UART011_RTIS| 1519 + UART011_RXIS), 1520 + uap->port.membase + UART011_ICR); 1371 1521 1372 1522 if (status & (UART011_RTIS|UART011_RXIS)) { 1373 1523 if (pl011_dma_rx_running(uap)) ··· 1386 1532 if (pass_counter-- == 0) 1387 1533 break; 1388 1534 1389 - status = pl011_readw(uap, REG_RIS) & imsc; 1535 + status = readw(uap->port.membase + UART011_RIS) & imsc; 1390 1536 } while (status != 0); 1391 1537 handled = 1; 1392 1538 } ··· 1400 1546 { 1401 1547 struct uart_amba_port *uap = 1402 1548 container_of(port, struct uart_amba_port, port); 1403 - unsigned int status = pl011_readw(uap, REG_FR); 1404 - return status & (uap->fr_busy|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; 1549 + unsigned int status = readw(uap->port.membase + UART01x_FR); 1550 + return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; 1405 1551 } 1406 1552 1407 1553 static unsigned int pl011_get_mctrl(struct uart_port *port) ··· 1409 1555 struct uart_amba_port *uap = 1410 1556 container_of(port, struct uart_amba_port, port); 1411 1557 unsigned int result = 0; 1412 - unsigned int status = pl011_readw(uap, REG_FR); 1558 + unsigned int status = readw(uap->port.membase + UART01x_FR); 1413 1559 1414 1560 #define TIOCMBIT(uartbit, tiocmbit) \ 1415 1561 if (status & uartbit) \ 1416 1562 result |= tiocmbit 1417 1563 1418 1564 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1419 - TIOCMBIT(uap->fr_dsr, TIOCM_DSR); 1420 - TIOCMBIT(uap->fr_cts, TIOCM_CTS); 1421 - TIOCMBIT(uap->fr_ri, TIOCM_RNG); 1565 + TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); 1566 + TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); 1567 + TIOCMBIT(UART011_FR_RI, TIOCM_RNG); 1422 1568 #undef TIOCMBIT 1423 1569 return result; 1424 1570 } ··· 1429 1575 container_of(port, struct uart_amba_port, port); 1430 1576 unsigned int cr; 1431 1577 1432 - cr = pl011_readw(uap, REG_CR); 1578 + cr = readw(uap->port.membase + UART011_CR); 1433 1579 1434 1580 #define TIOCMBIT(tiocmbit, uartbit) \ 1435 1581 if (mctrl & tiocmbit) \ ··· 1449 1595 } 1450 1596 #undef TIOCMBIT 1451 1597 1452 - pl011_writew(uap, cr, REG_CR); 1598 + writew(cr, uap->port.membase + UART011_CR); 1453 1599 } 1454 1600 1455 1601 static void pl011_break_ctl(struct uart_port *port, int break_state) ··· 1460 1606 unsigned int lcr_h; 1461 1607 1462 1608 spin_lock_irqsave(&uap->port.lock, flags); 1463 - lcr_h = pl011_readw(uap, uap->lcrh_tx); 1609 + lcr_h = readw(uap->port.membase + uap->lcrh_tx); 1464 1610 if (break_state == -1) 1465 1611 lcr_h |= UART01x_LCRH_BRK; 1466 1612 else 1467 1613 lcr_h &= ~UART01x_LCRH_BRK; 1468 - pl011_writew(uap, lcr_h, uap->lcrh_tx); 1614 + writew(lcr_h, uap->port.membase + uap->lcrh_tx); 1469 1615 spin_unlock_irqrestore(&uap->port.lock, flags); 1470 1616 } 1471 1617 ··· 1475 1621 { 1476 1622 struct uart_amba_port *uap = 1477 1623 container_of(port, struct uart_amba_port, port); 1624 + unsigned char __iomem *regs = uap->port.membase; 1478 1625 1479 - pl011_writew(uap, pl011_readw(uap, REG_MIS), REG_ICR); 1626 + writew(readw(regs + UART011_MIS), regs + UART011_ICR); 1480 1627 /* 1481 1628 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1482 1629 * we simply mask it. start_tx() will unmask it. ··· 1491 1636 * (including tx queue), so we're also fine with start_tx()'s caller 1492 1637 * side. 1493 1638 */ 1494 - pl011_writew(uap, pl011_readw(uap, REG_IMSC) & ~UART011_TXIM, REG_IMSC); 1639 + writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC); 1495 1640 } 1496 1641 1497 1642 static int pl011_get_poll_char(struct uart_port *port) ··· 1506 1651 */ 1507 1652 pl011_quiesce_irqs(port); 1508 1653 1509 - status = pl011_readw(uap, REG_FR); 1654 + status = readw(uap->port.membase + UART01x_FR); 1510 1655 if (status & UART01x_FR_RXFE) 1511 1656 return NO_POLL_CHAR; 1512 1657 1513 - return pl011_readw(uap, REG_DR); 1658 + return readw(uap->port.membase + UART01x_DR); 1514 1659 } 1515 1660 1516 1661 static void pl011_put_poll_char(struct uart_port *port, ··· 1519 1664 struct uart_amba_port *uap = 1520 1665 container_of(port, struct uart_amba_port, port); 1521 1666 1522 - while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 1667 + while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) 1523 1668 barrier(); 1524 1669 1525 - pl011_writew(uap, ch, REG_DR); 1670 + writew(ch, uap->port.membase + UART01x_DR); 1526 1671 } 1527 1672 1528 1673 #endif /* CONFIG_CONSOLE_POLL */ ··· 1546 1691 uap->port.uartclk = clk_get_rate(uap->clk); 1547 1692 1548 1693 /* Clear pending error and receive interrupts */ 1549 - pl011_writew(uap, UART011_OEIS | UART011_BEIS | UART011_PEIS | 1550 - UART011_FEIS | UART011_RTIS | UART011_RXIS, REG_ICR); 1694 + writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | 1695 + UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); 1551 1696 1552 1697 /* 1553 1698 * Save interrupts enable mask, and enable RX interrupts in case if 1554 1699 * the interrupt is used for NMI entry. 1555 1700 */ 1556 - uap->im = pl011_readw(uap, REG_IMSC); 1557 - pl011_writew(uap, UART011_RTIM | UART011_RXIM, REG_IMSC); 1701 + uap->im = readw(uap->port.membase + UART011_IMSC); 1702 + writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); 1558 1703 1559 1704 if (dev_get_platdata(uap->port.dev)) { 1560 1705 struct amba_pl011_data *plat; ··· 1568 1713 1569 1714 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1570 1715 { 1571 - pl011_writew(uap, lcr_h, uap->lcrh_rx); 1572 - if (is_implemented(uap, REG_ST_LCRH_RX)) { 1716 + writew(lcr_h, uap->port.membase + uap->lcrh_rx); 1717 + if (uap->lcrh_rx != uap->lcrh_tx) { 1573 1718 int i; 1574 1719 /* 1575 1720 * Wait 10 PCLKs before writing LCRH_TX register, 1576 1721 * to get this delay write read only register 10 times 1577 1722 */ 1578 1723 for (i = 0; i < 10; ++i) 1579 - pl011_writew(uap, 0xff, REG_MIS); 1580 - pl011_writew(uap, lcr_h, uap->lcrh_tx); 1724 + writew(0xff, uap->port.membase + UART011_MIS); 1725 + writew(lcr_h, uap->port.membase + uap->lcrh_tx); 1581 1726 } 1582 1727 } 1583 1728 1584 1729 static int pl011_allocate_irq(struct uart_amba_port *uap) 1585 1730 { 1586 - pl011_writew(uap, uap->im, REG_IMSC); 1731 + writew(uap->im, uap->port.membase + UART011_IMSC); 1587 1732 1588 1733 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); 1589 1734 } ··· 1598 1743 spin_lock_irq(&uap->port.lock); 1599 1744 1600 1745 /* Clear out any spuriously appearing RX interrupts */ 1601 - pl011_writew(uap, UART011_RTIS | UART011_RXIS, REG_ICR); 1746 + writew(UART011_RTIS | UART011_RXIS, 1747 + uap->port.membase + UART011_ICR); 1602 1748 uap->im = UART011_RTIM; 1603 1749 if (!pl011_dma_rx_running(uap)) 1604 1750 uap->im |= UART011_RXIM; 1605 - pl011_writew(uap, uap->im, REG_IMSC); 1751 + writew(uap->im, uap->port.membase + UART011_IMSC); 1606 1752 spin_unlock_irq(&uap->port.lock); 1607 1753 } 1608 1754 ··· 1622 1766 if (retval) 1623 1767 goto clk_dis; 1624 1768 1625 - pl011_writew(uap, uap->vendor->ifls, REG_IFLS); 1769 + writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); 1626 1770 1627 1771 spin_lock_irq(&uap->port.lock); 1628 1772 1629 1773 /* restore RTS and DTR */ 1630 1774 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); 1631 1775 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 1632 - pl011_writew(uap, cr, REG_CR); 1776 + writew(cr, uap->port.membase + UART011_CR); 1633 1777 1634 1778 spin_unlock_irq(&uap->port.lock); 1635 1779 1636 1780 /* 1637 1781 * initialise the old status of the modem signals 1638 1782 */ 1639 - uap->old_status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1783 + uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 1640 1784 1641 1785 /* Startup DMA */ 1642 1786 pl011_dma_startup(uap); ··· 1675 1819 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1676 1820 unsigned int lcrh) 1677 1821 { 1678 - unsigned long val; 1822 + unsigned long val; 1679 1823 1680 - val = pl011_readw(uap, lcrh); 1681 - val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1682 - pl011_writew(uap, val, lcrh); 1824 + val = readw(uap->port.membase + lcrh); 1825 + val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1826 + writew(val, uap->port.membase + lcrh); 1683 1827 } 1684 1828 1685 1829 /* ··· 1693 1837 1694 1838 uap->autorts = false; 1695 1839 spin_lock_irq(&uap->port.lock); 1696 - cr = pl011_readw(uap, REG_CR); 1840 + cr = readw(uap->port.membase + UART011_CR); 1697 1841 uap->old_cr = cr; 1698 1842 cr &= UART011_CR_RTS | UART011_CR_DTR; 1699 1843 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1700 - pl011_writew(uap, cr, REG_CR); 1844 + writew(cr, uap->port.membase + UART011_CR); 1701 1845 spin_unlock_irq(&uap->port.lock); 1702 1846 1703 1847 /* 1704 1848 * disable break condition and fifos 1705 1849 */ 1706 1850 pl011_shutdown_channel(uap, uap->lcrh_rx); 1707 - if (is_implemented(uap, REG_ST_LCRH_RX)) 1851 + if (uap->lcrh_rx != uap->lcrh_tx) 1708 1852 pl011_shutdown_channel(uap, uap->lcrh_tx); 1709 1853 } 1710 1854 ··· 1714 1858 1715 1859 /* mask all interrupts and clear all pending ones */ 1716 1860 uap->im = 0; 1717 - pl011_writew(uap, uap->im, REG_IMSC); 1718 - pl011_writew(uap, 0xffff, REG_ICR); 1861 + writew(uap->im, uap->port.membase + UART011_IMSC); 1862 + writew(0xffff, uap->port.membase + UART011_ICR); 1719 1863 1720 1864 spin_unlock_irq(&uap->port.lock); 1721 1865 } ··· 1867 2011 pl011_enable_ms(port); 1868 2012 1869 2013 /* first, disable everything */ 1870 - old_cr = pl011_readw(uap, REG_CR); 1871 - pl011_writew(uap, 0, REG_CR); 2014 + old_cr = readw(port->membase + UART011_CR); 2015 + writew(0, port->membase + UART011_CR); 1872 2016 1873 2017 if (termios->c_cflag & CRTSCTS) { 1874 2018 if (old_cr & UART011_CR_RTS) ··· 1901 2045 quot -= 2; 1902 2046 } 1903 2047 /* Set baud rate */ 1904 - pl011_writew(uap, quot & 0x3f, REG_FBRD); 1905 - pl011_writew(uap, quot >> 6, REG_IBRD); 2048 + writew(quot & 0x3f, port->membase + UART011_FBRD); 2049 + writew(quot >> 6, port->membase + UART011_IBRD); 1906 2050 1907 2051 /* 1908 2052 * ----------v----------v----------v----------v----- 1909 2053 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER 1910 - * REG_FBRD & REG_IBRD. 2054 + * UART011_FBRD & UART011_IBRD. 1911 2055 * ----------^----------^----------^----------^----- 1912 2056 */ 1913 2057 pl011_write_lcr_h(uap, lcr_h); 1914 - pl011_writew(uap, old_cr, REG_CR); 2058 + writew(old_cr, port->membase + UART011_CR); 1915 2059 1916 2060 spin_unlock_irqrestore(&port->lock, flags); 1917 2061 } ··· 2052 2196 struct uart_amba_port *uap = 2053 2197 container_of(port, struct uart_amba_port, port); 2054 2198 2055 - while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 2199 + while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) 2056 2200 barrier(); 2057 - pl011_writew(uap, ch, REG_DR); 2201 + writew(ch, uap->port.membase + UART01x_DR); 2058 2202 } 2059 2203 2060 2204 static void ··· 2079 2223 * First save the CR then disable the interrupts 2080 2224 */ 2081 2225 if (!uap->vendor->always_enabled) { 2082 - old_cr = pl011_readw(uap, REG_CR); 2226 + old_cr = readw(uap->port.membase + UART011_CR); 2083 2227 new_cr = old_cr & ~UART011_CR_CTSEN; 2084 2228 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2085 - pl011_writew(uap, new_cr, REG_CR); 2229 + writew(new_cr, uap->port.membase + UART011_CR); 2086 2230 } 2087 2231 2088 2232 uart_console_write(&uap->port, s, count, pl011_console_putchar); ··· 2092 2236 * and restore the TCR 2093 2237 */ 2094 2238 do { 2095 - status = pl011_readw(uap, REG_FR); 2096 - } while (status & uap->fr_busy); 2239 + status = readw(uap->port.membase + UART01x_FR); 2240 + } while (status & UART01x_FR_BUSY); 2097 2241 if (!uap->vendor->always_enabled) 2098 - pl011_writew(uap, old_cr, REG_CR); 2242 + writew(old_cr, uap->port.membase + UART011_CR); 2099 2243 2100 2244 if (locked) 2101 2245 spin_unlock(&uap->port.lock); ··· 2108 2252 pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2109 2253 int *parity, int *bits) 2110 2254 { 2111 - if (pl011_readw(uap, REG_CR) & UART01x_CR_UARTEN) { 2255 + if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { 2112 2256 unsigned int lcr_h, ibrd, fbrd; 2113 2257 2114 - lcr_h = pl011_readw(uap, uap->lcrh_tx); 2258 + lcr_h = readw(uap->port.membase + uap->lcrh_tx); 2115 2259 2116 2260 *parity = 'n'; 2117 2261 if (lcr_h & UART01x_LCRH_PEN) { ··· 2126 2270 else 2127 2271 *bits = 8; 2128 2272 2129 - ibrd = pl011_readw(uap, REG_IBRD); 2130 - fbrd = pl011_readw(uap, REG_FBRD); 2273 + ibrd = readw(uap->port.membase + UART011_IBRD); 2274 + fbrd = readw(uap->port.membase + UART011_FBRD); 2131 2275 2132 2276 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2133 2277 2134 2278 if (uap->vendor->oversampling) { 2135 - if (pl011_readw(uap, REG_CR) 2279 + if (readw(uap->port.membase + UART011_CR) 2136 2280 & ST_UART011_CR_OVSFACT) 2137 2281 *baud *= 2; 2138 2282 } ··· 2204 2348 2205 2349 static void pl011_putc(struct uart_port *port, int c) 2206 2350 { 2207 - struct uart_amba_port *uap = 2208 - container_of(port, struct uart_amba_port, port); 2209 - 2210 - while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 2351 + while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2211 2352 ; 2212 - pl011_writeb(uap, c, REG_DR); 2213 - while (pl011_readw(uap, REG_FR) & uap->fr_busy) 2353 + writeb(c, port->membase + UART01x_DR); 2354 + while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2214 2355 ; 2215 2356 } 2216 2357 ··· 2334 2481 int ret; 2335 2482 2336 2483 /* Ensure interrupts from this UART are masked and cleared */ 2337 - pl011_writew(uap, 0, REG_IMSC); 2338 - pl011_writew(uap, 0xffff, REG_ICR); 2484 + writew(0, uap->port.membase + UART011_IMSC); 2485 + writew(0xffff, uap->port.membase + UART011_ICR); 2339 2486 2340 2487 if (!amba_reg.state) { 2341 2488 ret = uart_register_driver(&amba_reg); ··· 2353 2500 return ret; 2354 2501 } 2355 2502 2356 - #ifdef CONFIG_ARM_AMBA 2357 2503 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2358 2504 { 2359 2505 struct uart_amba_port *uap; ··· 2373 2521 return PTR_ERR(uap->clk); 2374 2522 2375 2523 uap->vendor = vendor; 2376 - uap->reg_lut = vendor->reg_lut; 2377 2524 uap->lcrh_rx = vendor->lcrh_rx; 2378 2525 uap->lcrh_tx = vendor->lcrh_tx; 2379 - uap->fr_busy = vendor->fr_busy; 2380 - uap->fr_dsr = vendor->fr_dsr; 2381 - uap->fr_cts = vendor->fr_cts; 2382 - uap->fr_ri = vendor->fr_ri; 2383 2526 uap->fifosize = vendor->get_fifosize(dev); 2384 2527 uap->port.irq = dev->irq[0]; 2385 2528 uap->port.ops = &amba_pl011_pops; ··· 2398 2551 pl011_unregister_port(uap); 2399 2552 return 0; 2400 2553 } 2401 - #endif 2402 - 2403 - #ifdef CONFIG_SOC_ZX296702 2404 - static int zx_uart_probe(struct platform_device *pdev) 2405 - { 2406 - struct uart_amba_port *uap; 2407 - struct vendor_data *vendor = &vendor_zte; 2408 - struct resource *res; 2409 - int portnr, ret; 2410 - 2411 - portnr = pl011_find_free_port(); 2412 - if (portnr < 0) 2413 - return portnr; 2414 - 2415 - uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2416 - GFP_KERNEL); 2417 - if (!uap) { 2418 - ret = -ENOMEM; 2419 - goto out; 2420 - } 2421 - 2422 - uap->clk = devm_clk_get(&pdev->dev, NULL); 2423 - if (IS_ERR(uap->clk)) { 2424 - ret = PTR_ERR(uap->clk); 2425 - goto out; 2426 - } 2427 - 2428 - uap->vendor = vendor; 2429 - uap->reg_lut = vendor->reg_lut; 2430 - uap->lcrh_rx = vendor->lcrh_rx; 2431 - uap->lcrh_tx = vendor->lcrh_tx; 2432 - uap->fr_busy = vendor->fr_busy; 2433 - uap->fr_dsr = vendor->fr_dsr; 2434 - uap->fr_cts = vendor->fr_cts; 2435 - uap->fr_ri = vendor->fr_ri; 2436 - uap->fifosize = 16; 2437 - uap->port.irq = platform_get_irq(pdev, 0); 2438 - uap->port.ops = &amba_pl011_pops; 2439 - 2440 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2441 - 2442 - ret = pl011_setup_port(&pdev->dev, uap, res, portnr); 2443 - if (ret) 2444 - return ret; 2445 - 2446 - platform_set_drvdata(pdev, uap); 2447 - 2448 - return pl011_register_port(uap); 2449 - out: 2450 - return ret; 2451 - } 2452 - 2453 - static int zx_uart_remove(struct platform_device *pdev) 2454 - { 2455 - struct uart_amba_port *uap = platform_get_drvdata(pdev); 2456 - 2457 - uart_remove_one_port(&amba_reg, &uap->port); 2458 - pl011_unregister_port(uap); 2459 - return 0; 2460 - } 2461 - #endif 2462 2554 2463 2555 #ifdef CONFIG_PM_SLEEP 2464 2556 static int pl011_suspend(struct device *dev) ··· 2454 2668 return -ENOMEM; 2455 2669 2456 2670 uap->vendor = &vendor_sbsa; 2457 - uap->reg_lut = vendor_sbsa.reg_lut; 2458 - uap->fr_busy = vendor_sbsa.fr_busy; 2459 - uap->fr_dsr = vendor_sbsa.fr_dsr; 2460 - uap->fr_cts = vendor_sbsa.fr_cts; 2461 - uap->fr_ri = vendor_sbsa.fr_ri; 2462 2671 uap->fifosize = 32; 2463 2672 uap->port.irq = platform_get_irq(pdev, 0); 2464 2673 uap->port.ops = &sbsa_uart_pops; ··· 2503 2722 }, 2504 2723 }; 2505 2724 2506 - #ifdef CONFIG_ARM_AMBA 2507 2725 static struct amba_id pl011_ids[] = { 2508 2726 { 2509 2727 .id = 0x00041011, ··· 2528 2748 .probe = pl011_probe, 2529 2749 .remove = pl011_remove, 2530 2750 }; 2531 - #endif 2532 - 2533 - #ifdef CONFIG_SOC_ZX296702 2534 - static const struct of_device_id zx_uart_dt_ids[] = { 2535 - { .compatible = "zte,zx296702-uart", }, 2536 - { /* sentinel */ } 2537 - }; 2538 - MODULE_DEVICE_TABLE(of, zx_uart_dt_ids); 2539 - 2540 - static struct platform_driver zx_uart_driver = { 2541 - .driver = { 2542 - .name = "zx-uart", 2543 - .owner = THIS_MODULE, 2544 - .pm = &pl011_dev_pm_ops, 2545 - .of_match_table = zx_uart_dt_ids, 2546 - }, 2547 - .probe = zx_uart_probe, 2548 - .remove = zx_uart_remove, 2549 - }; 2550 - #endif 2551 - 2552 2751 2553 2752 static int __init pl011_init(void) 2554 2753 { 2555 - int ret; 2556 2754 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2557 2755 2558 2756 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2559 2757 pr_warn("could not register SBSA UART platform driver\n"); 2560 - 2561 - #ifdef CONFIG_SOC_ZX296702 2562 - ret = platform_driver_register(&zx_uart_driver); 2563 - if (ret) 2564 - pr_warn("could not register ZX UART platform driver\n"); 2565 - #endif 2566 - 2567 - #ifdef CONFIG_ARM_AMBA 2568 - ret = amba_driver_register(&pl011_driver); 2569 - #endif 2570 - return ret; 2758 + return amba_driver_register(&pl011_driver); 2571 2759 } 2572 2760 2573 2761 static void __exit pl011_exit(void) 2574 2762 { 2575 2763 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2576 - #ifdef CONFIG_SOC_ZX296702 2577 - platform_driver_unregister(&zx_uart_driver); 2578 - #endif 2579 - #ifdef CONFIG_ARM_AMBA 2580 2764 amba_driver_unregister(&pl011_driver); 2581 - #endif 2582 2765 } 2583 2766 2584 2767 /*

-14

include/linux/amba/serial.h

··· 33 33 #define UART01x_DR 0x00 /* Data read or written from the interface. */ 34 34 #define UART01x_RSR 0x04 /* Receive status register (Read). */ 35 35 #define UART01x_ECR 0x04 /* Error clear register (Write). */ 36 - #define ZX_UART01x_DR 0x04 /* Data read or written from the interface. */ 37 36 #define UART010_LCRH 0x08 /* Line control register, high byte. */ 38 37 #define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */ 39 38 #define UART010_LCRM 0x0C /* Line control register, middle byte. */ 40 39 #define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */ 41 40 #define UART010_LCRL 0x10 /* Line control register, low byte. */ 42 41 #define UART010_CR 0x14 /* Control register. */ 43 - #define ZX_UART01x_FR 0x14 /* Flag register (Read only). */ 44 42 #define UART01x_FR 0x18 /* Flag register (Read only). */ 45 43 #define UART010_IIR 0x1C /* Interrupt identification register (Read). */ 46 44 #define UART010_ICR 0x1C /* Interrupt clear register (Write). */ ··· 49 51 #define UART011_LCRH 0x2c /* Line control register. */ 50 52 #define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */ 51 53 #define UART011_CR 0x30 /* Control register. */ 52 - #define ZX_UART011_LCRH_TX 0x30 /* Tx Line control register. */ 53 54 #define UART011_IFLS 0x34 /* Interrupt fifo level select. */ 54 - #define ZX_UART011_CR 0x34 /* Control register. */ 55 - #define ZX_UART011_IFLS 0x38 /* Interrupt fifo level select. */ 56 55 #define UART011_IMSC 0x38 /* Interrupt mask. */ 57 56 #define UART011_RIS 0x3c /* Raw interrupt status. */ 58 57 #define UART011_MIS 0x40 /* Masked interrupt status. */ 59 - #define ZX_UART011_IMSC 0x40 /* Interrupt mask. */ 60 58 #define UART011_ICR 0x44 /* Interrupt clear register. */ 61 - #define ZX_UART011_RIS 0x44 /* Raw interrupt status. */ 62 59 #define UART011_DMACR 0x48 /* DMA control register. */ 63 - #define ZX_UART011_MIS 0x48 /* Masked interrupt status. */ 64 - #define ZX_UART011_ICR 0x4c /* Interrupt clear register. */ 65 60 #define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */ 66 - #define ZX_UART011_DMACR 0x50 /* DMA control register. */ 67 61 #define ST_UART011_XON1 0x54 /* XON1 register. */ 68 62 #define ST_UART011_XON2 0x58 /* XON2 register. */ 69 63 #define ST_UART011_XOFF1 0x5C /* XON1 register. */ ··· 75 85 #define UART01x_RSR_PE 0x02 76 86 #define UART01x_RSR_FE 0x01 77 87 78 - #define ZX_UART01x_FR_BUSY 0x300 79 88 #define UART011_FR_RI 0x100 80 89 #define UART011_FR_TXFE 0x080 81 90 #define UART011_FR_RXFF 0x040 82 91 #define UART01x_FR_TXFF 0x020 83 92 #define UART01x_FR_RXFE 0x010 84 93 #define UART01x_FR_BUSY 0x008 85 - #define ZX_UART01x_FR_DSR 0x008 86 94 #define UART01x_FR_DCD 0x004 87 95 #define UART01x_FR_DSR 0x002 88 - #define ZX_UART01x_FR_CTS 0x002 89 96 #define UART01x_FR_CTS 0x001 90 - #define ZX_UART011_FR_RI 0x001 91 97 #define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY) 92 98 93 99 #define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */