+11
-5
drivers/edac/synopsys_edac.c
+11
-5
drivers/edac/synopsys_edac.c
···
164
164
#define ECC_STAT_CECNT_SHIFT 8
165
165
#define ECC_STAT_BITNUM_MASK 0x7F
166
166
167
+
/* ECC error count register definitions */
168
+
#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000
169
+
#define ECC_ERRCNT_UECNT_SHIFT 16
170
+
#define ECC_ERRCNT_CECNT_MASK 0xFFFF
171
+
167
172
/* DDR QOS Interrupt register definitions */
168
173
#define DDR_QOS_IRQ_STAT_OFST 0x20200
169
174
#define DDR_QOSUE_MASK 0x4
···
428
423
base = priv->baseaddr;
429
424
p = &priv->stat;
430
425
426
+
regval = readl(base + ECC_ERRCNT_OFST);
427
+
p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;
428
+
p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;
429
+
if (!p->ce_cnt)
430
+
goto ue_err;
431
+
431
432
regval = readl(base + ECC_STAT_OFST);
432
433
if (!regval)
433
434
return 1;
434
-
435
-
p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT;
436
-
p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT;
437
-
if (!p->ce_cnt)
438
-
goto ue_err;
439
435
440
436
p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
441
437