tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

cpuidle: Invert CPUIDLE_FLAG_TIME_VALID logic

The only place where the time is invalid is when the ACPI_CSTATE_FFH entry
method is not set. Otherwise for all the drivers, the time can be correctly
measured.

Instead of duplicating the CPUIDLE_FLAG_TIME_VALID flag in all the drivers
for all the states, just invert the logic by replacing it by the flag
CPUIDLE_FLAG_TIME_INVALID, hence we can set this flag only for the acpi idle
driver, remove the former flag from all the drivers and invert the logic with
this flag in the different governor.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

authored by

Daniel Lezcano and committed by
Rafael J. Wysocki b82b6cca 206c5f60

+75 -125
-1
arch/arm/include/asm/cpuidle.h
··· 15 15 .exit_latency = 1,\ 16 16 .target_residency = 1,\ 17 17 .power_usage = p,\ 18 - .flags = CPUIDLE_FLAG_TIME_VALID,\ 19 18 .name = "WFI",\ 20 19 .desc = "ARM WFI",\ 21 20 }
-1
arch/arm/mach-davinci/cpuidle.c
··· 66 66 .enter = davinci_enter_idle, 67 67 .exit_latency = 10, 68 68 .target_residency = 10000, 69 - .flags = CPUIDLE_FLAG_TIME_VALID, 70 69 .name = "DDR SR", 71 70 .desc = "WFI and DDR Self Refresh", 72 71 },
-1
arch/arm/mach-imx/cpuidle-imx5.c
··· 24 24 .enter = imx5_cpuidle_enter, 25 25 .exit_latency = 2, 26 26 .target_residency = 1, 27 - .flags = CPUIDLE_FLAG_TIME_VALID, 28 27 .name = "IMX5 SRPG", 29 28 .desc = "CPU state retained,powered off", 30 29 },
+1 -2
arch/arm/mach-imx/cpuidle-imx6q.c
··· 53 53 { 54 54 .exit_latency = 50, 55 55 .target_residency = 75, 56 - .flags = CPUIDLE_FLAG_TIME_VALID | 57 - CPUIDLE_FLAG_TIMER_STOP, 56 + .flags = CPUIDLE_FLAG_TIMER_STOP, 58 57 .enter = imx6q_enter_wait, 59 58 .name = "WAIT", 60 59 .desc = "Clock off",
+1 -2
arch/arm/mach-imx/cpuidle-imx6sl.c
··· 40 40 { 41 41 .exit_latency = 50, 42 42 .target_residency = 75, 43 - .flags = CPUIDLE_FLAG_TIME_VALID | 44 - CPUIDLE_FLAG_TIMER_STOP, 43 + .flags = CPUIDLE_FLAG_TIMER_STOP, 45 44 .enter = imx6sl_enter_wait, 46 45 .name = "WAIT", 47 46 .desc = "Clock off",
-7
arch/arm/mach-omap2/cpuidle34xx.c
··· 265 265 .enter = omap3_enter_idle_bm, 266 266 .exit_latency = 2 + 2, 267 267 .target_residency = 5, 268 - .flags = CPUIDLE_FLAG_TIME_VALID, 269 268 .name = "C1", 270 269 .desc = "MPU ON + CORE ON", 271 270 }, ··· 272 273 .enter = omap3_enter_idle_bm, 273 274 .exit_latency = 10 + 10, 274 275 .target_residency = 30, 275 - .flags = CPUIDLE_FLAG_TIME_VALID, 276 276 .name = "C2", 277 277 .desc = "MPU ON + CORE ON", 278 278 }, ··· 279 281 .enter = omap3_enter_idle_bm, 280 282 .exit_latency = 50 + 50, 281 283 .target_residency = 300, 282 - .flags = CPUIDLE_FLAG_TIME_VALID, 283 284 .name = "C3", 284 285 .desc = "MPU RET + CORE ON", 285 286 }, ··· 286 289 .enter = omap3_enter_idle_bm, 287 290 .exit_latency = 1500 + 1800, 288 291 .target_residency = 4000, 289 - .flags = CPUIDLE_FLAG_TIME_VALID, 290 292 .name = "C4", 291 293 .desc = "MPU OFF + CORE ON", 292 294 }, ··· 293 297 .enter = omap3_enter_idle_bm, 294 298 .exit_latency = 2500 + 7500, 295 299 .target_residency = 12000, 296 - .flags = CPUIDLE_FLAG_TIME_VALID, 297 300 .name = "C5", 298 301 .desc = "MPU RET + CORE RET", 299 302 }, ··· 300 305 .enter = omap3_enter_idle_bm, 301 306 .exit_latency = 3000 + 8500, 302 307 .target_residency = 15000, 303 - .flags = CPUIDLE_FLAG_TIME_VALID, 304 308 .name = "C6", 305 309 .desc = "MPU OFF + CORE RET", 306 310 }, ··· 307 313 .enter = omap3_enter_idle_bm, 308 314 .exit_latency = 10000 + 30000, 309 315 .target_residency = 30000, 310 - .flags = CPUIDLE_FLAG_TIME_VALID, 311 316 .name = "C7", 312 317 .desc = "MPU OFF + CORE OFF", 313 318 },
+2 -3
arch/arm/mach-omap2/cpuidle44xx.c
··· 196 196 /* C1 - CPU0 ON + CPU1 ON + MPU ON */ 197 197 .exit_latency = 2 + 2, 198 198 .target_residency = 5, 199 - .flags = CPUIDLE_FLAG_TIME_VALID, 200 199 .enter = omap_enter_idle_simple, 201 200 .name = "C1", 202 201 .desc = "CPUx ON, MPUSS ON" ··· 204 205 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ 205 206 .exit_latency = 328 + 440, 206 207 .target_residency = 960, 207 - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED, 208 + .flags = CPUIDLE_FLAG_COUPLED, 208 209 .enter = omap_enter_idle_coupled, 209 210 .name = "C2", 210 211 .desc = "CPUx OFF, MPUSS CSWR", ··· 213 214 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ 214 215 .exit_latency = 460 + 518, 215 216 .target_residency = 1100, 216 - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED, 217 + .flags = CPUIDLE_FLAG_COUPLED, 217 218 .enter = omap_enter_idle_coupled, 218 219 .name = "C3", 219 220 .desc = "CPUx OFF, MPUSS OSWR",
-1
arch/arm/mach-s3c64xx/cpuidle.c
··· 48 48 .enter = s3c64xx_enter_idle, 49 49 .exit_latency = 1, 50 50 .target_residency = 1, 51 - .flags = CPUIDLE_FLAG_TIME_VALID, 52 51 .name = "IDLE", 53 52 .desc = "System active, ARM gated", 54 53 },
-4
arch/arm/mach-shmobile/pm-sh7372.c
··· 423 423 .desc = "Core Standby Mode", 424 424 .exit_latency = 10, 425 425 .target_residency = 20 + 10, 426 - .flags = CPUIDLE_FLAG_TIME_VALID, 427 426 .enter = sh7372_enter_core_standby, 428 427 }, 429 428 .states[2] = { ··· 430 431 .desc = "A3SM PLL ON", 431 432 .exit_latency = 20, 432 433 .target_residency = 30 + 20, 433 - .flags = CPUIDLE_FLAG_TIME_VALID, 434 434 .enter = sh7372_enter_a3sm_pll_on, 435 435 }, 436 436 .states[3] = { ··· 437 439 .desc = "A3SM PLL OFF", 438 440 .exit_latency = 120, 439 441 .target_residency = 30 + 120, 440 - .flags = CPUIDLE_FLAG_TIME_VALID, 441 442 .enter = sh7372_enter_a3sm_pll_off, 442 443 }, 443 444 .states[4] = { ··· 444 447 .desc = "A4S PLL OFF", 445 448 .exit_latency = 240, 446 449 .target_residency = 30 + 240, 447 - .flags = CPUIDLE_FLAG_TIME_VALID, 448 450 .enter = sh7372_enter_a4s, 449 451 .disabled = true, 450 452 },
-1
arch/arm/mach-tegra/cpuidle-tegra114.c
··· 75 75 .exit_latency = 500, 76 76 .target_residency = 1000, 77 77 .power_usage = 0, 78 - .flags = CPUIDLE_FLAG_TIME_VALID, 79 78 .name = "powered-down", 80 79 .desc = "CPU power gated", 81 80 },
+1 -2
arch/arm/mach-tegra/cpuidle-tegra20.c
··· 59 59 .exit_latency = 5000, 60 60 .target_residency = 10000, 61 61 .power_usage = 0, 62 - .flags = CPUIDLE_FLAG_TIME_VALID | 63 - CPUIDLE_FLAG_COUPLED, 62 + .flags = CPUIDLE_FLAG_COUPLED, 64 63 .name = "powered-down", 65 64 .desc = "CPU power gated", 66 65 },
-1
arch/arm/mach-tegra/cpuidle-tegra30.c
··· 56 56 .exit_latency = 2000, 57 57 .target_residency = 2200, 58 58 .power_usage = 0, 59 - .flags = CPUIDLE_FLAG_TIME_VALID, 60 59 .name = "powered-down", 61 60 .desc = "CPU power gated", 62 61 },
-1
arch/mips/include/asm/idle.h
··· 22 22 .exit_latency = 1,\ 23 23 .target_residency = 1,\ 24 24 .power_usage = UINT_MAX,\ 25 - .flags = CPUIDLE_FLAG_TIME_VALID,\ 26 25 .name = "wait",\ 27 26 .desc = "MIPS wait",\ 28 27 }
-3
arch/sh/kernel/cpu/shmobile/cpuidle.c
··· 59 59 .exit_latency = 1, 60 60 .target_residency = 1 * 2, 61 61 .power_usage = 3, 62 - .flags = CPUIDLE_FLAG_TIME_VALID, 63 62 .enter = cpuidle_sleep_enter, 64 63 .name = "C1", 65 64 .desc = "SuperH Sleep Mode", ··· 67 68 .exit_latency = 100, 68 69 .target_residency = 1 * 2, 69 70 .power_usage = 1, 70 - .flags = CPUIDLE_FLAG_TIME_VALID, 71 71 .enter = cpuidle_sleep_enter, 72 72 .name = "C2", 73 73 .desc = "SuperH Sleep Mode [SF]", ··· 76 78 .exit_latency = 2300, 77 79 .target_residency = 1 * 2, 78 80 .power_usage = 1, 79 - .flags = CPUIDLE_FLAG_TIME_VALID, 80 81 .enter = cpuidle_sleep_enter, 81 82 .name = "C3", 82 83 .desc = "SuperH Mobile Standby Mode [SF]",
-1
arch/x86/kernel/apm_32.c
··· 378 378 { /* entry 1 is for APM idle */ 379 379 .name = "APM", 380 380 .desc = "APM idle", 381 - .flags = CPUIDLE_FLAG_TIME_VALID, 382 381 .exit_latency = 250, /* WAG */ 383 382 .target_residency = 500, /* WAG */ 384 383 .enter = &apm_cpu_idle
+2 -4
drivers/acpi/processor_idle.c
··· 985 985 state->flags = 0; 986 986 switch (cx->type) { 987 987 case ACPI_STATE_C1: 988 - if (cx->entry_method == ACPI_CSTATE_FFH) 989 - state->flags |= CPUIDLE_FLAG_TIME_VALID; 988 + if (cx->entry_method != ACPI_CSTATE_FFH) 989 + state->flags |= CPUIDLE_FLAG_TIME_INVALID; 990 990 991 991 state->enter = acpi_idle_enter_c1; 992 992 state->enter_dead = acpi_idle_play_dead; ··· 994 994 break; 995 995 996 996 case ACPI_STATE_C2: 997 - state->flags |= CPUIDLE_FLAG_TIME_VALID; 998 997 state->enter = acpi_idle_enter_simple; 999 998 state->enter_dead = acpi_idle_play_dead; 1000 999 drv->safe_state_index = count; 1001 1000 break; 1002 1001 1003 1002 case ACPI_STATE_C3: 1004 - state->flags |= CPUIDLE_FLAG_TIME_VALID; 1005 1003 state->enter = pr->flags.bm_check ? 1006 1004 acpi_idle_enter_bm : 1007 1005 acpi_idle_enter_simple;
-1
drivers/cpuidle/cpuidle-arm64.c
··· 73 73 .exit_latency = 1, 74 74 .target_residency = 1, 75 75 .power_usage = UINT_MAX, 76 - .flags = CPUIDLE_FLAG_TIME_VALID, 77 76 .name = "WFI", 78 77 .desc = "ARM64 WFI", 79 78 }
-1
drivers/cpuidle/cpuidle-at91.c
··· 43 43 .enter = at91_enter_idle, 44 44 .exit_latency = 10, 45 45 .target_residency = 10000, 46 - .flags = CPUIDLE_FLAG_TIME_VALID, 47 46 .name = "RAM_SR", 48 47 .desc = "WFI and DDR Self Refresh", 49 48 },
+2 -4
drivers/cpuidle/cpuidle-big_little.c
··· 67 67 .enter = bl_enter_powerdown, 68 68 .exit_latency = 700, 69 69 .target_residency = 2500, 70 - .flags = CPUIDLE_FLAG_TIME_VALID | 71 - CPUIDLE_FLAG_TIMER_STOP, 70 + .flags = CPUIDLE_FLAG_TIMER_STOP, 72 71 .name = "C1", 73 72 .desc = "ARM little-cluster power down", 74 73 }, ··· 88 89 .enter = bl_enter_powerdown, 89 90 .exit_latency = 500, 90 91 .target_residency = 2000, 91 - .flags = CPUIDLE_FLAG_TIME_VALID | 92 - CPUIDLE_FLAG_TIMER_STOP, 92 + .flags = CPUIDLE_FLAG_TIMER_STOP, 93 93 .name = "C1", 94 94 .desc = "ARM big-cluster power down", 95 95 },
-1
drivers/cpuidle/cpuidle-calxeda.c
··· 55 55 { 56 56 .name = "PG", 57 57 .desc = "Power Gate", 58 - .flags = CPUIDLE_FLAG_TIME_VALID, 59 58 .exit_latency = 30, 60 59 .power_usage = 50, 61 60 .target_residency = 200,
+2 -5
drivers/cpuidle/cpuidle-cps.c
··· 79 79 .enter = cps_nc_enter, 80 80 .exit_latency = 200, 81 81 .target_residency = 450, 82 - .flags = CPUIDLE_FLAG_TIME_VALID, 83 82 .name = "nc-wait", 84 83 .desc = "non-coherent MIPS wait", 85 84 }, ··· 86 87 .enter = cps_nc_enter, 87 88 .exit_latency = 300, 88 89 .target_residency = 700, 89 - .flags = CPUIDLE_FLAG_TIME_VALID | 90 - CPUIDLE_FLAG_TIMER_STOP, 90 + .flags = CPUIDLE_FLAG_TIMER_STOP, 91 91 .name = "clock-gated", 92 92 .desc = "core clock gated", 93 93 }, ··· 94 96 .enter = cps_nc_enter, 95 97 .exit_latency = 600, 96 98 .target_residency = 1000, 97 - .flags = CPUIDLE_FLAG_TIME_VALID | 98 - CPUIDLE_FLAG_TIMER_STOP, 99 + .flags = CPUIDLE_FLAG_TIMER_STOP, 99 100 .name = "power-gated", 100 101 .desc = "core power gated", 101 102 },
-1
drivers/cpuidle/cpuidle-exynos.c
··· 47 47 .enter = exynos_enter_lowpower, 48 48 .exit_latency = 300, 49 49 .target_residency = 100000, 50 - .flags = CPUIDLE_FLAG_TIME_VALID, 51 50 .name = "C1", 52 51 .desc = "ARM power down", 53 52 },
-1
drivers/cpuidle/cpuidle-kirkwood.c
··· 47 47 .enter = kirkwood_enter_idle, 48 48 .exit_latency = 10, 49 49 .target_residency = 100000, 50 - .flags = CPUIDLE_FLAG_TIME_VALID, 51 50 .name = "DDR SR", 52 51 .desc = "WFI and DDR Self Refresh", 53 52 },
+2 -6
drivers/cpuidle/cpuidle-mvebu-v7.c
··· 53 53 .exit_latency = 10, 54 54 .power_usage = 50, 55 55 .target_residency = 100, 56 - .flags = CPUIDLE_FLAG_TIME_VALID, 57 56 .name = "MV CPU IDLE", 58 57 .desc = "CPU power down", 59 58 }, ··· 61 62 .exit_latency = 100, 62 63 .power_usage = 5, 63 64 .target_residency = 1000, 64 - .flags = CPUIDLE_FLAG_TIME_VALID | 65 - MVEBU_V7_FLAG_DEEP_IDLE, 65 + .flags = MVEBU_V7_FLAG_DEEP_IDLE, 66 66 .name = "MV CPU DEEP IDLE", 67 67 .desc = "CPU and L2 Fabric power down", 68 68 }, ··· 76 78 .exit_latency = 100, 77 79 .power_usage = 5, 78 80 .target_residency = 1000, 79 - .flags = (CPUIDLE_FLAG_TIME_VALID | 80 - MVEBU_V7_FLAG_DEEP_IDLE), 81 + .flags = MVEBU_V7_FLAG_DEEP_IDLE, 81 82 .name = "Deep Idle", 82 83 .desc = "CPU and L2 Fabric power down", 83 84 }, ··· 91 94 .exit_latency = 10, 92 95 .power_usage = 5, 93 96 .target_residency = 100, 94 - .flags = CPUIDLE_FLAG_TIME_VALID, 95 97 .name = "Idle", 96 98 .desc = "CPU and SCU power down", 97 99 },
+2 -4
drivers/cpuidle/cpuidle-powernv.c
··· 93 93 { /* Snooze */ 94 94 .name = "snooze", 95 95 .desc = "snooze", 96 - .flags = CPUIDLE_FLAG_TIME_VALID, 97 96 .exit_latency = 0, 98 97 .target_residency = 0, 99 98 .enter = &snooze_loop }, ··· 201 202 /* Add NAP state */ 202 203 strcpy(powernv_states[nr_idle_states].name, "Nap"); 203 204 strcpy(powernv_states[nr_idle_states].desc, "Nap"); 204 - powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIME_VALID; 205 + powernv_states[nr_idle_states].flags = 0; 205 206 powernv_states[nr_idle_states].exit_latency = 206 207 ((unsigned int)latency_ns) / 1000; 207 208 powernv_states[nr_idle_states].target_residency = ··· 214 215 /* Add FASTSLEEP state */ 215 216 strcpy(powernv_states[nr_idle_states].name, "FastSleep"); 216 217 strcpy(powernv_states[nr_idle_states].desc, "FastSleep"); 217 - powernv_states[nr_idle_states].flags = 218 - CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TIMER_STOP; 218 + powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIMER_STOP; 219 219 powernv_states[nr_idle_states].exit_latency = 220 220 ((unsigned int)latency_ns) / 1000; 221 221 powernv_states[nr_idle_states].target_residency =
-3
drivers/cpuidle/cpuidle-pseries.c
··· 142 142 { /* Snooze */ 143 143 .name = "snooze", 144 144 .desc = "snooze", 145 - .flags = CPUIDLE_FLAG_TIME_VALID, 146 145 .exit_latency = 0, 147 146 .target_residency = 0, 148 147 .enter = &snooze_loop }, 149 148 { /* CEDE */ 150 149 .name = "CEDE", 151 150 .desc = "CEDE", 152 - .flags = CPUIDLE_FLAG_TIME_VALID, 153 151 .exit_latency = 10, 154 152 .target_residency = 100, 155 153 .enter = &dedicated_cede_loop }, ··· 160 162 { /* Shared Cede */ 161 163 .name = "Shared Cede", 162 164 .desc = "Shared Cede", 163 - .flags = CPUIDLE_FLAG_TIME_VALID, 164 165 .exit_latency = 0, 165 166 .target_residency = 0, 166 167 .enter = &shared_cede_loop },
+1 -2
drivers/cpuidle/cpuidle-ux500.c
··· 101 101 .enter = ux500_enter_idle, 102 102 .exit_latency = 70, 103 103 .target_residency = 260, 104 - .flags = CPUIDLE_FLAG_TIME_VALID | 105 - CPUIDLE_FLAG_TIMER_STOP, 104 + .flags = CPUIDLE_FLAG_TIMER_STOP, 106 105 .name = "ApIdle", 107 106 .desc = "ARM Retention", 108 107 },
-1
drivers/cpuidle/cpuidle-zynq.c
··· 52 52 .enter = zynq_enter_idle, 53 53 .exit_latency = 10, 54 54 .target_residency = 10000, 55 - .flags = CPUIDLE_FLAG_TIME_VALID, 56 55 .name = "RAM_SR", 57 56 .desc = "WFI and RAM Self Refresh", 58 57 },
-1
drivers/cpuidle/driver.c
··· 201 201 state->exit_latency = 0; 202 202 state->target_residency = 0; 203 203 state->power_usage = -1; 204 - state->flags = CPUIDLE_FLAG_TIME_VALID; 205 204 state->enter = poll_idle; 206 205 state->disabled = false; 207 206 }
+1 -1
drivers/cpuidle/dt_idle_states.c
··· 73 73 return -EINVAL; 74 74 } 75 75 76 - idle_state->flags = CPUIDLE_FLAG_TIME_VALID; 76 + idle_state->flags = 0; 77 77 if (of_property_read_bool(state_node, "local-timer-stop")) 78 78 idle_state->flags |= CPUIDLE_FLAG_TIMER_STOP; 79 79 /*
+1 -1
drivers/cpuidle/governors/ladder.c
··· 79 79 80 80 last_state = &ldev->states[last_idx]; 81 81 82 - if (drv->states[last_idx].flags & CPUIDLE_FLAG_TIME_VALID) { 82 + if (!(drv->states[last_idx].flags & CPUIDLE_FLAG_TIME_INVALID)) { 83 83 last_residency = cpuidle_get_last_residency(dev) - \ 84 84 drv->states[last_idx].exit_latency; 85 85 }
+1 -1
drivers/cpuidle/governors/menu.c
··· 405 405 * the measured amount of time is less than the exit latency, 406 406 * assume the state was never reached and the exit latency is 0. 407 407 */ 408 - if (unlikely(!(target->flags & CPUIDLE_FLAG_TIME_VALID))) { 408 + if (unlikely(target->flags & CPUIDLE_FLAG_TIME_INVALID)) { 409 409 /* Use timer value as is */ 410 410 measured_us = data->next_timer_us; 411 411
+54 -54
drivers/idle/intel_idle.c
··· 128 128 { 129 129 .name = "C1-NHM", 130 130 .desc = "MWAIT 0x00", 131 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 131 + .flags = MWAIT2flg(0x00), 132 132 .exit_latency = 3, 133 133 .target_residency = 6, 134 134 .enter = &intel_idle }, 135 135 { 136 136 .name = "C1E-NHM", 137 137 .desc = "MWAIT 0x01", 138 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 138 + .flags = MWAIT2flg(0x01), 139 139 .exit_latency = 10, 140 140 .target_residency = 20, 141 141 .enter = &intel_idle }, 142 142 { 143 143 .name = "C3-NHM", 144 144 .desc = "MWAIT 0x10", 145 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 145 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 146 146 .exit_latency = 20, 147 147 .target_residency = 80, 148 148 .enter = &intel_idle }, 149 149 { 150 150 .name = "C6-NHM", 151 151 .desc = "MWAIT 0x20", 152 - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 152 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 153 153 .exit_latency = 200, 154 154 .target_residency = 800, 155 155 .enter = &intel_idle }, ··· 161 161 { 162 162 .name = "C1-SNB", 163 163 .desc = "MWAIT 0x00", 164 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 164 + .flags = MWAIT2flg(0x00), 165 165 .exit_latency = 2, 166 166 .target_residency = 2, 167 167 .enter = &intel_idle }, 168 168 { 169 169 .name = "C1E-SNB", 170 170 .desc = "MWAIT 0x01", 171 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 171 + .flags = MWAIT2flg(0x01), 172 172 .exit_latency = 10, 173 173 .target_residency = 20, 174 174 .enter = &intel_idle }, 175 175 { 176 176 .name = "C3-SNB", 177 177 .desc = "MWAIT 0x10", 178 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 178 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 179 179 .exit_latency = 80, 180 180 .target_residency = 211, 181 181 .enter = &intel_idle }, 182 182 { 183 183 .name = "C6-SNB", 184 184 .desc = "MWAIT 0x20", 185 - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 185 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 186 186 .exit_latency = 104, 187 187 .target_residency = 345, 188 188 .enter = &intel_idle }, 189 189 { 190 190 .name = "C7-SNB", 191 191 .desc = "MWAIT 0x30", 192 - .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 192 + .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 193 193 .exit_latency = 109, 194 194 .target_residency = 345, 195 195 .enter = &intel_idle }, ··· 201 201 { 202 202 .name = "C1-BYT", 203 203 .desc = "MWAIT 0x00", 204 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 204 + .flags = MWAIT2flg(0x00), 205 205 .exit_latency = 1, 206 206 .target_residency = 1, 207 207 .enter = &intel_idle }, 208 208 { 209 209 .name = "C1E-BYT", 210 210 .desc = "MWAIT 0x01", 211 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 211 + .flags = MWAIT2flg(0x01), 212 212 .exit_latency = 15, 213 213 .target_residency = 30, 214 214 .enter = &intel_idle }, 215 215 { 216 216 .name = "C6N-BYT", 217 217 .desc = "MWAIT 0x58", 218 - .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 218 + .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, 219 219 .exit_latency = 40, 220 220 .target_residency = 275, 221 221 .enter = &intel_idle }, 222 222 { 223 223 .name = "C6S-BYT", 224 224 .desc = "MWAIT 0x52", 225 - .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 225 + .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 226 226 .exit_latency = 140, 227 227 .target_residency = 560, 228 228 .enter = &intel_idle }, 229 229 { 230 230 .name = "C7-BYT", 231 231 .desc = "MWAIT 0x60", 232 - .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 232 + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 233 233 .exit_latency = 1200, 234 234 .target_residency = 1500, 235 235 .enter = &intel_idle }, 236 236 { 237 237 .name = "C7S-BYT", 238 238 .desc = "MWAIT 0x64", 239 - .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 239 + .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, 240 240 .exit_latency = 10000, 241 241 .target_residency = 20000, 242 242 .enter = &intel_idle }, ··· 248 248 { 249 249 .name = "C1-IVB", 250 250 .desc = "MWAIT 0x00", 251 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 251 + .flags = MWAIT2flg(0x00), 252 252 .exit_latency = 1, 253 253 .target_residency = 1, 254 254 .enter = &intel_idle }, 255 255 { 256 256 .name = "C1E-IVB", 257 257 .desc = "MWAIT 0x01", 258 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 258 + .flags = MWAIT2flg(0x01), 259 259 .exit_latency = 10, 260 260 .target_residency = 20, 261 261 .enter = &intel_idle }, 262 262 { 263 263 .name = "C3-IVB", 264 264 .desc = "MWAIT 0x10", 265 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 265 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 266 266 .exit_latency = 59, 267 267 .target_residency = 156, 268 268 .enter = &intel_idle }, 269 269 { 270 270 .name = "C6-IVB", 271 271 .desc = "MWAIT 0x20", 272 - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 272 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 273 273 .exit_latency = 80, 274 274 .target_residency = 300, 275 275 .enter = &intel_idle }, 276 276 { 277 277 .name = "C7-IVB", 278 278 .desc = "MWAIT 0x30", 279 - .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 279 + .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 280 280 .exit_latency = 87, 281 281 .target_residency = 300, 282 282 .enter = &intel_idle }, ··· 288 288 { 289 289 .name = "C1-IVT", 290 290 .desc = "MWAIT 0x00", 291 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 291 + .flags = MWAIT2flg(0x00), 292 292 .exit_latency = 1, 293 293 .target_residency = 1, 294 294 .enter = &intel_idle }, 295 295 { 296 296 .name = "C1E-IVT", 297 297 .desc = "MWAIT 0x01", 298 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 298 + .flags = MWAIT2flg(0x01), 299 299 .exit_latency = 10, 300 300 .target_residency = 80, 301 301 .enter = &intel_idle }, 302 302 { 303 303 .name = "C3-IVT", 304 304 .desc = "MWAIT 0x10", 305 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 305 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 306 306 .exit_latency = 59, 307 307 .target_residency = 156, 308 308 .enter = &intel_idle }, 309 309 { 310 310 .name = "C6-IVT", 311 311 .desc = "MWAIT 0x20", 312 - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 312 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 313 313 .exit_latency = 82, 314 314 .target_residency = 300, 315 315 .enter = &intel_idle }, ··· 321 321 { 322 322 .name = "C1-IVT-4S", 323 323 .desc = "MWAIT 0x00", 324 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 324 + .flags = MWAIT2flg(0x00), 325 325 .exit_latency = 1, 326 326 .target_residency = 1, 327 327 .enter = &intel_idle }, 328 328 { 329 329 .name = "C1E-IVT-4S", 330 330 .desc = "MWAIT 0x01", 331 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 331 + .flags = MWAIT2flg(0x01), 332 332 .exit_latency = 10, 333 333 .target_residency = 250, 334 334 .enter = &intel_idle }, 335 335 { 336 336 .name = "C3-IVT-4S", 337 337 .desc = "MWAIT 0x10", 338 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 338 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 339 339 .exit_latency = 59, 340 340 .target_residency = 300, 341 341 .enter = &intel_idle }, 342 342 { 343 343 .name = "C6-IVT-4S", 344 344 .desc = "MWAIT 0x20", 345 - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 345 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 346 346 .exit_latency = 84, 347 347 .target_residency = 400, 348 348 .enter = &intel_idle }, ··· 354 354 { 355 355 .name = "C1-IVT-8S", 356 356 .desc = "MWAIT 0x00", 357 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 357 + .flags = MWAIT2flg(0x00), 358 358 .exit_latency = 1, 359 359 .target_residency = 1, 360 360 .enter = &intel_idle }, 361 361 { 362 362 .name = "C1E-IVT-8S", 363 363 .desc = "MWAIT 0x01", 364 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 364 + .flags = MWAIT2flg(0x01), 365 365 .exit_latency = 10, 366 366 .target_residency = 500, 367 367 .enter = &intel_idle }, 368 368 { 369 369 .name = "C3-IVT-8S", 370 370 .desc = "MWAIT 0x10", 371 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 371 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 372 372 .exit_latency = 59, 373 373 .target_residency = 600, 374 374 .enter = &intel_idle }, 375 375 { 376 376 .name = "C6-IVT-8S", 377 377 .desc = "MWAIT 0x20", 378 - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 378 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 379 379 .exit_latency = 88, 380 380 .target_residency = 700, 381 381 .enter = &intel_idle }, ··· 387 387 { 388 388 .name = "C1-HSW", 389 389 .desc = "MWAIT 0x00", 390 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 390 + .flags = MWAIT2flg(0x00), 391 391 .exit_latency = 2, 392 392 .target_residency = 2, 393 393 .enter = &intel_idle }, 394 394 { 395 395 .name = "C1E-HSW", 396 396 .desc = "MWAIT 0x01", 397 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 397 + .flags = MWAIT2flg(0x01), 398 398 .exit_latency = 10, 399 399 .target_residency = 20, 400 400 .enter = &intel_idle }, 401 401 { 402 402 .name = "C3-HSW", 403 403 .desc = "MWAIT 0x10", 404 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 404 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 405 405 .exit_latency = 33, 406 406 .target_residency = 100, 407 407 .enter = &intel_idle }, 408 408 { 409 409 .name = "C6-HSW", 410 410 .desc = "MWAIT 0x20", 411 - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 411 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 412 412 .exit_latency = 133, 413 413 .target_residency = 400, 414 414 .enter = &intel_idle }, 415 415 { 416 416 .name = "C7s-HSW", 417 417 .desc = "MWAIT 0x32", 418 - .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 418 + .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, 419 419 .exit_latency = 166, 420 420 .target_residency = 500, 421 421 .enter = &intel_idle }, 422 422 { 423 423 .name = "C8-HSW", 424 424 .desc = "MWAIT 0x40", 425 - .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 425 + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 426 426 .exit_latency = 300, 427 427 .target_residency = 900, 428 428 .enter = &intel_idle }, 429 429 { 430 430 .name = "C9-HSW", 431 431 .desc = "MWAIT 0x50", 432 - .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 432 + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 433 433 .exit_latency = 600, 434 434 .target_residency = 1800, 435 435 .enter = &intel_idle }, 436 436 { 437 437 .name = "C10-HSW", 438 438 .desc = "MWAIT 0x60", 439 - .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 439 + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 440 440 .exit_latency = 2600, 441 441 .target_residency = 7700, 442 442 .enter = &intel_idle }, ··· 447 447 { 448 448 .name = "C1-BDW", 449 449 .desc = "MWAIT 0x00", 450 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 450 + .flags = MWAIT2flg(0x00), 451 451 .exit_latency = 2, 452 452 .target_residency = 2, 453 453 .enter = &intel_idle }, 454 454 { 455 455 .name = "C1E-BDW", 456 456 .desc = "MWAIT 0x01", 457 - .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 457 + .flags = MWAIT2flg(0x01), 458 458 .exit_latency = 10, 459 459 .target_residency = 20, 460 460 .enter = &intel_idle }, 461 461 { 462 462 .name = "C3-BDW", 463 463 .desc = "MWAIT 0x10", 464 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 464 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 465 465 .exit_latency = 40, 466 466 .target_residency = 100, 467 467 .enter = &intel_idle }, 468 468 { 469 469 .name = "C6-BDW", 470 470 .desc = "MWAIT 0x20", 471 - .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 471 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 472 472 .exit_latency = 133, 473 473 .target_residency = 400, 474 474 .enter = &intel_idle }, 475 475 { 476 476 .name = "C7s-BDW", 477 477 .desc = "MWAIT 0x32", 478 - .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 478 + .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, 479 479 .exit_latency = 166, 480 480 .target_residency = 500, 481 481 .enter = &intel_idle }, 482 482 { 483 483 .name = "C8-BDW", 484 484 .desc = "MWAIT 0x40", 485 - .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 485 + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 486 486 .exit_latency = 300, 487 487 .target_residency = 900, 488 488 .enter = &intel_idle }, 489 489 { 490 490 .name = "C9-BDW", 491 491 .desc = "MWAIT 0x50", 492 - .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 492 + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 493 493 .exit_latency = 600, 494 494 .target_residency = 1800, 495 495 .enter = &intel_idle }, 496 496 { 497 497 .name = "C10-BDW", 498 498 .desc = "MWAIT 0x60", 499 - .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 499 + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 500 500 .exit_latency = 2600, 501 501 .target_residency = 7700, 502 502 .enter = &intel_idle }, ··· 508 508 { 509 509 .name = "C1E-ATM", 510 510 .desc = "MWAIT 0x00", 511 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 511 + .flags = MWAIT2flg(0x00), 512 512 .exit_latency = 10, 513 513 .target_residency = 20, 514 514 .enter = &intel_idle }, 515 515 { 516 516 .name = "C2-ATM", 517 517 .desc = "MWAIT 0x10", 518 - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID, 518 + .flags = MWAIT2flg(0x10), 519 519 .exit_latency = 20, 520 520 .target_residency = 80, 521 521 .enter = &intel_idle }, 522 522 { 523 523 .name = "C4-ATM", 524 524 .desc = "MWAIT 0x30", 525 - .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 525 + .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 526 526 .exit_latency = 100, 527 527 .target_residency = 400, 528 528 .enter = &intel_idle }, 529 529 { 530 530 .name = "C6-ATM", 531 531 .desc = "MWAIT 0x52", 532 - .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 532 + .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 533 533 .exit_latency = 140, 534 534 .target_residency = 560, 535 535 .enter = &intel_idle }, ··· 540 540 { 541 541 .name = "C1-AVN", 542 542 .desc = "MWAIT 0x00", 543 - .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 543 + .flags = MWAIT2flg(0x00), 544 544 .exit_latency = 2, 545 545 .target_residency = 2, 546 546 .enter = &intel_idle }, 547 547 { 548 548 .name = "C6-AVN", 549 549 .desc = "MWAIT 0x51", 550 - .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 550 + .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, 551 551 .exit_latency = 15, 552 552 .target_residency = 45, 553 553 .enter = &intel_idle },
+2 -2
include/linux/cpuidle.h
··· 53 53 }; 54 54 55 55 /* Idle State Flags */ 56 - #define CPUIDLE_FLAG_TIME_VALID (0x01) /* is residency time measurable? */ 56 + #define CPUIDLE_FLAG_TIME_INVALID (0x01) /* is residency time measurable? */ 57 57 #define CPUIDLE_FLAG_COUPLED (0x02) /* state applies to multiple cpus */ 58 58 #define CPUIDLE_FLAG_TIMER_STOP (0x04) /* timer is stopped on this state */ 59 59 ··· 90 90 * cpuidle_get_last_residency - retrieves the last state's residency time 91 91 * @dev: the target CPU 92 92 * 93 - * NOTE: this value is invalid if CPUIDLE_FLAG_TIME_VALID isn't set 93 + * NOTE: this value is invalid if CPUIDLE_FLAG_TIME_INVALID is set 94 94 */ 95 95 static inline int cpuidle_get_last_residency(struct cpuidle_device *dev) 96 96 {