tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Disintegrate asm/system.h for MIPS
Disintegrate asm/system.h for MIPS.
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
cc: linux-mips@linux-mips.org
+262
-309
-1
arch/mips/cavium-octeon/setup.c
-1
arch/mips/cavium-octeon/setup.c
+1
-1
arch/mips/cavium-octeon/smp.c
+1
-1
arch/mips/cavium-octeon/smp.c
-1
arch/mips/dec/ecc-berr.c
-1
arch/mips/dec/ecc-berr.c
-1
arch/mips/dec/kn01-berr.c
-1
arch/mips/dec/kn01-berr.c
-1
arch/mips/dec/kn02xa-berr.c
-1
arch/mips/dec/kn02xa-berr.c
+1
-1
arch/mips/dec/wbflush.c
+1
-1
arch/mips/dec/wbflush.c
-1
arch/mips/emma/markeins/irq.c
-1
arch/mips/emma/markeins/irq.c
-1
arch/mips/fw/arc/misc.c
-1
arch/mips/fw/arc/misc.c
+1
-1
arch/mips/include/asm/atomic.h
+1
-1
arch/mips/include/asm/atomic.h
+2
arch/mips/include/asm/barrier.h
+2
arch/mips/include/asm/barrier.h
+124
arch/mips/include/asm/cmpxchg.h
+124
arch/mips/include/asm/cmpxchg.h
···
9
9
#define __ASM_CMPXCHG_H
10
10
11
11
#include <linux/irqflags.h>
12
+
#include <asm/war.h>
13
+
14
+
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
15
+
{
16
+
__u32 retval;
17
+
18
+
smp_mb__before_llsc();
19
+
20
+
if (kernel_uses_llsc && R10000_LLSC_WAR) {
21
+
unsigned long dummy;
22
+
23
+
__asm__ __volatile__(
24
+
" .set mips3 \n"
25
+
"1: ll %0, %3 # xchg_u32 \n"
26
+
" .set mips0 \n"
27
+
" move %2, %z4 \n"
28
+
" .set mips3 \n"
29
+
" sc %2, %1 \n"
30
+
" beqzl %2, 1b \n"
31
+
" .set mips0 \n"
32
+
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
33
+
: "R" (*m), "Jr" (val)
34
+
: "memory");
35
+
} else if (kernel_uses_llsc) {
36
+
unsigned long dummy;
37
+
38
+
do {
39
+
__asm__ __volatile__(
40
+
" .set mips3 \n"
41
+
" ll %0, %3 # xchg_u32 \n"
42
+
" .set mips0 \n"
43
+
" move %2, %z4 \n"
44
+
" .set mips3 \n"
45
+
" sc %2, %1 \n"
46
+
" .set mips0 \n"
47
+
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
48
+
: "R" (*m), "Jr" (val)
49
+
: "memory");
50
+
} while (unlikely(!dummy));
51
+
} else {
52
+
unsigned long flags;
53
+
54
+
raw_local_irq_save(flags);
55
+
retval = *m;
56
+
*m = val;
57
+
raw_local_irq_restore(flags); /* implies memory barrier */
58
+
}
59
+
60
+
smp_llsc_mb();
61
+
62
+
return retval;
63
+
}
64
+
65
+
#ifdef CONFIG_64BIT
66
+
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
67
+
{
68
+
__u64 retval;
69
+
70
+
smp_mb__before_llsc();
71
+
72
+
if (kernel_uses_llsc && R10000_LLSC_WAR) {
73
+
unsigned long dummy;
74
+
75
+
__asm__ __volatile__(
76
+
" .set mips3 \n"
77
+
"1: lld %0, %3 # xchg_u64 \n"
78
+
" move %2, %z4 \n"
79
+
" scd %2, %1 \n"
80
+
" beqzl %2, 1b \n"
81
+
" .set mips0 \n"
82
+
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
83
+
: "R" (*m), "Jr" (val)
84
+
: "memory");
85
+
} else if (kernel_uses_llsc) {
86
+
unsigned long dummy;
87
+
88
+
do {
89
+
__asm__ __volatile__(
90
+
" .set mips3 \n"
91
+
" lld %0, %3 # xchg_u64 \n"
92
+
" move %2, %z4 \n"
93
+
" scd %2, %1 \n"
94
+
" .set mips0 \n"
95
+
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
96
+
: "R" (*m), "Jr" (val)
97
+
: "memory");
98
+
} while (unlikely(!dummy));
99
+
} else {
100
+
unsigned long flags;
101
+
102
+
raw_local_irq_save(flags);
103
+
retval = *m;
104
+
*m = val;
105
+
raw_local_irq_restore(flags); /* implies memory barrier */
106
+
}
107
+
108
+
smp_llsc_mb();
109
+
110
+
return retval;
111
+
}
112
+
#else
113
+
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
114
+
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
115
+
#endif
116
+
117
+
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
118
+
{
119
+
switch (size) {
120
+
case 4:
121
+
return __xchg_u32(ptr, x);
122
+
case 8:
123
+
return __xchg_u64(ptr, x);
124
+
}
125
+
126
+
return x;
127
+
}
128
+
129
+
#define xchg(ptr, x) \
130
+
({ \
131
+
BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
132
+
\
133
+
((__typeof__(*(ptr))) \
134
+
__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
135
+
})
12
136
13
137
#define __HAVE_ARCH_CMPXCHG 1
14
138
-1
arch/mips/include/asm/dma.h
-1
arch/mips/include/asm/dma.h
+17
arch/mips/include/asm/exec.h
+17
arch/mips/include/asm/exec.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7
+
* Copyright (C) 1996 by Paul M. Antoine
8
+
* Copyright (C) 1999 Silicon Graphics
9
+
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10
+
* Copyright (C) 2000 MIPS Technologies, Inc.
11
+
*/
12
+
#ifndef _ASM_EXEC_H
13
+
#define _ASM_EXEC_H
14
+
15
+
extern unsigned long arch_align_stack(unsigned long sp);
16
+
17
+
#endif /* _ASM_EXEC_H */
-1
arch/mips/include/asm/mach-au1x00/au1000_dma.h
-1
arch/mips/include/asm/mach-au1x00/au1000_dma.h
+6
-1
arch/mips/include/asm/processor.h
+6
-1
arch/mips/include/asm/processor.h
···
19
19
#include <asm/cpu-info.h>
20
20
#include <asm/mipsregs.h>
21
21
#include <asm/prefetch.h>
22
-
#include <asm/system.h>
23
22
24
23
/*
25
24
* Return current * instruction pointer ("program counter").
···
354
355
355
356
#define ARCH_HAS_PREFETCHW
356
357
#define prefetchw(x) __builtin_prefetch((x), 1, 1)
358
+
359
+
/*
360
+
* See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
361
+
* systems.
362
+
*/
363
+
#define __ARCH_WANT_UNLOCKED_CTXSW
357
364
358
365
#endif
359
366
+11
arch/mips/include/asm/setup.h
+11
arch/mips/include/asm/setup.h
···
5
5
6
6
#ifdef __KERNEL__
7
7
extern void setup_early_printk(void);
8
+
9
+
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
10
+
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
11
+
12
+
typedef void (*vi_handler_t)(void);
13
+
extern void *set_vi_handler(int n, vi_handler_t addr);
14
+
15
+
extern void *set_except_vector(int n, void *addr);
16
+
extern unsigned long ebase;
17
+
extern void per_cpu_trap_init(void);
18
+
8
19
#endif /* __KERNEL__ */
9
20
10
21
#endif /* __SETUP_H */
+85
arch/mips/include/asm/switch_to.h
+85
arch/mips/include/asm/switch_to.h
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7
+
* Copyright (C) 1996 by Paul M. Antoine
8
+
* Copyright (C) 1999 Silicon Graphics
9
+
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10
+
* Copyright (C) 2000 MIPS Technologies, Inc.
11
+
*/
12
+
#ifndef _ASM_SWITCH_TO_H
13
+
#define _ASM_SWITCH_TO_H
14
+
15
+
#include <asm/cpu-features.h>
16
+
#include <asm/watch.h>
17
+
#include <asm/dsp.h>
18
+
19
+
struct task_struct;
20
+
21
+
/*
22
+
* switch_to(n) should switch tasks to task nr n, first
23
+
* checking that n isn't the current task, in which case it does nothing.
24
+
*/
25
+
extern asmlinkage void *resume(void *last, void *next, void *next_ti);
26
+
27
+
extern unsigned int ll_bit;
28
+
extern struct task_struct *ll_task;
29
+
30
+
#ifdef CONFIG_MIPS_MT_FPAFF
31
+
32
+
/*
33
+
* Handle the scheduler resume end of FPU affinity management. We do this
34
+
* inline to try to keep the overhead down. If we have been forced to run on
35
+
* a "CPU" with an FPU because of a previous high level of FP computation,
36
+
* but did not actually use the FPU during the most recent time-slice (CU1
37
+
* isn't set), we undo the restriction on cpus_allowed.
38
+
*
39
+
* We're not calling set_cpus_allowed() here, because we have no need to
40
+
* force prompt migration - we're already switching the current CPU to a
41
+
* different thread.
42
+
*/
43
+
44
+
#define __mips_mt_fpaff_switch_to(prev) \
45
+
do { \
46
+
struct thread_info *__prev_ti = task_thread_info(prev); \
47
+
\
48
+
if (cpu_has_fpu && \
49
+
test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
50
+
(!(KSTK_STATUS(prev) & ST0_CU1))) { \
51
+
clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
52
+
prev->cpus_allowed = prev->thread.user_cpus_allowed; \
53
+
} \
54
+
next->thread.emulated_fp = 0; \
55
+
} while(0)
56
+
57
+
#else
58
+
#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
59
+
#endif
60
+
61
+
#define __clear_software_ll_bit() \
62
+
do { \
63
+
if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
64
+
ll_bit = 0; \
65
+
} while (0)
66
+
67
+
#define switch_to(prev, next, last) \
68
+
do { \
69
+
__mips_mt_fpaff_switch_to(prev); \
70
+
if (cpu_has_dsp) \
71
+
__save_dsp(prev); \
72
+
__clear_software_ll_bit(); \
73
+
(last) = resume(prev, next, task_thread_info(next)); \
74
+
} while (0)
75
+
76
+
#define finish_arch_switch(prev) \
77
+
do { \
78
+
if (cpu_has_dsp) \
79
+
__restore_dsp(current); \
80
+
if (cpu_has_userlocal) \
81
+
write_c0_userlocal(current_thread_info()->tp_value); \
82
+
__restore_watch(); \
83
+
} while (0)
84
+
85
+
#endif /* _ASM_SWITCH_TO_H */
+3
-233
arch/mips/include/asm/system.h
+3
-233
arch/mips/include/asm/system.h
···
1
-
/*
2
-
* This file is subject to the terms and conditions of the GNU General Public
3
-
* License. See the file "COPYING" in the main directory of this archive
4
-
* for more details.
5
-
*
6
-
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7
-
* Copyright (C) 1996 by Paul M. Antoine
8
-
* Copyright (C) 1999 Silicon Graphics
9
-
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10
-
* Copyright (C) 2000 MIPS Technologies, Inc.
11
-
*/
12
-
#ifndef _ASM_SYSTEM_H
13
-
#define _ASM_SYSTEM_H
14
-
15
-
#include <linux/kernel.h>
16
-
#include <linux/types.h>
17
-
#include <linux/irqflags.h>
18
-
19
-
#include <asm/addrspace.h>
1
+
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
20
2
#include <asm/barrier.h>
21
3
#include <asm/cmpxchg.h>
22
-
#include <asm/cpu-features.h>
23
-
#include <asm/dsp.h>
24
-
#include <asm/watch.h>
25
-
#include <asm/war.h>
26
-
27
-
28
-
/*
29
-
* switch_to(n) should switch tasks to task nr n, first
30
-
* checking that n isn't the current task, in which case it does nothing.
31
-
*/
32
-
extern asmlinkage void *resume(void *last, void *next, void *next_ti);
33
-
34
-
struct task_struct;
35
-
36
-
extern unsigned int ll_bit;
37
-
extern struct task_struct *ll_task;
38
-
39
-
#ifdef CONFIG_MIPS_MT_FPAFF
40
-
41
-
/*
42
-
* Handle the scheduler resume end of FPU affinity management. We do this
43
-
* inline to try to keep the overhead down. If we have been forced to run on
44
-
* a "CPU" with an FPU because of a previous high level of FP computation,
45
-
* but did not actually use the FPU during the most recent time-slice (CU1
46
-
* isn't set), we undo the restriction on cpus_allowed.
47
-
*
48
-
* We're not calling set_cpus_allowed() here, because we have no need to
49
-
* force prompt migration - we're already switching the current CPU to a
50
-
* different thread.
51
-
*/
52
-
53
-
#define __mips_mt_fpaff_switch_to(prev) \
54
-
do { \
55
-
struct thread_info *__prev_ti = task_thread_info(prev); \
56
-
\
57
-
if (cpu_has_fpu && \
58
-
test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
59
-
(!(KSTK_STATUS(prev) & ST0_CU1))) { \
60
-
clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
61
-
prev->cpus_allowed = prev->thread.user_cpus_allowed; \
62
-
} \
63
-
next->thread.emulated_fp = 0; \
64
-
} while(0)
65
-
66
-
#else
67
-
#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
68
-
#endif
69
-
70
-
#define __clear_software_ll_bit() \
71
-
do { \
72
-
if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
73
-
ll_bit = 0; \
74
-
} while (0)
75
-
76
-
#define switch_to(prev, next, last) \
77
-
do { \
78
-
__mips_mt_fpaff_switch_to(prev); \
79
-
if (cpu_has_dsp) \
80
-
__save_dsp(prev); \
81
-
__clear_software_ll_bit(); \
82
-
(last) = resume(prev, next, task_thread_info(next)); \
83
-
} while (0)
84
-
85
-
#define finish_arch_switch(prev) \
86
-
do { \
87
-
if (cpu_has_dsp) \
88
-
__restore_dsp(current); \
89
-
if (cpu_has_userlocal) \
90
-
write_c0_userlocal(current_thread_info()->tp_value); \
91
-
__restore_watch(); \
92
-
} while (0)
93
-
94
-
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
95
-
{
96
-
__u32 retval;
97
-
98
-
smp_mb__before_llsc();
99
-
100
-
if (kernel_uses_llsc && R10000_LLSC_WAR) {
101
-
unsigned long dummy;
102
-
103
-
__asm__ __volatile__(
104
-
" .set mips3 \n"
105
-
"1: ll %0, %3 # xchg_u32 \n"
106
-
" .set mips0 \n"
107
-
" move %2, %z4 \n"
108
-
" .set mips3 \n"
109
-
" sc %2, %1 \n"
110
-
" beqzl %2, 1b \n"
111
-
" .set mips0 \n"
112
-
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
113
-
: "R" (*m), "Jr" (val)
114
-
: "memory");
115
-
} else if (kernel_uses_llsc) {
116
-
unsigned long dummy;
117
-
118
-
do {
119
-
__asm__ __volatile__(
120
-
" .set mips3 \n"
121
-
" ll %0, %3 # xchg_u32 \n"
122
-
" .set mips0 \n"
123
-
" move %2, %z4 \n"
124
-
" .set mips3 \n"
125
-
" sc %2, %1 \n"
126
-
" .set mips0 \n"
127
-
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
128
-
: "R" (*m), "Jr" (val)
129
-
: "memory");
130
-
} while (unlikely(!dummy));
131
-
} else {
132
-
unsigned long flags;
133
-
134
-
raw_local_irq_save(flags);
135
-
retval = *m;
136
-
*m = val;
137
-
raw_local_irq_restore(flags); /* implies memory barrier */
138
-
}
139
-
140
-
smp_llsc_mb();
141
-
142
-
return retval;
143
-
}
144
-
145
-
#ifdef CONFIG_64BIT
146
-
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
147
-
{
148
-
__u64 retval;
149
-
150
-
smp_mb__before_llsc();
151
-
152
-
if (kernel_uses_llsc && R10000_LLSC_WAR) {
153
-
unsigned long dummy;
154
-
155
-
__asm__ __volatile__(
156
-
" .set mips3 \n"
157
-
"1: lld %0, %3 # xchg_u64 \n"
158
-
" move %2, %z4 \n"
159
-
" scd %2, %1 \n"
160
-
" beqzl %2, 1b \n"
161
-
" .set mips0 \n"
162
-
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
163
-
: "R" (*m), "Jr" (val)
164
-
: "memory");
165
-
} else if (kernel_uses_llsc) {
166
-
unsigned long dummy;
167
-
168
-
do {
169
-
__asm__ __volatile__(
170
-
" .set mips3 \n"
171
-
" lld %0, %3 # xchg_u64 \n"
172
-
" move %2, %z4 \n"
173
-
" scd %2, %1 \n"
174
-
" .set mips0 \n"
175
-
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
176
-
: "R" (*m), "Jr" (val)
177
-
: "memory");
178
-
} while (unlikely(!dummy));
179
-
} else {
180
-
unsigned long flags;
181
-
182
-
raw_local_irq_save(flags);
183
-
retval = *m;
184
-
*m = val;
185
-
raw_local_irq_restore(flags); /* implies memory barrier */
186
-
}
187
-
188
-
smp_llsc_mb();
189
-
190
-
return retval;
191
-
}
192
-
#else
193
-
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
194
-
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
195
-
#endif
196
-
197
-
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
198
-
{
199
-
switch (size) {
200
-
case 4:
201
-
return __xchg_u32(ptr, x);
202
-
case 8:
203
-
return __xchg_u64(ptr, x);
204
-
}
205
-
206
-
return x;
207
-
}
208
-
209
-
#define xchg(ptr, x) \
210
-
({ \
211
-
BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
212
-
\
213
-
((__typeof__(*(ptr))) \
214
-
__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
215
-
})
216
-
217
-
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
218
-
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
219
-
220
-
typedef void (*vi_handler_t)(void);
221
-
extern void *set_vi_handler(int n, vi_handler_t addr);
222
-
223
-
extern void *set_except_vector(int n, void *addr);
224
-
extern unsigned long ebase;
225
-
extern void per_cpu_trap_init(void);
226
-
227
-
/*
228
-
* See include/asm-ia64/system.h; prevents deadlock on SMP
229
-
* systems.
230
-
*/
231
-
#define __ARCH_WANT_UNLOCKED_CTXSW
232
-
233
-
extern unsigned long arch_align_stack(unsigned long sp);
234
-
235
-
#endif /* _ASM_SYSTEM_H */
4
+
#include <asm/exec.h>
5
+
#include <asm/switch_to.h>
-1
arch/mips/include/asm/txx9/jmr3927.h
-1
arch/mips/include/asm/txx9/jmr3927.h
+1
-1
arch/mips/kernel/cpu-bugs64.c
+1
-1
arch/mips/kernel/cpu-bugs64.c
-1
arch/mips/kernel/cpu-probe.c
-1
arch/mips/kernel/cpu-probe.c
-1
arch/mips/kernel/irq-rm7000.c
-1
arch/mips/kernel/irq-rm7000.c
-1
arch/mips/kernel/irq-rm9000.c
-1
arch/mips/kernel/irq-rm9000.c
-1
arch/mips/kernel/irq.c
-1
arch/mips/kernel/irq.c
-1
arch/mips/kernel/irq_cpu.c
-1
arch/mips/kernel/irq_cpu.c
-1
arch/mips/kernel/mips-mt.c
-1
arch/mips/kernel/mips-mt.c
-1
arch/mips/kernel/process.c
-1
arch/mips/kernel/process.c
-1
arch/mips/kernel/ptrace.c
-1
arch/mips/kernel/ptrace.c
-1
arch/mips/kernel/ptrace32.c
-1
arch/mips/kernel/ptrace32.c
-1
arch/mips/kernel/rtlx.c
-1
arch/mips/kernel/rtlx.c
-1
arch/mips/kernel/setup.c
-1
arch/mips/kernel/setup.c
+1
arch/mips/kernel/signal.c
+1
arch/mips/kernel/signal.c
+1
-1
arch/mips/kernel/signal32.c
+1
-1
arch/mips/kernel/signal32.c
-1
arch/mips/kernel/signal_n32.c
-1
arch/mips/kernel/signal_n32.c
-1
arch/mips/kernel/smp-bmips.c
-1
arch/mips/kernel/smp-bmips.c
-1
arch/mips/kernel/smp-cmp.c
-1
arch/mips/kernel/smp-cmp.c
-1
arch/mips/kernel/smp-mt.c
-1
arch/mips/kernel/smp-mt.c
+1
-1
arch/mips/kernel/smp.c
+1
-1
arch/mips/kernel/smp.c
-1
arch/mips/kernel/smtc-proc.c
-1
arch/mips/kernel/smtc-proc.c
-1
arch/mips/kernel/smtc.c
-1
arch/mips/kernel/smtc.c
-1
arch/mips/kernel/spram.c
-1
arch/mips/kernel/spram.c
+1
arch/mips/kernel/syscall.c
+1
arch/mips/kernel/syscall.c
-1
arch/mips/kernel/traps.c
-1
arch/mips/kernel/traps.c
-1
arch/mips/kernel/unaligned.c
-1
arch/mips/kernel/unaligned.c
-1
arch/mips/kernel/vpe.c
-1
arch/mips/kernel/vpe.c
-1
arch/mips/lasat/reset.c
-1
arch/mips/lasat/reset.c
-1
arch/mips/math-emu/dsemul.c
-1
arch/mips/math-emu/dsemul.c
-1
arch/mips/mipssim/sim_smtc.c
-1
arch/mips/mipssim/sim_smtc.c
+1
arch/mips/mipssim/sim_time.c
+1
arch/mips/mipssim/sim_time.c
-1
arch/mips/mm/c-octeon.c
-1
arch/mips/mm/c-octeon.c
-1
arch/mips/mm/c-r3k.c
-1
arch/mips/mm/c-r3k.c
-1
arch/mips/mm/c-r4k.c
-1
arch/mips/mm/c-r4k.c
-1
arch/mips/mm/c-tx39.c
-1
arch/mips/mm/c-tx39.c
-1
arch/mips/mm/fault.c
-1
arch/mips/mm/fault.c
-1
arch/mips/mm/page.c
-1
arch/mips/mm/page.c
-1
arch/mips/mm/sc-ip22.c
-1
arch/mips/mm/sc-ip22.c
-1
arch/mips/mm/sc-mips.c
-1
arch/mips/mm/sc-mips.c
-1
arch/mips/mm/sc-r5k.c
-1
arch/mips/mm/sc-r5k.c
-1
arch/mips/mm/tlb-r3k.c
-1
arch/mips/mm/tlb-r3k.c
-1
arch/mips/mm/tlb-r4k.c
-1
arch/mips/mm/tlb-r4k.c
-1
arch/mips/mm/tlb-r8k.c
-1
arch/mips/mm/tlb-r8k.c
+1
arch/mips/mm/tlbex.c
+1
arch/mips/mm/tlbex.c
-1
arch/mips/mti-malta/malta-init.c
-1
arch/mips/mti-malta/malta-init.c
+1
arch/mips/mti-malta/malta-int.c
+1
arch/mips/mti-malta/malta-int.c
+1
arch/mips/mti-malta/malta-time.c
+1
arch/mips/mti-malta/malta-time.c
-1
arch/mips/netlogic/common/irq.c
-1
arch/mips/netlogic/common/irq.c
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
-1
arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
-1
arch/mips/pmc-sierra/yosemite/irq.c
-1
arch/mips/pmc-sierra/yosemite/irq.c
-1
arch/mips/pmc-sierra/yosemite/prom.c
-1
arch/mips/pmc-sierra/yosemite/prom.c
+1
arch/mips/pnx833x/common/interrupts.c
+1
arch/mips/pnx833x/common/interrupts.c
+1
arch/mips/powertv/asic/asic_int.c
+1
arch/mips/powertv/asic/asic_int.c
-1
arch/mips/powertv/asic/irq_asic.c
-1
arch/mips/powertv/asic/irq_asic.c
-1
arch/mips/powertv/init.c
-1
arch/mips/powertv/init.c
-1
arch/mips/rb532/irq.c
-1
arch/mips/rb532/irq.c
-1
arch/mips/sgi-ip22/ip22-berr.c
-1
arch/mips/sgi-ip22/ip22-berr.c
-1
arch/mips/sgi-ip22/ip22-reset.c
-1
arch/mips/sgi-ip22/ip22-reset.c
-1
arch/mips/sgi-ip22/ip28-berr.c
-1
arch/mips/sgi-ip22/ip28-berr.c
-1
arch/mips/sgi-ip27/ip27-irq.c
-1
arch/mips/sgi-ip27/ip27-irq.c
-1
arch/mips/sgi-ip27/ip27-reset.c
-1
arch/mips/sgi-ip27/ip27-reset.c
-1
arch/mips/sgi-ip32/ip32-irq.c
-1
arch/mips/sgi-ip32/ip32-irq.c
-1
arch/mips/sgi-ip32/ip32-reset.c
-1
arch/mips/sgi-ip32/ip32-reset.c
-1
arch/mips/sibyte/bcm1480/irq.c
-1
arch/mips/sibyte/bcm1480/irq.c
-1
arch/mips/sibyte/common/sb_tbprof.c
-1
arch/mips/sibyte/common/sb_tbprof.c
-1
arch/mips/sibyte/sb1250/bus_watcher.c
-1
arch/mips/sibyte/sb1250/bus_watcher.c
-1
arch/mips/sibyte/sb1250/irq.c
-1
arch/mips/sibyte/sb1250/irq.c
-1
arch/mips/sni/reset.c
-1
arch/mips/sni/reset.c
-1
arch/mips/vr41xx/common/irq.c
-1
arch/mips/vr41xx/common/irq.c