tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/tegra: Add code for booting RISC-V based engines
Add helper code for booting RISC-V based engines where firmware is
located in a carveout.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Mikko Perttunen
and committed by
Thierry Reding
b7dc179e
95ffcb4c
+138
-1
+2
-1
drivers/gpu/drm/tegra/Makefile
+2
-1
drivers/gpu/drm/tegra/Makefile
+106
drivers/gpu/drm/tegra/riscv.c
+106
drivers/gpu/drm/tegra/riscv.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022, NVIDIA Corporation.
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*/
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#include <linux/dev_printk.h>
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#include <linux/device.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include "riscv.h"
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#define RISCV_CPUCTL 0x4388
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#define RISCV_CPUCTL_STARTCPU_TRUE (1 << 0)
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#define RISCV_BR_RETCODE 0x465c
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#define RISCV_BR_RETCODE_RESULT_V(x) ((x) & 0x3)
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#define RISCV_BR_RETCODE_RESULT_PASS_V 3
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#define RISCV_BCR_CTRL 0x4668
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#define RISCV_BCR_CTRL_CORE_SELECT_RISCV (1 << 4)
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#define RISCV_BCR_DMACFG 0x466c
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#define RISCV_BCR_DMACFG_TARGET_LOCAL_FB (0 << 0)
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#define RISCV_BCR_DMACFG_LOCK_LOCKED (1 << 31)
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#define RISCV_BCR_DMAADDR_PKCPARAM_LO 0x4670
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#define RISCV_BCR_DMAADDR_PKCPARAM_HI 0x4674
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#define RISCV_BCR_DMAADDR_FMCCODE_LO 0x4678
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#define RISCV_BCR_DMAADDR_FMCCODE_HI 0x467c
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#define RISCV_BCR_DMAADDR_FMCDATA_LO 0x4680
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#define RISCV_BCR_DMAADDR_FMCDATA_HI 0x4684
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#define RISCV_BCR_DMACFG_SEC 0x4694
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#define RISCV_BCR_DMACFG_SEC_GSCID(v) ((v) << 16)
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static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset)
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{
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writel(value, riscv->regs + offset);
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}
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int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv)
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{
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struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc;
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struct tegra_drm_riscv_descriptor *os = &riscv->os_desc;
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const struct device_node *np = riscv->dev->of_node;
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int err;
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#define READ_PROP(name, location) \
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err = of_property_read_u32(np, name, location); \
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if (err) { \
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dev_err(riscv->dev, "failed to read " name ": %d\n", err); \
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return err; \
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}
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READ_PROP("nvidia,bl-manifest-offset", &bl->manifest_offset);
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READ_PROP("nvidia,bl-code-offset", &bl->code_offset);
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READ_PROP("nvidia,bl-data-offset", &bl->data_offset);
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READ_PROP("nvidia,os-manifest-offset", &os->manifest_offset);
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READ_PROP("nvidia,os-code-offset", &os->code_offset);
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READ_PROP("nvidia,os-data-offset", &os->data_offset);
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#undef READ_PROP
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if (bl->manifest_offset == 0 && bl->code_offset == 0 &&
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bl->data_offset == 0 && os->manifest_offset == 0 &&
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os->code_offset == 0 && os->data_offset == 0) {
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dev_err(riscv->dev, "descriptors not available\n");
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return -EINVAL;
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}
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return 0;
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}
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int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
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u32 gscid, const struct tegra_drm_riscv_descriptor *desc)
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{
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phys_addr_t addr;
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int err;
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u32 val;
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riscv_writel(riscv, RISCV_BCR_CTRL_CORE_SELECT_RISCV, RISCV_BCR_CTRL);
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addr = image_address + desc->manifest_offset;
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riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_PKCPARAM_LO);
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riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_PKCPARAM_HI);
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addr = image_address + desc->code_offset;
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riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCCODE_LO);
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riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCCODE_HI);
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addr = image_address + desc->data_offset;
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riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCDATA_LO);
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riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCDATA_HI);
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riscv_writel(riscv, RISCV_BCR_DMACFG_SEC_GSCID(gscid), RISCV_BCR_DMACFG_SEC);
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riscv_writel(riscv,
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RISCV_BCR_DMACFG_TARGET_LOCAL_FB | RISCV_BCR_DMACFG_LOCK_LOCKED, RISCV_BCR_DMACFG);
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riscv_writel(riscv, RISCV_CPUCTL_STARTCPU_TRUE, RISCV_CPUCTL);
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err = readl_poll_timeout(
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riscv->regs + RISCV_BR_RETCODE, val,
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RISCV_BR_RETCODE_RESULT_V(val) == RISCV_BR_RETCODE_RESULT_PASS_V,
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10, 100000);
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if (err) {
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dev_err(riscv->dev, "error during bootrom execution. BR_RETCODE=%d\n", val);
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return err;
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}
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return 0;
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}
+30
drivers/gpu/drm/tegra/riscv.h
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drivers/gpu/drm/tegra/riscv.h
···
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, NVIDIA Corporation.
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*/
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#ifndef DRM_TEGRA_RISCV_H
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#define DRM_TEGRA_RISCV_H
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struct tegra_drm_riscv_descriptor {
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u32 manifest_offset;
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u32 code_offset;
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u32 code_size;
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u32 data_offset;
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u32 data_size;
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};
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struct tegra_drm_riscv {
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/* User initializes */
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struct device *dev;
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void __iomem *regs;
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struct tegra_drm_riscv_descriptor bl_desc;
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struct tegra_drm_riscv_descriptor os_desc;
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};
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int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv);
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int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
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u32 gscid, const struct tegra_drm_riscv_descriptor *desc);
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#endif