···1894189418951895 (*) dma_wmb();18961896 (*) dma_rmb();18971897+ (*) dma_mb();1897189818981899 These are for use with consistent memory to guarantee the ordering18991900 of writes or reads of shared memory accessible to both the CPU and a···19261925 The dma_rmb() allows us guarantee the device has released ownership19271926 before we read the data from the descriptor, and the dma_wmb() allows19281927 us to guarantee the data is written to the descriptor before the device19291929- can see it now has ownership. Note that, when using writel(), a prior19301930- wmb() is not needed to guarantee that the cache coherent memory writes19311931- have completed before writing to the MMIO region. The cheaper19321932- writel_relaxed() does not provide this guarantee and must not be used19331933- here.19281928+ can see it now has ownership. The dma_mb() implies both a dma_rmb() and19291929+ a dma_wmb(). Note that, when using writel(), a prior wmb() is not needed19301930+ to guarantee that the cache coherent memory writes have completed before19311931+ writing to the MMIO region. The cheaper writel_relaxed() does not provide19321932+ this guarantee and must not be used here.1934193319351934 See the subsection "Kernel I/O barrier effects" for more information on19361935 relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for