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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: pxa2xx: Add support for Intel Broxton
LPSS SPI in Intel Broxton is otherwise the same than in Intel Sunrisepoint
but it supports up to four chip selects per port and has different FIFO
thresholds. Patch adds support for two Broxton SoC variants.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Jarkko Nikula
and committed by
Mark Brown
b7c08cf8
8b136baa
+21
+20
drivers/spi/spi-pxa2xx.c
+20
drivers/spi/spi-pxa2xx.c
···
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.tx_threshold_lo = 32,
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.tx_threshold_hi = 56,
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},
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+
{ /* LPSS_BXT_SSP */
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+
.offset = 0x200,
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+
.reg_general = -1,
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+
.reg_ssp = 0x20,
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+
.reg_cs_ctrl = 0x24,
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+
.reg_capabilities = 0xfc,
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+
.rx_threshold = 1,
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+
.tx_threshold_lo = 16,
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+
.tx_threshold_hi = 48,
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+
},
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};
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static inline const struct lpss_config
···
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case LPSS_LPT_SSP:
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case LPSS_BYT_SSP:
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case LPSS_SPT_SSP:
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+
case LPSS_BXT_SSP:
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return true;
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default:
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return false;
···
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case LPSS_LPT_SSP:
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case LPSS_BYT_SSP:
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case LPSS_SPT_SSP:
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+
case LPSS_BXT_SSP:
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config = lpss_get_config(drv_data);
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tx_thres = config->tx_threshold_lo;
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tx_hi_thres = config->tx_threshold_hi;
···
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/* SPT-H */
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{ PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
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{ PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
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+
/* BXT */
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+
{ PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
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+
{ PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
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+
{ PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
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+
/* APL */
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+
{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
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+
{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
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+
{ PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
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{ },
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};
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