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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
mips: bmips: dts: add BCM63268 reset controller support
BCM63268 SoCs have a reset controller for certain components.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
authored by
Álvaro Fernández Rojas
and committed by
Thomas Bogendoerfer
b7aa2288
7acf84e8
+32
+6
arch/mips/boot/dts/brcm/bcm63268.dtsi
+6
arch/mips/boot/dts/brcm/bcm63268.dtsi
···
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mask = <0x1>;
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};
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periph_rst: reset-controller@10000010 {
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compatible = "brcm,bcm6345-reset";
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reg = <0x10000010 0x4>;
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#reset-cells = <1>;
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};
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periph_intc: interrupt-controller@10000020 {
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compatible = "brcm,bcm6345-l1-intc";
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reg = <0x10000020 0x20>,
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include/dt-bindings/reset/bcm63268-reset.h
+26
include/dt-bindings/reset/bcm63268-reset.h
···
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __DT_BINDINGS_RESET_BCM63268_H
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#define __DT_BINDINGS_RESET_BCM63268_H
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#define BCM63268_RST_SPI 0
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#define BCM63268_RST_IPSEC 1
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#define BCM63268_RST_EPHY 2
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#define BCM63268_RST_SAR 3
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#define BCM63268_RST_ENETSW 4
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#define BCM63268_RST_USBS 5
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#define BCM63268_RST_USBH 6
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#define BCM63268_RST_PCM 7
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#define BCM63268_RST_PCIE_CORE 8
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#define BCM63268_RST_PCIE 9
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#define BCM63268_RST_PCIE_EXT 10
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#define BCM63268_RST_WLAN_SHIM 11
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#define BCM63268_RST_DDR_PHY 12
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#define BCM63268_RST_FAP0 13
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#define BCM63268_RST_WLAN_UBUS 14
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#define BCM63268_RST_DECT 15
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#define BCM63268_RST_FAP1 16
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#define BCM63268_RST_PCIE_HARD 17
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#define BCM63268_RST_GPHY 18
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#endif /* __DT_BINDINGS_RESET_BCM63268_H */