···13301330 */1331133113321332 if (usb_endpoint_xfer_control(&urb->ep->desc)) {13331333+ if (hcd->self.uses_pio_for_control)13341334+ return ret;13331335 if (hcd->self.uses_dma) {13341336 urb->setup_dma = dma_map_single(13351337 hcd->self.controller,
+3
drivers/usb/musb/musb_core.c
···21162116 * Otherwise, wait till the gadget driver hooks up.21172117 */21182118 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {21192119+ struct usb_hcd *hcd = musb_to_hcd(musb);21202120+21192121 MUSB_HST_MODE(musb);21202122 musb->xceiv->default_a = 1;21212123 musb->xceiv->state = OTG_STATE_A_IDLE;2122212421232125 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);2124212621272127+ hcd->self.uses_pio_for_control = 1;21252128 DBG(1, "%s mode, status %d, devctl %02x %c\n",21262129 "HOST", status,21272130 musb_readb(musb->mregs, MUSB_DEVCTL),
+86-38
drivers/usb/musb/musb_gadget.c
···92929393/* ----------------------------------------------------------------------- */94949595+/* Maps the buffer to dma */9696+9797+static inline void map_dma_buffer(struct musb_request *request,9898+ struct musb *musb)9999+{100100+ if (request->request.dma == DMA_ADDR_INVALID) {101101+ request->request.dma = dma_map_single(102102+ musb->controller,103103+ request->request.buf,104104+ request->request.length,105105+ request->tx106106+ ? DMA_TO_DEVICE107107+ : DMA_FROM_DEVICE);108108+ request->mapped = 1;109109+ } else {110110+ dma_sync_single_for_device(musb->controller,111111+ request->request.dma,112112+ request->request.length,113113+ request->tx114114+ ? DMA_TO_DEVICE115115+ : DMA_FROM_DEVICE);116116+ request->mapped = 0;117117+ }118118+}119119+120120+/* Unmap the buffer from dma and maps it back to cpu */121121+static inline void unmap_dma_buffer(struct musb_request *request,122122+ struct musb *musb)123123+{124124+ if (request->request.dma == DMA_ADDR_INVALID) {125125+ DBG(20, "not unmapping a never mapped buffer\n");126126+ return;127127+ }128128+ if (request->mapped) {129129+ dma_unmap_single(musb->controller,130130+ request->request.dma,131131+ request->request.length,132132+ request->tx133133+ ? DMA_TO_DEVICE134134+ : DMA_FROM_DEVICE);135135+ request->request.dma = DMA_ADDR_INVALID;136136+ request->mapped = 0;137137+ } else {138138+ dma_sync_single_for_cpu(musb->controller,139139+ request->request.dma,140140+ request->request.length,141141+ request->tx142142+ ? DMA_TO_DEVICE143143+ : DMA_FROM_DEVICE);144144+145145+ }146146+}147147+95148/*96149 * Immediately complete a request.97150 *···172119173120 ep->busy = 1;174121 spin_unlock(&musb->lock);175175- if (is_dma_capable()) {176176- if (req->mapped) {177177- dma_unmap_single(musb->controller,178178- req->request.dma,179179- req->request.length,180180- req->tx181181- ? DMA_TO_DEVICE182182- : DMA_FROM_DEVICE);183183- req->request.dma = DMA_ADDR_INVALID;184184- req->mapped = 0;185185- } else if (req->request.dma != DMA_ADDR_INVALID)186186- dma_sync_single_for_cpu(musb->controller,187187- req->request.dma,188188- req->request.length,189189- req->tx190190- ? DMA_TO_DEVICE191191- : DMA_FROM_DEVICE);192192- }122122+ if (is_dma_capable() && ep->dma)123123+ unmap_dma_buffer(req, musb);193124 if (request->status == 0)194125 DBG(5, "%s done request %p, %d/%d\n",195126 ep->end_point.name, request,···432395#endif433396434397 if (!use_dma) {398398+ /*399399+ * Unmap the dma buffer back to cpu if dma channel400400+ * programming fails401401+ */402402+ if (is_dma_capable() && musb_ep->dma)403403+ unmap_dma_buffer(req, musb);404404+435405 musb_write_fifo(musb_ep->hw_ep, fifo_count,436406 (u8 *) (request->buf + request->actual));437407 request->actual += fifo_count;···757713 return;758714 }759715#endif716716+ /*717717+ * Unmap the dma buffer back to cpu if dma channel718718+ * programming fails. This buffer is mapped if the719719+ * channel allocation is successful720720+ */721721+ if (is_dma_capable() && musb_ep->dma) {722722+ unmap_dma_buffer(req, musb);723723+724724+ /*725725+ * Clear DMAENAB and AUTOCLEAR for the726726+ * PIO mode transfer727727+ */728728+ csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);729729+ musb_writew(epio, MUSB_RXCSR, csr);730730+ }760731761732 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)762733 (request->buf + request->actual));···896837 if (!request)897838 return;898839 }840840+#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)899841exit:842842+#endif900843 /* Analyze request */901844 rxstate(musb, to_musb_request(request));902845}···12111150 request->epnum = musb_ep->current_epnum;12121151 request->tx = musb_ep->is_in;1213115212141214- if (is_dma_capable() && musb_ep->dma) {12151215- if (request->request.dma == DMA_ADDR_INVALID) {12161216- request->request.dma = dma_map_single(12171217- musb->controller,12181218- request->request.buf,12191219- request->request.length,12201220- request->tx12211221- ? DMA_TO_DEVICE12221222- : DMA_FROM_DEVICE);12231223- request->mapped = 1;12241224- } else {12251225- dma_sync_single_for_device(musb->controller,12261226- request->request.dma,12271227- request->request.length,12281228- request->tx12291229- ? DMA_TO_DEVICE12301230- : DMA_FROM_DEVICE);12311231- request->mapped = 0;12321232- }12331233- } else11531153+ if (is_dma_capable() && musb_ep->dma)11541154+ map_dma_buffer(request, musb);11551155+ else12341156 request->mapped = 0;1235115712361158 spin_lock_irqsave(&musb->lock, lockflags);···18331789 spin_unlock_irqrestore(&musb->lock, flags);1834179018351791 if (is_otg_enabled(musb)) {17921792+ struct usb_hcd *hcd = musb_to_hcd(musb);17931793+18361794 DBG(3, "OTG startup...\n");1837179518381796 /* REVISIT: funcall to other code, which also···18491803 musb->gadget_driver = NULL;18501804 musb->g.dev.driver = NULL;18511805 spin_unlock_irqrestore(&musb->lock, flags);18061806+ } else {18071807+ hcd->self.uses_pio_for_control = 1;18521808 }18531809 }18541810 }
+4
include/linux/usb.h
···313313 int busnum; /* Bus number (in order of reg) */314314 const char *bus_name; /* stable id (PCI slot_name etc) */315315 u8 uses_dma; /* Does the host controller use DMA? */316316+ u8 uses_pio_for_control; /*317317+ * Does the host controller use PIO318318+ * for control transfers?319319+ */316320 u8 otg_port; /* 0, or number of OTG/HNP port */317321 unsigned is_b_host:1; /* true during some HNP roleswitches */318322 unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */