Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ARM: integrator: define clocks in the device trees

This adds the clock definitions to the Integrator/CP
and Integrator/AP device trees.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

+135 -2
+35
arch/arm/boot/dts/integratorap.dts
··· 18 18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; 19 19 }; 20 20 21 + /* 24 MHz chrystal on the core module */ 22 + xtal24mhz: xtal24mhz@24M { 23 + #clock-cells = <0>; 24 + compatible = "fixed-clock"; 25 + clock-frequency = <24000000>; 26 + }; 27 + 28 + pclk: pclk@0 { 29 + #clock-cells = <0>; 30 + compatible = "fixed-factor-clock"; 31 + clock-div = <1>; 32 + clock-mult = <1>; 33 + clocks = <&xtal24mhz>; 34 + }; 35 + 36 + /* The UART clock is 14.74 MHz divided by an ICS525 */ 37 + uartclk: uartclk@14.74M { 38 + #clock-cells = <0>; 39 + compatible = "fixed-clock"; 40 + clock-frequency = <14745600>; 41 + }; 42 + 21 43 syscon { 22 44 compatible = "arm,integrator-ap-syscon"; 23 45 reg = <0x11000000 0x100>; ··· 50 28 51 29 timer0: timer@13000000 { 52 30 compatible = "arm,integrator-timer"; 31 + clocks = <&xtal24mhz>; 53 32 }; 54 33 55 34 timer1: timer@13000100 { 56 35 compatible = "arm,integrator-timer"; 36 + clocks = <&xtal24mhz>; 57 37 }; 58 38 59 39 timer2: timer@13000200 { 60 40 compatible = "arm,integrator-timer"; 41 + clocks = <&xtal24mhz>; 61 42 }; 62 43 63 44 pic: pic@14000000 { ··· 117 92 rtc: rtc@15000000 { 118 93 compatible = "arm,pl030", "arm,primecell"; 119 94 arm,primecell-periphid = <0x00041030>; 95 + clocks = <&pclk>; 96 + clock-names = "apb_pclk"; 120 97 }; 121 98 122 99 uart0: uart@16000000 { 123 100 compatible = "arm,pl010", "arm,primecell"; 124 101 arm,primecell-periphid = <0x00041010>; 102 + clocks = <&uartclk>, <&pclk>; 103 + clock-names = "uartclk", "apb_pclk"; 125 104 }; 126 105 127 106 uart1: uart@17000000 { 128 107 compatible = "arm,pl010", "arm,primecell"; 129 108 arm,primecell-periphid = <0x00041010>; 109 + clocks = <&uartclk>, <&pclk>; 110 + clock-names = "uartclk", "apb_pclk"; 130 111 }; 131 112 132 113 kmi0: kmi@18000000 { 133 114 compatible = "arm,pl050", "arm,primecell"; 134 115 arm,primecell-periphid = <0x00041050>; 116 + clocks = <&xtal24mhz>, <&pclk>; 117 + clock-names = "KMIREFCLK", "apb_pclk"; 135 118 }; 136 119 137 120 kmi1: kmi@19000000 { 138 121 compatible = "arm,pl050", "arm,primecell"; 139 122 arm,primecell-periphid = <0x00041050>; 123 + clocks = <&xtal24mhz>, <&pclk>; 124 + clock-names = "KMIREFCLK", "apb_pclk"; 140 125 }; 141 126 }; 142 127 };
+100 -2
arch/arm/boot/dts/integratorcp.dts
··· 13 13 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; 14 14 }; 15 15 16 + /* 17 + * The Integrator/CP overall clocking architecture can be found in 18 + * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which 19 + * appear to illustrate the layout used in most configurations. 20 + */ 21 + 22 + /* The codec chrystal operates at 24.576 MHz */ 23 + xtal_codec: xtal24.576@24.576M { 24 + #clock-cells = <0>; 25 + compatible = "fixed-clock"; 26 + clock-frequency = <24576000>; 27 + }; 28 + 29 + /* The chrystal is divided by 2 by the codec for the AACI bit clock */ 30 + aaci_bitclk: aaci_bitclk@12.288M { 31 + #clock-cells = <0>; 32 + compatible = "fixed-factor-clock"; 33 + clock-div = <2>; 34 + clock-mult = <1>; 35 + clocks = <&xtal_codec>; 36 + }; 37 + 38 + /* This is a 25MHz chrystal on the base board */ 39 + xtal25mhz: xtal25mhz@25M { 40 + #clock-cells = <0>; 41 + compatible = "fixed-clock"; 42 + clock-frequency = <25000000>; 43 + }; 44 + 45 + /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ 46 + uartclk: uartclk@14.74M { 47 + #clock-cells = <0>; 48 + compatible = "fixed-clock"; 49 + clock-frequency = <14745600>; 50 + }; 51 + 52 + /* Actually sysclk I think */ 53 + pclk: pclk@0 { 54 + #clock-cells = <0>; 55 + compatible = "fixed-clock"; 56 + clock-frequency = <0>; 57 + }; 58 + 59 + core-module@10000000 { 60 + /* 24 MHz chrystal on the core module */ 61 + xtal24mhz: xtal24mhz@24M { 62 + #clock-cells = <0>; 63 + compatible = "fixed-clock"; 64 + clock-frequency = <24000000>; 65 + }; 66 + 67 + /* 68 + * External oscillator on the core module, usually used 69 + * to drive video circuitry. Driven from the 24MHz clock. 70 + */ 71 + auxosc: cm_aux_osc@25M { 72 + #clock-cells = <0>; 73 + compatible = "arm,integrator-cm-auxosc"; 74 + clocks = <&xtal24mhz>; 75 + }; 76 + 77 + /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ 78 + kmiclk: kmiclk@1M { 79 + #clock-cells = <0>; 80 + compatible = "fixed-factor-clock"; 81 + clock-div = <3>; 82 + clock-mult = <1>; 83 + clocks = <&xtal24mhz>; 84 + }; 85 + 86 + /* The timer clock is the 24 MHz oscillator divided to 1MHz */ 87 + timclk: timclk@1M { 88 + #clock-cells = <0>; 89 + compatible = "fixed-factor-clock"; 90 + clock-div = <24>; 91 + clock-mult = <1>; 92 + clocks = <&xtal24mhz>; 93 + }; 94 + }; 95 + 16 96 syscon { 17 97 compatible = "arm,integrator-cp-syscon"; 18 98 reg = <0xcb000000 0x100>; 19 99 }; 20 100 21 101 timer0: timer@13000000 { 22 - /* TIMER0 runs @ 25MHz */ 102 + /* TIMER0 runs directly on the 25MHz chrystal */ 23 103 compatible = "arm,integrator-cp-timer"; 24 - status = "disabled"; 104 + clocks = <&xtal25mhz>; 25 105 }; 26 106 27 107 timer1: timer@13000100 { 28 108 /* TIMER1 runs @ 1MHz */ 29 109 compatible = "arm,integrator-cp-timer"; 110 + clocks = <&timclk>; 30 111 }; 31 112 32 113 timer2: timer@13000200 { 33 114 /* TIMER2 runs @ 1MHz */ 34 115 compatible = "arm,integrator-cp-timer"; 116 + clocks = <&timclk>; 35 117 }; 36 118 37 119 pic: pic@14000000 { ··· 156 74 */ 157 75 rtc@15000000 { 158 76 compatible = "arm,pl031", "arm,primecell"; 77 + clocks = <&pclk>; 78 + clock-names = "apb_pclk"; 159 79 }; 160 80 161 81 uart@16000000 { 162 82 compatible = "arm,pl011", "arm,primecell"; 83 + clocks = <&uartclk>, <&pclk>; 84 + clock-names = "uartclk", "apb_pclk"; 163 85 }; 164 86 165 87 uart@17000000 { 166 88 compatible = "arm,pl011", "arm,primecell"; 89 + clocks = <&uartclk>, <&pclk>; 90 + clock-names = "uartclk", "apb_pclk"; 167 91 }; 168 92 169 93 kmi@18000000 { 170 94 compatible = "arm,pl050", "arm,primecell"; 95 + clocks = <&kmiclk>, <&pclk>; 96 + clock-names = "KMIREFCLK", "apb_pclk"; 171 97 }; 172 98 173 99 kmi@19000000 { 174 100 compatible = "arm,pl050", "arm,primecell"; 101 + clocks = <&kmiclk>, <&pclk>; 102 + clock-names = "KMIREFCLK", "apb_pclk"; 175 103 }; 176 104 177 105 /* ··· 192 100 reg = <0x1c000000 0x1000>; 193 101 interrupts = <23 24>; 194 102 max-frequency = <515633>; 103 + clocks = <&uartclk>, <&pclk>; 104 + clock-names = "mclk", "apb_pclk"; 195 105 }; 196 106 197 107 aaci@1d000000 { 198 108 compatible = "arm,pl041", "arm,primecell"; 199 109 reg = <0x1d000000 0x1000>; 200 110 interrupts = <25>; 111 + clocks = <&pclk>; 112 + clock-names = "apb_pclk"; 201 113 }; 202 114 203 115 clcd@c0000000 { 204 116 compatible = "arm,pl110", "arm,primecell"; 205 117 reg = <0xC0000000 0x1000>; 206 118 interrupts = <22>; 119 + clocks = <&auxosc>, <&pclk>; 120 + clock-names = "clcd", "apb_pclk"; 207 121 }; 208 122 }; 209 123 };