tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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arm: dts: lpc32xx: assign interrupt types

LPC32xx interrupt controller has two cells, instead of zero
specify proper irq types for all consumers.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

Vladimir Zapolskiy b715802f c82e688a

+34 -29
+34 -29
arch/arm/boot/dts/lpc32xx.dtsi
··· 14 14 #include "skeleton.dtsi" 15 15 16 16 #include <dt-bindings/clock/lpc32xx-clock.h> 17 + #include <dt-bindings/interrupt-controller/irq.h> 17 18 18 19 / { 19 20 compatible = "nxp,lpc3220"; ··· 67 66 mlc: flash@200a8000 { 68 67 compatible = "nxp,lpc3220-mlc"; 69 68 reg = <0x200a8000 0x11000>; 70 - interrupts = <11 0>; 69 + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 71 70 clocks = <&clk LPC32XX_CLK_MLC>; 72 71 status = "disabled"; 73 72 }; ··· 75 74 dma: dma@31000000 { 76 75 compatible = "arm,pl080", "arm,primecell"; 77 76 reg = <0x31000000 0x1000>; 78 - interrupts = <0x1c 0>; 77 + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 79 78 clocks = <&clk LPC32XX_CLK_DMA>; 80 79 clock-names = "apb_pclk"; 81 80 }; ··· 92 91 ohci: ohci@0 { 93 92 compatible = "nxp,ohci-nxp", "usb-ohci"; 94 93 reg = <0x0 0x300>; 95 - interrupts = <0x3b 0>; 94 + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 96 95 clocks = <&usbclk LPC32XX_USB_CLK_HOST>; 97 96 status = "disabled"; 98 97 }; ··· 100 99 usbd: usbd@0 { 101 100 compatible = "nxp,lpc3220-udc"; 102 101 reg = <0x0 0x300>; 103 - interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; 102 + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>, 103 + <62 IRQ_TYPE_LEVEL_HIGH>, 104 + <60 IRQ_TYPE_LEVEL_HIGH>, 105 + <58 IRQ_TYPE_LEVEL_LOW>; 104 106 clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; 105 107 status = "disabled"; 106 108 }; ··· 111 107 i2cusb: i2c@300 { 112 108 compatible = "nxp,pnx-i2c"; 113 109 reg = <0x300 0x100>; 114 - interrupts = <0x3f 0>; 110 + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; 115 111 clocks = <&usbclk LPC32XX_USB_CLK_I2C>; 116 112 #address-cells = <1>; 117 113 #size-cells = <0>; ··· 128 124 clcd: clcd@31040000 { 129 125 compatible = "arm,pl110", "arm,primecell"; 130 126 reg = <0x31040000 0x1000>; 131 - interrupts = <0x0e 0>; 127 + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 132 128 clocks = <&clk LPC32XX_CLK_LCD>; 133 129 clock-names = "apb_pclk"; 134 130 status = "disabled"; ··· 137 133 mac: ethernet@31060000 { 138 134 compatible = "nxp,lpc-eth"; 139 135 reg = <0x31060000 0x1000>; 140 - interrupts = <0x1d 0>; 136 + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 141 137 clocks = <&clk LPC32XX_CLK_MAC>; 142 138 }; 143 139 ··· 165 161 ssp0: ssp@20084000 { 166 162 compatible = "arm,pl022", "arm,primecell"; 167 163 reg = <0x20084000 0x1000>; 168 - interrupts = <0x14 0>; 164 + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 169 165 clocks = <&clk LPC32XX_CLK_SSP0>; 170 166 clock-names = "apb_pclk"; 171 167 }; ··· 178 174 ssp1: ssp@2008c000 { 179 175 compatible = "arm,pl022", "arm,primecell"; 180 176 reg = <0x2008c000 0x1000>; 181 - interrupts = <0x15 0>; 177 + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 182 178 clocks = <&clk LPC32XX_CLK_SSP1>; 183 179 clock-names = "apb_pclk"; 184 180 }; ··· 196 192 sd: sd@20098000 { 197 193 compatible = "arm,pl18x", "arm,primecell"; 198 194 reg = <0x20098000 0x1000>; 199 - interrupts = <0x0f 0>, <0x0d 0>; 195 + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, 196 + <13 IRQ_TYPE_LEVEL_HIGH>; 200 197 clocks = <&clk LPC32XX_CLK_SD>; 201 198 clock-names = "apb_pclk"; 202 199 status = "disabled"; ··· 213 208 /* actually, ns16550a w/ 64 byte fifos! */ 214 209 compatible = "nxp,lpc3220-uart"; 215 210 reg = <0x40090000 0x1000>; 216 - interrupts = <9 0>; 211 + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 217 212 reg-shift = <2>; 218 213 clocks = <&clk LPC32XX_CLK_UART5>; 219 214 status = "disabled"; ··· 222 217 uart3: serial@40080000 { 223 218 compatible = "nxp,lpc3220-uart"; 224 219 reg = <0x40080000 0x1000>; 225 - interrupts = <7 0>; 220 + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 226 221 reg-shift = <2>; 227 222 clocks = <&clk LPC32XX_CLK_UART3>; 228 223 status = "disabled"; ··· 231 226 uart4: serial@40088000 { 232 227 compatible = "nxp,lpc3220-uart"; 233 228 reg = <0x40088000 0x1000>; 234 - interrupts = <8 0>; 229 + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 235 230 reg-shift = <2>; 236 231 clocks = <&clk LPC32XX_CLK_UART4>; 237 232 status = "disabled"; ··· 240 235 uart6: serial@40098000 { 241 236 compatible = "nxp,lpc3220-uart"; 242 237 reg = <0x40098000 0x1000>; 243 - interrupts = <10 0>; 238 + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 244 239 reg-shift = <2>; 245 240 clocks = <&clk LPC32XX_CLK_UART6>; 246 241 status = "disabled"; ··· 249 244 i2c1: i2c@400A0000 { 250 245 compatible = "nxp,pnx-i2c"; 251 246 reg = <0x400A0000 0x100>; 252 - interrupts = <0x33 0>; 247 + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 253 248 #address-cells = <1>; 254 249 #size-cells = <0>; 255 250 pnx,timeout = <0x64>; ··· 259 254 i2c2: i2c@400A8000 { 260 255 compatible = "nxp,pnx-i2c"; 261 256 reg = <0x400A8000 0x100>; 262 - interrupts = <0x32 0>; 257 + interrupts = <50 IRQ_TYPE_LEVEL_LOW>; 263 258 #address-cells = <1>; 264 259 #size-cells = <0>; 265 260 pnx,timeout = <0x64>; ··· 313 308 uart1: serial@40014000 { 314 309 compatible = "nxp,lpc3220-hsuart"; 315 310 reg = <0x40014000 0x1000>; 316 - interrupts = <26 0>; 311 + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; 317 312 status = "disabled"; 318 313 }; 319 314 320 315 uart2: serial@40018000 { 321 316 compatible = "nxp,lpc3220-hsuart"; 322 317 reg = <0x40018000 0x1000>; 323 - interrupts = <25 0>; 318 + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; 324 319 status = "disabled"; 325 320 }; 326 321 327 322 uart7: serial@4001c000 { 328 323 compatible = "nxp,lpc3220-hsuart"; 329 324 reg = <0x4001c000 0x1000>; 330 - interrupts = <24 0>; 325 + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 331 326 status = "disabled"; 332 327 }; 333 328 334 329 rtc: rtc@40024000 { 335 330 compatible = "nxp,lpc3220-rtc"; 336 331 reg = <0x40024000 0x1000>; 337 - interrupts = <0x34 0>; 332 + interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; 338 333 clocks = <&clk LPC32XX_CLK_RTC>; 339 334 }; 340 335 ··· 348 343 timer4: timer@4002C000 { 349 344 compatible = "nxp,lpc3220-timer"; 350 345 reg = <0x4002C000 0x1000>; 351 - interrupts = <0x3 0>; 346 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 352 347 clocks = <&clk LPC32XX_CLK_TIMER4>; 353 348 clock-names = "timerclk"; 354 349 status = "disabled"; ··· 357 352 timer5: timer@40030000 { 358 353 compatible = "nxp,lpc3220-timer"; 359 354 reg = <0x40030000 0x1000>; 360 - interrupts = <0x4 0>; 355 + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 361 356 clocks = <&clk LPC32XX_CLK_TIMER5>; 362 357 clock-names = "timerclk"; 363 358 status = "disabled"; ··· 374 369 reg = <0x40044000 0x1000>; 375 370 clocks = <&clk LPC32XX_CLK_TIMER0>; 376 371 clock-names = "timerclk"; 377 - interrupts = <0x10 0>; 372 + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 378 373 }; 379 374 380 375 /* ··· 387 382 adc: adc@40048000 { 388 383 compatible = "nxp,lpc3220-adc"; 389 384 reg = <0x40048000 0x1000>; 390 - interrupts = <0x27 0>; 385 + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 391 386 clocks = <&clk LPC32XX_CLK_ADC>; 392 387 status = "disabled"; 393 388 }; ··· 395 390 tsc: tsc@40048000 { 396 391 compatible = "nxp,lpc3220-tsc"; 397 392 reg = <0x40048000 0x1000>; 398 - interrupts = <0x27 0>; 393 + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 399 394 clocks = <&clk LPC32XX_CLK_ADC>; 400 395 status = "disabled"; 401 396 }; ··· 403 398 timer1: timer@4004C000 { 404 399 compatible = "nxp,lpc3220-timer"; 405 400 reg = <0x4004C000 0x1000>; 406 - interrupts = <0x11 0>; 401 + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 407 402 clocks = <&clk LPC32XX_CLK_TIMER1>; 408 403 clock-names = "timerclk"; 409 404 }; ··· 411 406 key: key@40050000 { 412 407 compatible = "nxp,lpc3220-key"; 413 408 reg = <0x40050000 0x1000>; 414 - interrupts = <54 0>; 409 + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 415 410 status = "disabled"; 416 411 }; 417 412 418 413 timer2: timer@40058000 { 419 414 compatible = "nxp,lpc3220-timer"; 420 415 reg = <0x40058000 0x1000>; 421 - interrupts = <0x12 0>; 416 + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 422 417 clocks = <&clk LPC32XX_CLK_TIMER2>; 423 418 clock-names = "timerclk"; 424 419 status = "disabled"; ··· 441 436 timer3: timer@40060000 { 442 437 compatible = "nxp,lpc3220-timer"; 443 438 reg = <0x40060000 0x1000>; 444 - interrupts = <0x13 0>; 439 + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 445 440 clocks = <&clk LPC32XX_CLK_TIMER3>; 446 441 clock-names = "timerclk"; 447 442 status = "disabled";