+3
-1
drivers/pinctrl/pinctrl-microchip-sgpio.c
+3
-1
drivers/pinctrl/pinctrl-microchip-sgpio.c
···
845
845
i = 0;
846
846
device_for_each_child_node(dev, fwnode) {
847
847
ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
848
-
if (ret)
848
+
if (ret) {
849
+
fwnode_handle_put(fwnode);
849
850
return ret;
851
+
}
850
852
}
851
853
852
854
if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
+7
-2
drivers/pinctrl/stm32/pinctrl-stm32.c
+7
-2
drivers/pinctrl/stm32/pinctrl-stm32.c
···
1224
1224
struct device *dev = pctl->dev;
1225
1225
struct resource res;
1226
1226
int npins = STM32_GPIO_PINS_PER_BANK;
1227
-
int bank_nr, err;
1227
+
int bank_nr, err, i = 0;
1228
1228
1229
1229
if (!IS_ERR(bank->rstc))
1230
1230
reset_control_deassert(bank->rstc);
···
1246
1246
1247
1247
of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1248
1248
1249
-
if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
1249
+
if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
1250
1250
bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1251
1251
bank->gpio_chip.base = args.args[1];
1252
+
1253
+
npins = args.args[2];
1254
+
while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
1255
+
++i, &args))
1256
+
npins += args.args[2];
1252
1257
} else {
1253
1258
bank_nr = pctl->nbanks;
1254
1259
bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;