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MIPS: Netlogic: Avoid unnecessary cache flushes
XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache
flushes.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2729/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
Jayachandran C
and committed by
Ralf Baechle
b66f953c
11d48aac
+2
-3
+2
-3
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+2
-3
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
···
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#define cpu_has_llsc 1
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#define cpu_has_vtag_icache 0
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#define cpu_has_dc_aliases 0
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-
#define cpu_has_ic_fills_f_dc 0
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+
#define cpu_has_ic_fills_f_dc 1
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#define cpu_has_dsp 0
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#define cpu_has_mipsmt 0
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#define cpu_has_userlocal 0
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-
#define cpu_icache_snoops_remote_store 0
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+
#define cpu_icache_snoops_remote_store 1
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-
#define cpu_has_nofpuex 0
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#define cpu_has_64bits 1
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#define cpu_has_mips32r1 1