···769769 /*770770 * acquire the CPU spinlocks771771 */772772- for (i = num_online_cpus()-1; i >= 0; i--)772772+ for_each_online_cpu(i)773773 if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0)774774 panic("kgdb: couldn't get cpulock %d\n", i);775775···1044104410451045exit_kgdb_exception:10461046 /* release locks so other CPUs can go */10471047- for (i = num_online_cpus()-1; i >= 0; i--)10471047+ for_each_online_cpu(i)10481048 __raw_spin_unlock(&kgdb_cpulock[i]);10491049 spin_unlock(&kgdb_lock);10501050
+21-12
arch/mips/kernel/smp.c
···375375 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {376376 smp_on_other_tlbs(flush_tlb_mm_ipi, (void *)mm);377377 } else {378378- int i;379379- for (i = 0; i < num_online_cpus(); i++)380380- if (smp_processor_id() != i)381381- cpu_context(i, mm) = 0;378378+ cpumask_t mask = cpu_online_map;379379+ unsigned int cpu;380380+381381+ cpu_clear(smp_processor_id(), mask);382382+ for_each_online_cpu(cpu)383383+ if (cpu_context(cpu, mm))384384+ cpu_context(cpu, mm) = 0;382385 }383386 local_flush_tlb_mm(mm);384387···414411 fd.addr2 = end;415412 smp_on_other_tlbs(flush_tlb_range_ipi, (void *)&fd);416413 } else {417417- int i;418418- for (i = 0; i < num_online_cpus(); i++)419419- if (smp_processor_id() != i)420420- cpu_context(i, mm) = 0;414414+ cpumask_t mask = cpu_online_map;415415+ unsigned int cpu;416416+417417+ cpu_clear(smp_processor_id(), mask);418418+ for_each_online_cpu(cpu)419419+ if (cpu_context(cpu, mm))420420+ cpu_context(cpu, mm) = 0;421421 }422422 local_flush_tlb_range(vma, start, end);423423 preempt_enable();···459453 fd.addr1 = page;460454 smp_on_other_tlbs(flush_tlb_page_ipi, (void *)&fd);461455 } else {462462- int i;463463- for (i = 0; i < num_online_cpus(); i++)464464- if (smp_processor_id() != i)465465- cpu_context(i, vma->vm_mm) = 0;456456+ cpumask_t mask = cpu_online_map;457457+ unsigned int cpu;458458+459459+ cpu_clear(smp_processor_id(), mask);460460+ for_each_online_cpu(cpu)461461+ if (cpu_context(cpu, vma->vm_mm))462462+ cpu_context(cpu, vma->vm_mm) = 0;466463 }467464 local_flush_tlb_page(vma, page);468465 preempt_enable();
+2-2
arch/mips/kernel/smtc.c
···12641264 if (cpu_has_vtag_icache)12651265 flush_icache_all();12661266 /* Traverse all online CPUs (hack requires contigous range) */12671267- for (i = 0; i < num_online_cpus(); i++) {12671267+ for_each_online_cpu(i) {12681268 /*12691269 * We don't need to worry about our own CPU, nor those of12701270 * CPUs who don't share our TLB.···12931293 /*12941294 * SMTC shares the TLB within VPEs and possibly across all VPEs.12951295 */12961296- for (i = 0; i < num_online_cpus(); i++) {12961296+ for_each_online_cpu(i) {12971297 if ((smtc_status & SMTC_TLB_SHARED) ||12981298 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))12991299 cpu_context(i, mm) = asid_cache(i) = asid;
+2-2
include/asm-mips/mmu_context.h
···120120{121121 int i;122122123123- for (i = 0; i < num_online_cpus(); i++)123123+ for_each_online_cpu(i)124124 cpu_context(i, mm) = 0;125125126126 return 0;···284284 int i;285285286286 /* SMTC shares the TLB (and ASIDs) across VPEs */287287- for (i = 0; i < num_online_cpus(); i++) {287287+ for_each_online_cpu(i) {288288 if((smtc_status & SMTC_TLB_SHARED)289289 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))290290 cpu_context(i, mm) = 0;