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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: mm: scache: Add secondary cache support for MIPS R6 cores
The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
+4
-2
+2
-1
arch/mips/mm/c-r4k.c
+2
-1
arch/mips/mm/c-r4k.c
···
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1473
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default:
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1476
-
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1476
+
MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1477
+
MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
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#ifdef CONFIG_MIPS_CPU_SCACHE
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if (mips_sc_init ()) {
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scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+2
-1
arch/mips/mm/sc-mips.c
+2
-1
arch/mips/mm/sc-mips.c
···
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/* Ignore anything but MIPSxx processors */
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if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
108
-
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
108
+
MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
109
+
MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)))
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return 0;
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/* Does this MIPS32/MIPS64 CPU have a config2 register? */