Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

net: mscc: ocelot: Add support for tcam

Add ACL support using the TCAM. Using ACL it is possible to create rules
in hardware to filter/redirect frames.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Horatiu Vultur and committed by
David S. Miller
b5962294 6345266a

+1508 -3
+3 -2
arch/mips/boot/dts/mscc/ocelot.dtsi
··· 132 132 <0x1270000 0x100>, 133 133 <0x1280000 0x100>, 134 134 <0x1800000 0x80000>, 135 - <0x1880000 0x10000>; 135 + <0x1880000 0x10000>, 136 + <0x1060000 0x10000>; 136 137 reg-names = "sys", "rew", "qs", "port0", "port1", 137 138 "port2", "port3", "port4", "port5", "port6", 138 139 "port7", "port8", "port9", "port10", "qsys", 139 - "ana"; 140 + "ana", "s2"; 140 141 interrupts = <21 22>; 141 142 interrupt-names = "xtr", "inj"; 142 143
+1 -1
drivers/net/ethernet/mscc/Makefile
··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 2 obj-$(CONFIG_MSCC_OCELOT_SWITCH) += mscc_ocelot_common.o 3 3 mscc_ocelot_common-y := ocelot.o ocelot_io.o 4 - mscc_ocelot_common-y += ocelot_regs.o ocelot_tc.o ocelot_police.o 4 + mscc_ocelot_common-y += ocelot_regs.o ocelot_tc.o ocelot_police.o ocelot_ace.o 5 5 obj-$(CONFIG_MSCC_OCELOT_SWITCH_OCELOT) += ocelot_board.o
+13
drivers/net/ethernet/mscc/ocelot.c
··· 22 22 #include <net/switchdev.h> 23 23 24 24 #include "ocelot.h" 25 + #include "ocelot_ace.h" 25 26 26 27 #define TABLE_UPDATE_SLEEP_US 10 27 28 #define TABLE_UPDATE_TIMEOUT_US 100000 ··· 129 128 130 129 /* Clear the MAC table */ 131 130 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 131 + } 132 + 133 + static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port) 134 + { 135 + ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 136 + ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 137 + ANA_PORT_VCAP_S2_CFG, port->chip_port); 132 138 } 133 139 134 140 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) ··· 1670 1662 /* Basic L2 initialization */ 1671 1663 ocelot_vlan_port_apply(ocelot, ocelot_port); 1672 1664 1665 + /* Enable vcap lookups */ 1666 + ocelot_vcap_enable(ocelot, ocelot_port); 1667 + 1673 1668 return 0; 1674 1669 1675 1670 err_register_netdev: ··· 1707 1696 1708 1697 ocelot_mact_init(ocelot); 1709 1698 ocelot_vlan_init(ocelot); 1699 + ocelot_ace_init(ocelot); 1710 1700 1711 1701 for (port = 0; port < ocelot->num_phys_ports; port++) { 1712 1702 /* Clear all counters (5 groups) */ ··· 1820 1808 { 1821 1809 destroy_workqueue(ocelot->stats_queue); 1822 1810 mutex_destroy(&ocelot->stats_lock); 1811 + ocelot_ace_deinit(); 1823 1812 } 1824 1813 EXPORT_SYMBOL(ocelot_deinit); 1825 1814
+8
drivers/net/ethernet/mscc/ocelot.h
··· 69 69 QSYS, 70 70 REW, 71 71 SYS, 72 + S2, 72 73 HSIO, 73 74 TARGET_MAX, 74 75 }; ··· 336 335 SYS_CM_DATA_RD, 337 336 SYS_CM_OP, 338 337 SYS_CM_DATA, 338 + S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET, 339 + S2_CORE_MV_CFG, 340 + S2_CACHE_ENTRY_DAT, 341 + S2_CACHE_MASK_DAT, 342 + S2_CACHE_ACTION_DAT, 343 + S2_CACHE_CNT_DAT, 344 + S2_CACHE_TG_DAT, 339 345 }; 340 346 341 347 enum ocelot_regfield {
+777
drivers/net/ethernet/mscc/ocelot_ace.c
··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* Microsemi Ocelot Switch driver 3 + * Copyright (c) 2019 Microsemi Corporation 4 + */ 5 + 6 + #include <linux/iopoll.h> 7 + #include <linux/proc_fs.h> 8 + 9 + #include "ocelot_ace.h" 10 + #include "ocelot_vcap.h" 11 + #include "ocelot_s2.h" 12 + 13 + #define OCELOT_POLICER_DISCARD 0x17f 14 + 15 + static struct ocelot_acl_block *acl_block; 16 + 17 + struct vcap_props { 18 + const char *name; /* Symbolic name */ 19 + u16 tg_width; /* Type-group width (in bits) */ 20 + u16 sw_count; /* Sub word count */ 21 + u16 entry_count; /* Entry count */ 22 + u16 entry_words; /* Number of entry words */ 23 + u16 entry_width; /* Entry width (in bits) */ 24 + u16 action_count; /* Action count */ 25 + u16 action_words; /* Number of action words */ 26 + u16 action_width; /* Action width (in bits) */ 27 + u16 action_type_width; /* Action type width (in bits) */ 28 + struct { 29 + u16 width; /* Action type width (in bits) */ 30 + u16 count; /* Action type sub word count */ 31 + } action_table[2]; 32 + u16 counter_words; /* Number of counter words */ 33 + u16 counter_width; /* Counter width (in bits) */ 34 + }; 35 + 36 + #define ENTRY_WIDTH 32 37 + #define BITS_TO_32BIT(x) (1 + (((x) - 1) / ENTRY_WIDTH)) 38 + 39 + static const struct vcap_props vcap_is2 = { 40 + .name = "IS2", 41 + .tg_width = 2, 42 + .sw_count = 4, 43 + .entry_count = VCAP_IS2_CNT, 44 + .entry_words = BITS_TO_32BIT(VCAP_IS2_ENTRY_WIDTH), 45 + .entry_width = VCAP_IS2_ENTRY_WIDTH, 46 + .action_count = (VCAP_IS2_CNT + VCAP_PORT_CNT + 2), 47 + .action_words = BITS_TO_32BIT(VCAP_IS2_ACTION_WIDTH), 48 + .action_width = (VCAP_IS2_ACTION_WIDTH), 49 + .action_type_width = 1, 50 + .action_table = { 51 + { 52 + .width = (IS2_AO_ACL_ID + IS2_AL_ACL_ID), 53 + .count = 2 54 + }, 55 + { 56 + .width = 6, 57 + .count = 4 58 + }, 59 + }, 60 + .counter_words = BITS_TO_32BIT(4 * ENTRY_WIDTH), 61 + .counter_width = ENTRY_WIDTH, 62 + }; 63 + 64 + enum vcap_sel { 65 + VCAP_SEL_ENTRY = 0x1, 66 + VCAP_SEL_ACTION = 0x2, 67 + VCAP_SEL_COUNTER = 0x4, 68 + VCAP_SEL_ALL = 0x7, 69 + }; 70 + 71 + enum vcap_cmd { 72 + VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */ 73 + VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */ 74 + VCAP_CMD_MOVE_UP = 2, /* Move <count> up */ 75 + VCAP_CMD_MOVE_DOWN = 3, /* Move <count> down */ 76 + VCAP_CMD_INITIALIZE = 4, /* Write all (from cache) */ 77 + }; 78 + 79 + #define VCAP_ENTRY_WIDTH 12 /* Max entry width (32bit words) */ 80 + #define VCAP_COUNTER_WIDTH 4 /* Max counter width (32bit words) */ 81 + 82 + struct vcap_data { 83 + u32 entry[VCAP_ENTRY_WIDTH]; /* ENTRY_DAT */ 84 + u32 mask[VCAP_ENTRY_WIDTH]; /* MASK_DAT */ 85 + u32 action[VCAP_ENTRY_WIDTH]; /* ACTION_DAT */ 86 + u32 counter[VCAP_COUNTER_WIDTH]; /* CNT_DAT */ 87 + u32 tg; /* TG_DAT */ 88 + u32 type; /* Action type */ 89 + u32 tg_sw; /* Current type-group */ 90 + u32 cnt; /* Current counter */ 91 + u32 key_offset; /* Current entry offset */ 92 + u32 action_offset; /* Current action offset */ 93 + u32 counter_offset; /* Current counter offset */ 94 + u32 tg_value; /* Current type-group value */ 95 + u32 tg_mask; /* Current type-group mask */ 96 + } vcap_data_t; 97 + 98 + static u32 vcap_s2_read_update_ctrl(struct ocelot *oc) 99 + { 100 + return ocelot_read(oc, S2_CORE_UPDATE_CTRL); 101 + } 102 + 103 + static void vcap_cmd(struct ocelot *oc, u16 ix, int cmd, int sel) 104 + { 105 + u32 value = (S2_CORE_UPDATE_CTRL_UPDATE_CMD(cmd) | 106 + S2_CORE_UPDATE_CTRL_UPDATE_ADDR(ix) | 107 + S2_CORE_UPDATE_CTRL_UPDATE_SHOT); 108 + int rc; 109 + 110 + if ((sel & VCAP_SEL_ENTRY) && ix >= vcap_is2.entry_count) 111 + return; 112 + 113 + if (!(sel & VCAP_SEL_ENTRY)) 114 + value |= S2_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS; 115 + 116 + if (!(sel & VCAP_SEL_ACTION)) 117 + value |= S2_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS; 118 + 119 + if (!(sel & VCAP_SEL_COUNTER)) 120 + value |= S2_CORE_UPDATE_CTRL_UPDATE_CNT_DIS; 121 + 122 + ocelot_write(oc, value, S2_CORE_UPDATE_CTRL); 123 + rc = readx_poll_timeout(vcap_s2_read_update_ctrl, oc, value, 124 + (value & S2_CORE_UPDATE_CTRL_UPDATE_SHOT) == 0, 125 + 10, 100000); 126 + } 127 + 128 + /* Convert from 0-based row to VCAP entry row and run command */ 129 + static void vcap_row_cmd(struct ocelot *oc, u32 row, int cmd, int sel) 130 + { 131 + vcap_cmd(oc, vcap_is2.entry_count - row - 1, cmd, sel); 132 + } 133 + 134 + static void vcap_entry2cache(struct ocelot *oc, struct vcap_data *data) 135 + { 136 + u32 i; 137 + 138 + for (i = 0; i < vcap_is2.entry_words; i++) { 139 + ocelot_write_rix(oc, data->entry[i], S2_CACHE_ENTRY_DAT, i); 140 + ocelot_write_rix(oc, ~data->mask[i], S2_CACHE_MASK_DAT, i); 141 + } 142 + ocelot_write(oc, data->tg, S2_CACHE_TG_DAT); 143 + } 144 + 145 + static void vcap_cache2entry(struct ocelot *oc, struct vcap_data *data) 146 + { 147 + u32 i; 148 + 149 + for (i = 0; i < vcap_is2.entry_words; i++) { 150 + data->entry[i] = ocelot_read_rix(oc, S2_CACHE_ENTRY_DAT, i); 151 + // Invert mask 152 + data->mask[i] = ~ocelot_read_rix(oc, S2_CACHE_MASK_DAT, i); 153 + } 154 + data->tg = ocelot_read(oc, S2_CACHE_TG_DAT); 155 + } 156 + 157 + static void vcap_action2cache(struct ocelot *oc, struct vcap_data *data) 158 + { 159 + u32 i, width, mask; 160 + 161 + /* Encode action type */ 162 + width = vcap_is2.action_type_width; 163 + if (width) { 164 + mask = GENMASK(width, 0); 165 + data->action[0] = ((data->action[0] & ~mask) | data->type); 166 + } 167 + 168 + for (i = 0; i < vcap_is2.action_words; i++) 169 + ocelot_write_rix(oc, data->action[i], S2_CACHE_ACTION_DAT, i); 170 + 171 + for (i = 0; i < vcap_is2.counter_words; i++) 172 + ocelot_write_rix(oc, data->counter[i], S2_CACHE_CNT_DAT, i); 173 + } 174 + 175 + static void vcap_cache2action(struct ocelot *oc, struct vcap_data *data) 176 + { 177 + u32 i, width; 178 + 179 + for (i = 0; i < vcap_is2.action_words; i++) 180 + data->action[i] = ocelot_read_rix(oc, S2_CACHE_ACTION_DAT, i); 181 + 182 + for (i = 0; i < vcap_is2.counter_words; i++) 183 + data->counter[i] = ocelot_read_rix(oc, S2_CACHE_CNT_DAT, i); 184 + 185 + /* Extract action type */ 186 + width = vcap_is2.action_type_width; 187 + data->type = (width ? (data->action[0] & GENMASK(width, 0)) : 0); 188 + } 189 + 190 + /* Calculate offsets for entry */ 191 + static void is2_data_get(struct vcap_data *data, int ix) 192 + { 193 + u32 i, col, offset, count, cnt, base, width = vcap_is2.tg_width; 194 + 195 + count = (data->tg_sw == VCAP_TG_HALF ? 2 : 4); 196 + col = (ix % 2); 197 + cnt = (vcap_is2.sw_count / count); 198 + base = (vcap_is2.sw_count - col * cnt - cnt); 199 + data->tg_value = 0; 200 + data->tg_mask = 0; 201 + for (i = 0; i < cnt; i++) { 202 + offset = ((base + i) * width); 203 + data->tg_value |= (data->tg_sw << offset); 204 + data->tg_mask |= GENMASK(offset + width - 1, offset); 205 + } 206 + 207 + /* Calculate key/action/counter offsets */ 208 + col = (count - col - 1); 209 + data->key_offset = (base * vcap_is2.entry_width) / vcap_is2.sw_count; 210 + data->counter_offset = (cnt * col * vcap_is2.counter_width); 211 + i = data->type; 212 + width = vcap_is2.action_table[i].width; 213 + cnt = vcap_is2.action_table[i].count; 214 + data->action_offset = 215 + (((cnt * col * width) / count) + vcap_is2.action_type_width); 216 + } 217 + 218 + static void vcap_data_set(u32 *data, u32 offset, u32 len, u32 value) 219 + { 220 + u32 i, v, m; 221 + 222 + for (i = 0; i < len; i++, offset++) { 223 + v = data[offset / ENTRY_WIDTH]; 224 + m = (1 << (offset % ENTRY_WIDTH)); 225 + if (value & (1 << i)) 226 + v |= m; 227 + else 228 + v &= ~m; 229 + data[offset / ENTRY_WIDTH] = v; 230 + } 231 + } 232 + 233 + static u32 vcap_data_get(u32 *data, u32 offset, u32 len) 234 + { 235 + u32 i, v, m, value = 0; 236 + 237 + for (i = 0; i < len; i++, offset++) { 238 + v = data[offset / ENTRY_WIDTH]; 239 + m = (1 << (offset % ENTRY_WIDTH)); 240 + if (v & m) 241 + value |= (1 << i); 242 + } 243 + return value; 244 + } 245 + 246 + static void vcap_key_set(struct vcap_data *data, u32 offset, u32 width, 247 + u32 value, u32 mask) 248 + { 249 + vcap_data_set(data->entry, offset + data->key_offset, width, value); 250 + vcap_data_set(data->mask, offset + data->key_offset, width, mask); 251 + } 252 + 253 + static void vcap_key_bytes_set(struct vcap_data *data, u32 offset, u8 *val, 254 + u8 *msk, u32 count) 255 + { 256 + u32 i, j, n = 0, value = 0, mask = 0; 257 + 258 + /* Data wider than 32 bits are split up in chunks of maximum 32 bits. 259 + * The 32 LSB of the data are written to the 32 MSB of the TCAM. 260 + */ 261 + offset += (count * 8); 262 + for (i = 0; i < count; i++) { 263 + j = (count - i - 1); 264 + value += (val[j] << n); 265 + mask += (msk[j] << n); 266 + n += 8; 267 + if (n == ENTRY_WIDTH || (i + 1) == count) { 268 + offset -= n; 269 + vcap_key_set(data, offset, n, value, mask); 270 + n = 0; 271 + value = 0; 272 + mask = 0; 273 + } 274 + } 275 + } 276 + 277 + static void vcap_key_l4_port_set(struct vcap_data *data, u32 offset, 278 + struct ocelot_vcap_udp_tcp *port) 279 + { 280 + vcap_key_set(data, offset, 16, port->value, port->mask); 281 + } 282 + 283 + static void vcap_key_bit_set(struct vcap_data *data, u32 offset, 284 + enum ocelot_vcap_bit val) 285 + { 286 + vcap_key_set(data, offset, 1, val == OCELOT_VCAP_BIT_1 ? 1 : 0, 287 + val == OCELOT_VCAP_BIT_ANY ? 0 : 1); 288 + } 289 + 290 + #define VCAP_KEY_SET(fld, val, msk) \ 291 + vcap_key_set(&data, IS2_HKO_##fld, IS2_HKL_##fld, val, msk) 292 + #define VCAP_KEY_ANY_SET(fld) \ 293 + vcap_key_set(&data, IS2_HKO_##fld, IS2_HKL_##fld, 0, 0) 294 + #define VCAP_KEY_BIT_SET(fld, val) vcap_key_bit_set(&data, IS2_HKO_##fld, val) 295 + #define VCAP_KEY_BYTES_SET(fld, val, msk) \ 296 + vcap_key_bytes_set(&data, IS2_HKO_##fld, val, msk, IS2_HKL_##fld / 8) 297 + 298 + static void vcap_action_set(struct vcap_data *data, u32 offset, u32 width, 299 + u32 value) 300 + { 301 + vcap_data_set(data->action, offset + data->action_offset, width, value); 302 + } 303 + 304 + #define VCAP_ACT_SET(fld, val) \ 305 + vcap_action_set(data, IS2_AO_##fld, IS2_AL_##fld, val) 306 + 307 + static void is2_action_set(struct vcap_data *data, 308 + enum ocelot_ace_action action) 309 + { 310 + switch (action) { 311 + case OCELOT_ACL_ACTION_DROP: 312 + VCAP_ACT_SET(PORT_MASK, 0x0); 313 + VCAP_ACT_SET(MASK_MODE, 0x1); 314 + VCAP_ACT_SET(POLICE_ENA, 0x1); 315 + VCAP_ACT_SET(POLICE_IDX, OCELOT_POLICER_DISCARD); 316 + VCAP_ACT_SET(CPU_QU_NUM, 0x0); 317 + VCAP_ACT_SET(CPU_COPY_ENA, 0x0); 318 + break; 319 + case OCELOT_ACL_ACTION_TRAP: 320 + VCAP_ACT_SET(PORT_MASK, 0x0); 321 + VCAP_ACT_SET(MASK_MODE, 0x0); 322 + VCAP_ACT_SET(POLICE_ENA, 0x0); 323 + VCAP_ACT_SET(POLICE_IDX, 0x0); 324 + VCAP_ACT_SET(CPU_QU_NUM, 0x0); 325 + VCAP_ACT_SET(CPU_COPY_ENA, 0x1); 326 + break; 327 + } 328 + } 329 + 330 + static void is2_entry_set(struct ocelot *ocelot, int ix, 331 + struct ocelot_ace_rule *ace) 332 + { 333 + u32 val, msk, type, type_mask = 0xf, i, count; 334 + struct ocelot_ace_vlan *tag = &ace->vlan; 335 + struct ocelot_vcap_u64 payload = { 0 }; 336 + struct vcap_data data = { 0 }; 337 + int row = (ix / 2); 338 + 339 + /* Read row */ 340 + vcap_row_cmd(ocelot, row, VCAP_CMD_READ, VCAP_SEL_ALL); 341 + vcap_cache2entry(ocelot, &data); 342 + vcap_cache2action(ocelot, &data); 343 + 344 + data.tg_sw = VCAP_TG_HALF; 345 + is2_data_get(&data, ix); 346 + data.tg = (data.tg & ~data.tg_mask); 347 + if (ace->prio != 0) 348 + data.tg |= data.tg_value; 349 + 350 + data.type = IS2_ACTION_TYPE_NORMAL; 351 + 352 + VCAP_KEY_ANY_SET(PAG); 353 + VCAP_KEY_SET(IGR_PORT_MASK, 0, ~BIT(ace->chip_port)); 354 + VCAP_KEY_BIT_SET(FIRST, OCELOT_VCAP_BIT_1); 355 + VCAP_KEY_BIT_SET(HOST_MATCH, OCELOT_VCAP_BIT_ANY); 356 + VCAP_KEY_BIT_SET(L2_MC, ace->dmac_mc); 357 + VCAP_KEY_BIT_SET(L2_BC, ace->dmac_bc); 358 + VCAP_KEY_BIT_SET(VLAN_TAGGED, tag->tagged); 359 + VCAP_KEY_SET(VID, tag->vid.value, tag->vid.mask); 360 + VCAP_KEY_SET(PCP, tag->pcp.value[0], tag->pcp.mask[0]); 361 + VCAP_KEY_BIT_SET(DEI, tag->dei); 362 + 363 + switch (ace->type) { 364 + case OCELOT_ACE_TYPE_ETYPE: { 365 + struct ocelot_ace_frame_etype *etype = &ace->frame.etype; 366 + 367 + type = IS2_TYPE_ETYPE; 368 + VCAP_KEY_BYTES_SET(L2_DMAC, etype->dmac.value, 369 + etype->dmac.mask); 370 + VCAP_KEY_BYTES_SET(L2_SMAC, etype->smac.value, 371 + etype->smac.mask); 372 + VCAP_KEY_BYTES_SET(MAC_ETYPE_ETYPE, etype->etype.value, 373 + etype->etype.mask); 374 + VCAP_KEY_ANY_SET(MAC_ETYPE_L2_PAYLOAD); // Clear unused bits 375 + vcap_key_bytes_set(&data, IS2_HKO_MAC_ETYPE_L2_PAYLOAD, 376 + etype->data.value, etype->data.mask, 2); 377 + break; 378 + } 379 + case OCELOT_ACE_TYPE_LLC: { 380 + struct ocelot_ace_frame_llc *llc = &ace->frame.llc; 381 + 382 + type = IS2_TYPE_LLC; 383 + VCAP_KEY_BYTES_SET(L2_DMAC, llc->dmac.value, llc->dmac.mask); 384 + VCAP_KEY_BYTES_SET(L2_SMAC, llc->smac.value, llc->smac.mask); 385 + for (i = 0; i < 4; i++) { 386 + payload.value[i] = llc->llc.value[i]; 387 + payload.mask[i] = llc->llc.mask[i]; 388 + } 389 + VCAP_KEY_BYTES_SET(MAC_LLC_L2_LLC, payload.value, payload.mask); 390 + break; 391 + } 392 + case OCELOT_ACE_TYPE_SNAP: { 393 + struct ocelot_ace_frame_snap *snap = &ace->frame.snap; 394 + 395 + type = IS2_TYPE_SNAP; 396 + VCAP_KEY_BYTES_SET(L2_DMAC, snap->dmac.value, snap->dmac.mask); 397 + VCAP_KEY_BYTES_SET(L2_SMAC, snap->smac.value, snap->smac.mask); 398 + VCAP_KEY_BYTES_SET(MAC_SNAP_L2_SNAP, 399 + ace->frame.snap.snap.value, 400 + ace->frame.snap.snap.mask); 401 + break; 402 + } 403 + case OCELOT_ACE_TYPE_ARP: { 404 + struct ocelot_ace_frame_arp *arp = &ace->frame.arp; 405 + 406 + type = IS2_TYPE_ARP; 407 + VCAP_KEY_BYTES_SET(MAC_ARP_L2_SMAC, arp->smac.value, 408 + arp->smac.mask); 409 + VCAP_KEY_BIT_SET(MAC_ARP_ARP_ADDR_SPACE_OK, arp->ethernet); 410 + VCAP_KEY_BIT_SET(MAC_ARP_ARP_PROTO_SPACE_OK, arp->ip); 411 + VCAP_KEY_BIT_SET(MAC_ARP_ARP_LEN_OK, arp->length); 412 + VCAP_KEY_BIT_SET(MAC_ARP_ARP_TGT_MATCH, arp->dmac_match); 413 + VCAP_KEY_BIT_SET(MAC_ARP_ARP_SENDER_MATCH, arp->smac_match); 414 + VCAP_KEY_BIT_SET(MAC_ARP_ARP_OPCODE_UNKNOWN, arp->unknown); 415 + 416 + /* OPCODE is inverse, bit 0 is reply flag, bit 1 is RARP flag */ 417 + val = ((arp->req == OCELOT_VCAP_BIT_0 ? 1 : 0) | 418 + (arp->arp == OCELOT_VCAP_BIT_0 ? 2 : 0)); 419 + msk = ((arp->req == OCELOT_VCAP_BIT_ANY ? 0 : 1) | 420 + (arp->arp == OCELOT_VCAP_BIT_ANY ? 0 : 2)); 421 + VCAP_KEY_SET(MAC_ARP_ARP_OPCODE, val, msk); 422 + vcap_key_bytes_set(&data, IS2_HKO_MAC_ARP_L3_IP4_DIP, 423 + arp->dip.value.addr, arp->dip.mask.addr, 4); 424 + vcap_key_bytes_set(&data, IS2_HKO_MAC_ARP_L3_IP4_SIP, 425 + arp->sip.value.addr, arp->sip.mask.addr, 4); 426 + VCAP_KEY_ANY_SET(MAC_ARP_DIP_EQ_SIP); 427 + break; 428 + } 429 + case OCELOT_ACE_TYPE_IPV4: 430 + case OCELOT_ACE_TYPE_IPV6: { 431 + enum ocelot_vcap_bit sip_eq_dip, sport_eq_dport, seq_zero, tcp; 432 + enum ocelot_vcap_bit ttl, fragment, options, tcp_ack, tcp_urg; 433 + enum ocelot_vcap_bit tcp_fin, tcp_syn, tcp_rst, tcp_psh; 434 + struct ocelot_ace_frame_ipv4 *ipv4 = NULL; 435 + struct ocelot_ace_frame_ipv6 *ipv6 = NULL; 436 + struct ocelot_vcap_udp_tcp *sport, *dport; 437 + struct ocelot_vcap_ipv4 sip, dip; 438 + struct ocelot_vcap_u8 proto, ds; 439 + struct ocelot_vcap_u48 *ip_data; 440 + 441 + if (ace->type == OCELOT_ACE_TYPE_IPV4) { 442 + ipv4 = &ace->frame.ipv4; 443 + ttl = ipv4->ttl; 444 + fragment = ipv4->fragment; 445 + options = ipv4->options; 446 + proto = ipv4->proto; 447 + ds = ipv4->ds; 448 + ip_data = &ipv4->data; 449 + sip = ipv4->sip; 450 + dip = ipv4->dip; 451 + sport = &ipv4->sport; 452 + dport = &ipv4->dport; 453 + tcp_fin = ipv4->tcp_fin; 454 + tcp_syn = ipv4->tcp_syn; 455 + tcp_rst = ipv4->tcp_rst; 456 + tcp_psh = ipv4->tcp_psh; 457 + tcp_ack = ipv4->tcp_ack; 458 + tcp_urg = ipv4->tcp_urg; 459 + sip_eq_dip = ipv4->sip_eq_dip; 460 + sport_eq_dport = ipv4->sport_eq_dport; 461 + seq_zero = ipv4->seq_zero; 462 + } else { 463 + ipv6 = &ace->frame.ipv6; 464 + ttl = ipv6->ttl; 465 + fragment = OCELOT_VCAP_BIT_ANY; 466 + options = OCELOT_VCAP_BIT_ANY; 467 + proto = ipv6->proto; 468 + ds = ipv6->ds; 469 + ip_data = &ipv6->data; 470 + for (i = 0; i < 8; i++) { 471 + val = ipv6->sip.value[i + 8]; 472 + msk = ipv6->sip.mask[i + 8]; 473 + if (i < 4) { 474 + dip.value.addr[i] = val; 475 + dip.mask.addr[i] = msk; 476 + } else { 477 + sip.value.addr[i - 4] = val; 478 + sip.mask.addr[i - 4] = msk; 479 + } 480 + } 481 + sport = &ipv6->sport; 482 + dport = &ipv6->dport; 483 + tcp_fin = ipv6->tcp_fin; 484 + tcp_syn = ipv6->tcp_syn; 485 + tcp_rst = ipv6->tcp_rst; 486 + tcp_psh = ipv6->tcp_psh; 487 + tcp_ack = ipv6->tcp_ack; 488 + tcp_urg = ipv6->tcp_urg; 489 + sip_eq_dip = ipv6->sip_eq_dip; 490 + sport_eq_dport = ipv6->sport_eq_dport; 491 + seq_zero = ipv6->seq_zero; 492 + } 493 + 494 + VCAP_KEY_BIT_SET(IP4, 495 + ipv4 ? OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0); 496 + VCAP_KEY_BIT_SET(L3_FRAGMENT, fragment); 497 + VCAP_KEY_ANY_SET(L3_FRAG_OFS_GT0); 498 + VCAP_KEY_BIT_SET(L3_OPTIONS, options); 499 + VCAP_KEY_BIT_SET(L3_TTL_GT0, ttl); 500 + VCAP_KEY_BYTES_SET(L3_TOS, ds.value, ds.mask); 501 + vcap_key_bytes_set(&data, IS2_HKO_L3_IP4_DIP, dip.value.addr, 502 + dip.mask.addr, 4); 503 + vcap_key_bytes_set(&data, IS2_HKO_L3_IP4_SIP, sip.value.addr, 504 + sip.mask.addr, 4); 505 + VCAP_KEY_BIT_SET(DIP_EQ_SIP, sip_eq_dip); 506 + val = proto.value[0]; 507 + msk = proto.mask[0]; 508 + type = IS2_TYPE_IP_UDP_TCP; 509 + if (msk == 0xff && (val == 6 || val == 17)) { 510 + /* UDP/TCP protocol match */ 511 + tcp = (val == 6 ? 512 + OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0); 513 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_TCP, tcp); 514 + vcap_key_l4_port_set(&data, 515 + IS2_HKO_IP4_TCP_UDP_L4_DPORT, 516 + dport); 517 + vcap_key_l4_port_set(&data, 518 + IS2_HKO_IP4_TCP_UDP_L4_SPORT, 519 + sport); 520 + VCAP_KEY_ANY_SET(IP4_TCP_UDP_L4_RNG); 521 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_SPORT_EQ_DPORT, 522 + sport_eq_dport); 523 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_SEQUENCE_EQ0, seq_zero); 524 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_L4_FIN, tcp_fin); 525 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_L4_SYN, tcp_syn); 526 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_L4_RST, tcp_rst); 527 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_L4_PSH, tcp_psh); 528 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_L4_ACK, tcp_ack); 529 + VCAP_KEY_BIT_SET(IP4_TCP_UDP_L4_URG, tcp_urg); 530 + VCAP_KEY_ANY_SET(IP4_TCP_UDP_L4_1588_DOM); 531 + VCAP_KEY_ANY_SET(IP4_TCP_UDP_L4_1588_VER); 532 + } else { 533 + if (msk == 0) { 534 + /* Any IP protocol match */ 535 + type_mask = IS2_TYPE_MASK_IP_ANY; 536 + } else { 537 + /* Non-UDP/TCP protocol match */ 538 + type = IS2_TYPE_IP_OTHER; 539 + for (i = 0; i < 6; i++) { 540 + payload.value[i] = ip_data->value[i]; 541 + payload.mask[i] = ip_data->mask[i]; 542 + } 543 + } 544 + VCAP_KEY_BYTES_SET(IP4_OTHER_L3_PROTO, proto.value, 545 + proto.mask); 546 + VCAP_KEY_BYTES_SET(IP4_OTHER_L3_PAYLOAD, payload.value, 547 + payload.mask); 548 + } 549 + break; 550 + } 551 + case OCELOT_ACE_TYPE_ANY: 552 + default: 553 + type = 0; 554 + type_mask = 0; 555 + count = (vcap_is2.entry_width / 2); 556 + for (i = (IS2_HKO_PCP + IS2_HKL_PCP); i < count; 557 + i += ENTRY_WIDTH) { 558 + /* Clear entry data */ 559 + vcap_key_set(&data, i, min(32u, count - i), 0, 0); 560 + } 561 + break; 562 + } 563 + 564 + VCAP_KEY_SET(TYPE, type, type_mask); 565 + is2_action_set(&data, ace->action); 566 + vcap_data_set(data.counter, data.counter_offset, vcap_is2.counter_width, 567 + ace->stats.pkts); 568 + 569 + /* Write row */ 570 + vcap_entry2cache(ocelot, &data); 571 + vcap_action2cache(ocelot, &data); 572 + vcap_row_cmd(ocelot, row, VCAP_CMD_WRITE, VCAP_SEL_ALL); 573 + } 574 + 575 + static void is2_entry_get(struct ocelot_ace_rule *rule, int ix) 576 + { 577 + struct ocelot *op = rule->port->ocelot; 578 + struct vcap_data data; 579 + int row = (ix / 2); 580 + u32 cnt; 581 + 582 + vcap_row_cmd(op, row, VCAP_CMD_READ, VCAP_SEL_COUNTER); 583 + vcap_cache2action(op, &data); 584 + data.tg_sw = VCAP_TG_HALF; 585 + is2_data_get(&data, ix); 586 + cnt = vcap_data_get(data.counter, data.counter_offset, 587 + vcap_is2.counter_width); 588 + 589 + rule->stats.pkts = cnt; 590 + } 591 + 592 + static void ocelot_ace_rule_add(struct ocelot_acl_block *block, 593 + struct ocelot_ace_rule *rule) 594 + { 595 + struct ocelot_ace_rule *tmp; 596 + struct list_head *pos, *n; 597 + 598 + block->count++; 599 + 600 + if (list_empty(&block->rules)) { 601 + list_add(&rule->list, &block->rules); 602 + return; 603 + } 604 + 605 + list_for_each_safe(pos, n, &block->rules) { 606 + tmp = list_entry(pos, struct ocelot_ace_rule, list); 607 + if (rule->prio < tmp->prio) 608 + break; 609 + } 610 + list_add(&rule->list, pos->prev); 611 + } 612 + 613 + static int ocelot_ace_rule_get_index_id(struct ocelot_acl_block *block, 614 + struct ocelot_ace_rule *rule) 615 + { 616 + struct ocelot_ace_rule *tmp; 617 + int index = -1; 618 + 619 + list_for_each_entry(tmp, &block->rules, list) { 620 + ++index; 621 + if (rule->id == tmp->id) 622 + break; 623 + } 624 + return index; 625 + } 626 + 627 + static struct ocelot_ace_rule* 628 + ocelot_ace_rule_get_rule_index(struct ocelot_acl_block *block, int index) 629 + { 630 + struct ocelot_ace_rule *tmp; 631 + int i = 0; 632 + 633 + list_for_each_entry(tmp, &block->rules, list) { 634 + if (i == index) 635 + return tmp; 636 + ++i; 637 + } 638 + 639 + return NULL; 640 + } 641 + 642 + int ocelot_ace_rule_offload_add(struct ocelot_ace_rule *rule) 643 + { 644 + struct ocelot_ace_rule *ace; 645 + int i, index; 646 + 647 + /* Add rule to the linked list */ 648 + ocelot_ace_rule_add(acl_block, rule); 649 + 650 + /* Get the index of the inserted rule */ 651 + index = ocelot_ace_rule_get_index_id(acl_block, rule); 652 + 653 + /* Move down the rules to make place for the new rule */ 654 + for (i = acl_block->count - 1; i > index; i--) { 655 + ace = ocelot_ace_rule_get_rule_index(acl_block, i); 656 + is2_entry_set(rule->port->ocelot, i, ace); 657 + } 658 + 659 + /* Now insert the new rule */ 660 + is2_entry_set(rule->port->ocelot, index, rule); 661 + return 0; 662 + } 663 + 664 + static void ocelot_ace_rule_del(struct ocelot_acl_block *block, 665 + struct ocelot_ace_rule *rule) 666 + { 667 + struct ocelot_ace_rule *tmp; 668 + struct list_head *pos, *q; 669 + 670 + list_for_each_safe(pos, q, &block->rules) { 671 + tmp = list_entry(pos, struct ocelot_ace_rule, list); 672 + if (tmp->id == rule->id) { 673 + list_del(pos); 674 + kfree(tmp); 675 + } 676 + } 677 + 678 + block->count--; 679 + } 680 + 681 + int ocelot_ace_rule_offload_del(struct ocelot_ace_rule *rule) 682 + { 683 + struct ocelot_ace_rule del_ace = { 0 }; 684 + struct ocelot_ace_rule *ace; 685 + int i, index; 686 + 687 + /* Gets index of the rule */ 688 + index = ocelot_ace_rule_get_index_id(acl_block, rule); 689 + 690 + /* Delete rule */ 691 + ocelot_ace_rule_del(acl_block, rule); 692 + 693 + /* Move up all the blocks over the deleted rule */ 694 + for (i = index; i < acl_block->count; i++) { 695 + ace = ocelot_ace_rule_get_rule_index(acl_block, i); 696 + is2_entry_set(rule->port->ocelot, i, ace); 697 + } 698 + 699 + /* Now delete the last rule, because it is duplicated */ 700 + is2_entry_set(rule->port->ocelot, acl_block->count, &del_ace); 701 + 702 + return 0; 703 + } 704 + 705 + int ocelot_ace_rule_stats_update(struct ocelot_ace_rule *rule) 706 + { 707 + struct ocelot_ace_rule *tmp; 708 + int index; 709 + 710 + index = ocelot_ace_rule_get_index_id(acl_block, rule); 711 + is2_entry_get(rule, index); 712 + 713 + /* After we get the result we need to clear the counters */ 714 + tmp = ocelot_ace_rule_get_rule_index(acl_block, index); 715 + tmp->stats.pkts = 0; 716 + is2_entry_set(rule->port->ocelot, index, tmp); 717 + 718 + return 0; 719 + } 720 + 721 + static struct ocelot_acl_block *ocelot_acl_block_create(struct ocelot *ocelot) 722 + { 723 + struct ocelot_acl_block *block; 724 + 725 + block = kzalloc(sizeof(*block), GFP_KERNEL); 726 + if (!block) 727 + return NULL; 728 + 729 + INIT_LIST_HEAD(&block->rules); 730 + block->count = 0; 731 + block->ocelot = ocelot; 732 + 733 + return block; 734 + } 735 + 736 + static void ocelot_acl_block_destroy(struct ocelot_acl_block *block) 737 + { 738 + kfree(block); 739 + } 740 + 741 + int ocelot_ace_init(struct ocelot *ocelot) 742 + { 743 + struct vcap_data data = { 0 }; 744 + 745 + vcap_entry2cache(ocelot, &data); 746 + ocelot_write(ocelot, vcap_is2.entry_count, S2_CORE_MV_CFG); 747 + vcap_cmd(ocelot, 0, VCAP_CMD_INITIALIZE, VCAP_SEL_ENTRY); 748 + 749 + vcap_action2cache(ocelot, &data); 750 + ocelot_write(ocelot, vcap_is2.action_count, S2_CORE_MV_CFG); 751 + vcap_cmd(ocelot, 0, VCAP_CMD_INITIALIZE, 752 + VCAP_SEL_ACTION | VCAP_SEL_COUNTER); 753 + 754 + /* Create a policer that will drop the frames for the cpu. 755 + * This policer will be used as action in the acl rules to drop 756 + * frames. 757 + */ 758 + ocelot_write_gix(ocelot, 0x299, ANA_POL_MODE_CFG, 759 + OCELOT_POLICER_DISCARD); 760 + ocelot_write_gix(ocelot, 0x1, ANA_POL_PIR_CFG, 761 + OCELOT_POLICER_DISCARD); 762 + ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_PIR_STATE, 763 + OCELOT_POLICER_DISCARD); 764 + ocelot_write_gix(ocelot, 0x0, ANA_POL_CIR_CFG, 765 + OCELOT_POLICER_DISCARD); 766 + ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_CIR_STATE, 767 + OCELOT_POLICER_DISCARD); 768 + 769 + acl_block = ocelot_acl_block_create(ocelot); 770 + 771 + return 0; 772 + } 773 + 774 + void ocelot_ace_deinit(void) 775 + { 776 + ocelot_acl_block_destroy(acl_block); 777 + }
+227
drivers/net/ethernet/mscc/ocelot_ace.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 + /* Microsemi Ocelot Switch driver 3 + * Copyright (c) 2019 Microsemi Corporation 4 + */ 5 + 6 + #ifndef _MSCC_OCELOT_ACE_H_ 7 + #define _MSCC_OCELOT_ACE_H_ 8 + 9 + #include "ocelot.h" 10 + #include <net/sch_generic.h> 11 + #include <net/pkt_cls.h> 12 + 13 + struct ocelot_ipv4 { 14 + u8 addr[4]; 15 + }; 16 + 17 + enum ocelot_vcap_bit { 18 + OCELOT_VCAP_BIT_ANY, 19 + OCELOT_VCAP_BIT_0, 20 + OCELOT_VCAP_BIT_1 21 + }; 22 + 23 + struct ocelot_vcap_u8 { 24 + u8 value[1]; 25 + u8 mask[1]; 26 + }; 27 + 28 + struct ocelot_vcap_u16 { 29 + u8 value[2]; 30 + u8 mask[2]; 31 + }; 32 + 33 + struct ocelot_vcap_u24 { 34 + u8 value[3]; 35 + u8 mask[3]; 36 + }; 37 + 38 + struct ocelot_vcap_u32 { 39 + u8 value[4]; 40 + u8 mask[4]; 41 + }; 42 + 43 + struct ocelot_vcap_u40 { 44 + u8 value[5]; 45 + u8 mask[5]; 46 + }; 47 + 48 + struct ocelot_vcap_u48 { 49 + u8 value[6]; 50 + u8 mask[6]; 51 + }; 52 + 53 + struct ocelot_vcap_u64 { 54 + u8 value[8]; 55 + u8 mask[8]; 56 + }; 57 + 58 + struct ocelot_vcap_u128 { 59 + u8 value[16]; 60 + u8 mask[16]; 61 + }; 62 + 63 + struct ocelot_vcap_vid { 64 + u16 value; 65 + u16 mask; 66 + }; 67 + 68 + struct ocelot_vcap_ipv4 { 69 + struct ocelot_ipv4 value; 70 + struct ocelot_ipv4 mask; 71 + }; 72 + 73 + struct ocelot_vcap_udp_tcp { 74 + u16 value; 75 + u16 mask; 76 + }; 77 + 78 + enum ocelot_ace_type { 79 + OCELOT_ACE_TYPE_ANY, 80 + OCELOT_ACE_TYPE_ETYPE, 81 + OCELOT_ACE_TYPE_LLC, 82 + OCELOT_ACE_TYPE_SNAP, 83 + OCELOT_ACE_TYPE_ARP, 84 + OCELOT_ACE_TYPE_IPV4, 85 + OCELOT_ACE_TYPE_IPV6 86 + }; 87 + 88 + struct ocelot_ace_vlan { 89 + struct ocelot_vcap_vid vid; /* VLAN ID (12 bit) */ 90 + struct ocelot_vcap_u8 pcp; /* PCP (3 bit) */ 91 + enum ocelot_vcap_bit dei; /* DEI */ 92 + enum ocelot_vcap_bit tagged; /* Tagged/untagged frame */ 93 + }; 94 + 95 + struct ocelot_ace_frame_etype { 96 + struct ocelot_vcap_u48 dmac; 97 + struct ocelot_vcap_u48 smac; 98 + struct ocelot_vcap_u16 etype; 99 + struct ocelot_vcap_u16 data; /* MAC data */ 100 + }; 101 + 102 + struct ocelot_ace_frame_llc { 103 + struct ocelot_vcap_u48 dmac; 104 + struct ocelot_vcap_u48 smac; 105 + 106 + /* LLC header: DSAP at byte 0, SSAP at byte 1, Control at byte 2 */ 107 + struct ocelot_vcap_u32 llc; 108 + }; 109 + 110 + struct ocelot_ace_frame_snap { 111 + struct ocelot_vcap_u48 dmac; 112 + struct ocelot_vcap_u48 smac; 113 + 114 + /* SNAP header: Organization Code at byte 0, Type at byte 3 */ 115 + struct ocelot_vcap_u40 snap; 116 + }; 117 + 118 + struct ocelot_ace_frame_arp { 119 + struct ocelot_vcap_u48 smac; 120 + enum ocelot_vcap_bit arp; /* Opcode ARP/RARP */ 121 + enum ocelot_vcap_bit req; /* Opcode request/reply */ 122 + enum ocelot_vcap_bit unknown; /* Opcode unknown */ 123 + enum ocelot_vcap_bit smac_match; /* Sender MAC matches SMAC */ 124 + enum ocelot_vcap_bit dmac_match; /* Target MAC matches DMAC */ 125 + 126 + /**< Protocol addr. length 4, hardware length 6 */ 127 + enum ocelot_vcap_bit length; 128 + 129 + enum ocelot_vcap_bit ip; /* Protocol address type IP */ 130 + enum ocelot_vcap_bit ethernet; /* Hardware address type Ethernet */ 131 + struct ocelot_vcap_ipv4 sip; /* Sender IP address */ 132 + struct ocelot_vcap_ipv4 dip; /* Target IP address */ 133 + }; 134 + 135 + struct ocelot_ace_frame_ipv4 { 136 + enum ocelot_vcap_bit ttl; /* TTL zero */ 137 + enum ocelot_vcap_bit fragment; /* Fragment */ 138 + enum ocelot_vcap_bit options; /* Header options */ 139 + struct ocelot_vcap_u8 ds; 140 + struct ocelot_vcap_u8 proto; /* Protocol */ 141 + struct ocelot_vcap_ipv4 sip; /* Source IP address */ 142 + struct ocelot_vcap_ipv4 dip; /* Destination IP address */ 143 + struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */ 144 + struct ocelot_vcap_udp_tcp sport; /* UDP/TCP: Source port */ 145 + struct ocelot_vcap_udp_tcp dport; /* UDP/TCP: Destination port */ 146 + enum ocelot_vcap_bit tcp_fin; 147 + enum ocelot_vcap_bit tcp_syn; 148 + enum ocelot_vcap_bit tcp_rst; 149 + enum ocelot_vcap_bit tcp_psh; 150 + enum ocelot_vcap_bit tcp_ack; 151 + enum ocelot_vcap_bit tcp_urg; 152 + enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */ 153 + enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */ 154 + enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */ 155 + }; 156 + 157 + struct ocelot_ace_frame_ipv6 { 158 + struct ocelot_vcap_u8 proto; /* IPv6 protocol */ 159 + struct ocelot_vcap_u128 sip; /* IPv6 source (byte 0-7 ignored) */ 160 + enum ocelot_vcap_bit ttl; /* TTL zero */ 161 + struct ocelot_vcap_u8 ds; 162 + struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */ 163 + struct ocelot_vcap_udp_tcp sport; 164 + struct ocelot_vcap_udp_tcp dport; 165 + enum ocelot_vcap_bit tcp_fin; 166 + enum ocelot_vcap_bit tcp_syn; 167 + enum ocelot_vcap_bit tcp_rst; 168 + enum ocelot_vcap_bit tcp_psh; 169 + enum ocelot_vcap_bit tcp_ack; 170 + enum ocelot_vcap_bit tcp_urg; 171 + enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */ 172 + enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */ 173 + enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */ 174 + }; 175 + 176 + enum ocelot_ace_action { 177 + OCELOT_ACL_ACTION_DROP, 178 + OCELOT_ACL_ACTION_TRAP, 179 + }; 180 + 181 + struct ocelot_ace_stats { 182 + u64 bytes; 183 + u64 pkts; 184 + u64 used; 185 + }; 186 + 187 + struct ocelot_ace_rule { 188 + struct list_head list; 189 + struct ocelot_port *port; 190 + 191 + u16 prio; 192 + u32 id; 193 + 194 + enum ocelot_ace_action action; 195 + struct ocelot_ace_stats stats; 196 + int chip_port; 197 + 198 + enum ocelot_vcap_bit dmac_mc; 199 + enum ocelot_vcap_bit dmac_bc; 200 + struct ocelot_ace_vlan vlan; 201 + 202 + enum ocelot_ace_type type; 203 + union { 204 + /* ocelot_ACE_TYPE_ANY: No specific fields */ 205 + struct ocelot_ace_frame_etype etype; 206 + struct ocelot_ace_frame_llc llc; 207 + struct ocelot_ace_frame_snap snap; 208 + struct ocelot_ace_frame_arp arp; 209 + struct ocelot_ace_frame_ipv4 ipv4; 210 + struct ocelot_ace_frame_ipv6 ipv6; 211 + } frame; 212 + }; 213 + 214 + struct ocelot_acl_block { 215 + struct list_head rules; 216 + struct ocelot *ocelot; 217 + int count; 218 + }; 219 + 220 + int ocelot_ace_rule_offload_add(struct ocelot_ace_rule *rule); 221 + int ocelot_ace_rule_offload_del(struct ocelot_ace_rule *rule); 222 + int ocelot_ace_rule_stats_update(struct ocelot_ace_rule *rule); 223 + 224 + int ocelot_ace_init(struct ocelot *ocelot); 225 + void ocelot_ace_deinit(void); 226 + 227 + #endif /* _MSCC_OCELOT_ACE_H_ */
+1
drivers/net/ethernet/mscc/ocelot_board.c
··· 188 188 { QSYS, "qsys" }, 189 189 { ANA, "ana" }, 190 190 { QS, "qs" }, 191 + { S2, "s2" }, 191 192 }; 192 193 193 194 if (!np && !pdev->dev.platform_data)
+11
drivers/net/ethernet/mscc/ocelot_regs.c
··· 224 224 REG(SYS_PTP_CFG, 0x0006c4), 225 225 }; 226 226 227 + static const u32 ocelot_s2_regmap[] = { 228 + REG(S2_CORE_UPDATE_CTRL, 0x000000), 229 + REG(S2_CORE_MV_CFG, 0x000004), 230 + REG(S2_CACHE_ENTRY_DAT, 0x000008), 231 + REG(S2_CACHE_MASK_DAT, 0x000108), 232 + REG(S2_CACHE_ACTION_DAT, 0x000208), 233 + REG(S2_CACHE_CNT_DAT, 0x000308), 234 + REG(S2_CACHE_TG_DAT, 0x000388), 235 + }; 236 + 227 237 static const u32 *ocelot_regmap[] = { 228 238 [ANA] = ocelot_ana_regmap, 229 239 [QS] = ocelot_qs_regmap, 230 240 [QSYS] = ocelot_qsys_regmap, 231 241 [REW] = ocelot_rew_regmap, 232 242 [SYS] = ocelot_sys_regmap, 243 + [S2] = ocelot_s2_regmap, 233 244 }; 234 245 235 246 static const struct reg_field ocelot_regfields[] = {
+64
drivers/net/ethernet/mscc/ocelot_s2.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 + /* Microsemi Ocelot Switch driver 3 + * Copyright (c) 2018 Microsemi Corporation 4 + */ 5 + 6 + #ifndef _OCELOT_S2_CORE_H_ 7 + #define _OCELOT_S2_CORE_H_ 8 + 9 + #define S2_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22)) 10 + #define S2_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22) 11 + #define S2_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22) 12 + #define S2_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 13 + #define S2_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 14 + #define S2_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 15 + #define S2_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3)) 16 + #define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3) 17 + #define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3) 18 + #define S2_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2) 19 + #define S2_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1) 20 + #define S2_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) 21 + 22 + #define S2_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16)) 23 + #define S2_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16) 24 + #define S2_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16) 25 + #define S2_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0)) 26 + #define S2_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0) 27 + 28 + #define S2_CACHE_ENTRY_DAT_RSZ 0x4 29 + 30 + #define S2_CACHE_MASK_DAT_RSZ 0x4 31 + 32 + #define S2_CACHE_ACTION_DAT_RSZ 0x4 33 + 34 + #define S2_CACHE_CNT_DAT_RSZ 0x4 35 + 36 + #define S2_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 37 + 38 + #define S2_BIST_CTRL_TCAM_BIST BIT(1) 39 + #define S2_BIST_CTRL_TCAM_INIT BIT(0) 40 + 41 + #define S2_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8) 42 + #define S2_BIST_CFG_TCAM_HCG_DIS BIT(7) 43 + #define S2_BIST_CFG_TCAM_CG_DIS BIT(6) 44 + #define S2_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0)) 45 + #define S2_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0) 46 + 47 + #define S2_BIST_STAT_BIST_RT_ERR BIT(15) 48 + #define S2_BIST_STAT_BIST_PENC_ERR BIT(14) 49 + #define S2_BIST_STAT_BIST_COMP_ERR BIT(13) 50 + #define S2_BIST_STAT_BIST_ADDR_ERR BIT(12) 51 + #define S2_BIST_STAT_BIST_BL1E_ERR BIT(11) 52 + #define S2_BIST_STAT_BIST_BL1_ERR BIT(10) 53 + #define S2_BIST_STAT_BIST_BL0E_ERR BIT(9) 54 + #define S2_BIST_STAT_BIST_BL0_ERR BIT(8) 55 + #define S2_BIST_STAT_BIST_PH1_ERR BIT(7) 56 + #define S2_BIST_STAT_BIST_PH0_ERR BIT(6) 57 + #define S2_BIST_STAT_BIST_PV1_ERR BIT(5) 58 + #define S2_BIST_STAT_BIST_PV0_ERR BIT(4) 59 + #define S2_BIST_STAT_BIST_RUN BIT(3) 60 + #define S2_BIST_STAT_BIST_ERR BIT(2) 61 + #define S2_BIST_STAT_BIST_BUSY BIT(1) 62 + #define S2_BIST_STAT_TCAM_RDY BIT(0) 63 + 64 + #endif /* _OCELOT_S2_CORE_H_ */
+403
drivers/net/ethernet/mscc/ocelot_vcap.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + * Microsemi Ocelot Switch driver 3 + * Copyright (c) 2019 Microsemi Corporation 4 + */ 5 + 6 + #ifndef _OCELOT_VCAP_H_ 7 + #define _OCELOT_VCAP_H_ 8 + 9 + /* ================================================================= 10 + * VCAP Common 11 + * ================================================================= 12 + */ 13 + 14 + /* VCAP Type-Group values */ 15 + #define VCAP_TG_NONE 0 /* Entry is invalid */ 16 + #define VCAP_TG_FULL 1 /* Full entry */ 17 + #define VCAP_TG_HALF 2 /* Half entry */ 18 + #define VCAP_TG_QUARTER 3 /* Quarter entry */ 19 + 20 + /* ================================================================= 21 + * VCAP IS2 22 + * ================================================================= 23 + */ 24 + 25 + #define VCAP_IS2_CNT 64 26 + #define VCAP_IS2_ENTRY_WIDTH 376 27 + #define VCAP_IS2_ACTION_WIDTH 99 28 + #define VCAP_PORT_CNT 11 29 + 30 + /* IS2 half key types */ 31 + #define IS2_TYPE_ETYPE 0 32 + #define IS2_TYPE_LLC 1 33 + #define IS2_TYPE_SNAP 2 34 + #define IS2_TYPE_ARP 3 35 + #define IS2_TYPE_IP_UDP_TCP 4 36 + #define IS2_TYPE_IP_OTHER 5 37 + #define IS2_TYPE_IPV6 6 38 + #define IS2_TYPE_OAM 7 39 + #define IS2_TYPE_SMAC_SIP6 8 40 + #define IS2_TYPE_ANY 100 /* Pseudo type */ 41 + 42 + /* IS2 half key type mask for matching any IP */ 43 + #define IS2_TYPE_MASK_IP_ANY 0xe 44 + 45 + /* IS2 action types */ 46 + #define IS2_ACTION_TYPE_NORMAL 0 47 + #define IS2_ACTION_TYPE_SMAC_SIP 1 48 + 49 + /* IS2 MASK_MODE values */ 50 + #define IS2_ACT_MASK_MODE_NONE 0 51 + #define IS2_ACT_MASK_MODE_FILTER 1 52 + #define IS2_ACT_MASK_MODE_POLICY 2 53 + #define IS2_ACT_MASK_MODE_REDIR 3 54 + 55 + /* IS2 REW_OP values */ 56 + #define IS2_ACT_REW_OP_NONE 0 57 + #define IS2_ACT_REW_OP_PTP_ONE 2 58 + #define IS2_ACT_REW_OP_PTP_TWO 3 59 + #define IS2_ACT_REW_OP_SPECIAL 8 60 + #define IS2_ACT_REW_OP_PTP_ORG 9 61 + #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3)) 62 + #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3)) 63 + #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5)) 64 + #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7) 65 + 66 + #define VCAP_PORT_WIDTH 4 67 + 68 + /* IS2 quarter key - SMAC_SIP4 */ 69 + #define IS2_QKO_IGR_PORT 0 70 + #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH 71 + #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT) 72 + #define IS2_QKL_L2_SMAC 48 73 + #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC) 74 + #define IS2_QKL_L3_IP4_SIP 32 75 + 76 + /* IS2 half key - common */ 77 + #define IS2_HKO_TYPE 0 78 + #define IS2_HKL_TYPE 4 79 + #define IS2_HKO_FIRST (IS2_HKO_TYPE + IS2_HKL_TYPE) 80 + #define IS2_HKL_FIRST 1 81 + #define IS2_HKO_PAG (IS2_HKO_FIRST + IS2_HKL_FIRST) 82 + #define IS2_HKL_PAG 8 83 + #define IS2_HKO_IGR_PORT_MASK (IS2_HKO_PAG + IS2_HKL_PAG) 84 + #define IS2_HKL_IGR_PORT_MASK (VCAP_PORT_CNT + 1) 85 + #define IS2_HKO_SERVICE_FRM (IS2_HKO_IGR_PORT_MASK + IS2_HKL_IGR_PORT_MASK) 86 + #define IS2_HKL_SERVICE_FRM 1 87 + #define IS2_HKO_HOST_MATCH (IS2_HKO_SERVICE_FRM + IS2_HKL_SERVICE_FRM) 88 + #define IS2_HKL_HOST_MATCH 1 89 + #define IS2_HKO_L2_MC (IS2_HKO_HOST_MATCH + IS2_HKL_HOST_MATCH) 90 + #define IS2_HKL_L2_MC 1 91 + #define IS2_HKO_L2_BC (IS2_HKO_L2_MC + IS2_HKL_L2_MC) 92 + #define IS2_HKL_L2_BC 1 93 + #define IS2_HKO_VLAN_TAGGED (IS2_HKO_L2_BC + IS2_HKL_L2_BC) 94 + #define IS2_HKL_VLAN_TAGGED 1 95 + #define IS2_HKO_VID (IS2_HKO_VLAN_TAGGED + IS2_HKL_VLAN_TAGGED) 96 + #define IS2_HKL_VID 12 97 + #define IS2_HKO_DEI (IS2_HKO_VID + IS2_HKL_VID) 98 + #define IS2_HKL_DEI 1 99 + #define IS2_HKO_PCP (IS2_HKO_DEI + IS2_HKL_DEI) 100 + #define IS2_HKL_PCP 3 101 + 102 + /* IS2 half key - MAC_ETYPE/MAC_LLC/MAC_SNAP/OAM common */ 103 + #define IS2_HKO_L2_DMAC (IS2_HKO_PCP + IS2_HKL_PCP) 104 + #define IS2_HKL_L2_DMAC 48 105 + #define IS2_HKO_L2_SMAC (IS2_HKO_L2_DMAC + IS2_HKL_L2_DMAC) 106 + #define IS2_HKL_L2_SMAC 48 107 + 108 + /* IS2 half key - MAC_ETYPE */ 109 + #define IS2_HKO_MAC_ETYPE_ETYPE (IS2_HKO_L2_SMAC + IS2_HKL_L2_SMAC) 110 + #define IS2_HKL_MAC_ETYPE_ETYPE 16 111 + #define IS2_HKO_MAC_ETYPE_L2_PAYLOAD \ 112 + (IS2_HKO_MAC_ETYPE_ETYPE + IS2_HKL_MAC_ETYPE_ETYPE) 113 + #define IS2_HKL_MAC_ETYPE_L2_PAYLOAD 27 114 + 115 + /* IS2 half key - MAC_LLC */ 116 + #define IS2_HKO_MAC_LLC_L2_LLC IS2_HKO_MAC_ETYPE_ETYPE 117 + #define IS2_HKL_MAC_LLC_L2_LLC 40 118 + 119 + /* IS2 half key - MAC_SNAP */ 120 + #define IS2_HKO_MAC_SNAP_L2_SNAP IS2_HKO_MAC_ETYPE_ETYPE 121 + #define IS2_HKL_MAC_SNAP_L2_SNAP 40 122 + 123 + /* IS2 half key - ARP */ 124 + #define IS2_HKO_MAC_ARP_L2_SMAC IS2_HKO_L2_DMAC 125 + #define IS2_HKL_MAC_ARP_L2_SMAC 48 126 + #define IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK \ 127 + (IS2_HKO_MAC_ARP_L2_SMAC + IS2_HKL_MAC_ARP_L2_SMAC) 128 + #define IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK 1 129 + #define IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK \ 130 + (IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK + IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK) 131 + #define IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK 1 132 + #define IS2_HKO_MAC_ARP_ARP_LEN_OK \ 133 + (IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK + \ 134 + IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK) 135 + #define IS2_HKL_MAC_ARP_ARP_LEN_OK 1 136 + #define IS2_HKO_MAC_ARP_ARP_TGT_MATCH \ 137 + (IS2_HKO_MAC_ARP_ARP_LEN_OK + IS2_HKL_MAC_ARP_ARP_LEN_OK) 138 + #define IS2_HKL_MAC_ARP_ARP_TGT_MATCH 1 139 + #define IS2_HKO_MAC_ARP_ARP_SENDER_MATCH \ 140 + (IS2_HKO_MAC_ARP_ARP_TGT_MATCH + IS2_HKL_MAC_ARP_ARP_TGT_MATCH) 141 + #define IS2_HKL_MAC_ARP_ARP_SENDER_MATCH 1 142 + #define IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN \ 143 + (IS2_HKO_MAC_ARP_ARP_SENDER_MATCH + IS2_HKL_MAC_ARP_ARP_SENDER_MATCH) 144 + #define IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN 1 145 + #define IS2_HKO_MAC_ARP_ARP_OPCODE \ 146 + (IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN + \ 147 + IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN) 148 + #define IS2_HKL_MAC_ARP_ARP_OPCODE 2 149 + #define IS2_HKO_MAC_ARP_L3_IP4_DIP \ 150 + (IS2_HKO_MAC_ARP_ARP_OPCODE + IS2_HKL_MAC_ARP_ARP_OPCODE) 151 + #define IS2_HKL_MAC_ARP_L3_IP4_DIP 32 152 + #define IS2_HKO_MAC_ARP_L3_IP4_SIP \ 153 + (IS2_HKO_MAC_ARP_L3_IP4_DIP + IS2_HKL_MAC_ARP_L3_IP4_DIP) 154 + #define IS2_HKL_MAC_ARP_L3_IP4_SIP 32 155 + #define IS2_HKO_MAC_ARP_DIP_EQ_SIP \ 156 + (IS2_HKO_MAC_ARP_L3_IP4_SIP + IS2_HKL_MAC_ARP_L3_IP4_SIP) 157 + #define IS2_HKL_MAC_ARP_DIP_EQ_SIP 1 158 + 159 + /* IS2 half key - IP4_TCP_UDP/IP4_OTHER common */ 160 + #define IS2_HKO_IP4 IS2_HKO_L2_DMAC 161 + #define IS2_HKL_IP4 1 162 + #define IS2_HKO_L3_FRAGMENT (IS2_HKO_IP4 + IS2_HKL_IP4) 163 + #define IS2_HKL_L3_FRAGMENT 1 164 + #define IS2_HKO_L3_FRAG_OFS_GT0 (IS2_HKO_L3_FRAGMENT + IS2_HKL_L3_FRAGMENT) 165 + #define IS2_HKL_L3_FRAG_OFS_GT0 1 166 + #define IS2_HKO_L3_OPTIONS (IS2_HKO_L3_FRAG_OFS_GT0 + IS2_HKL_L3_FRAG_OFS_GT0) 167 + #define IS2_HKL_L3_OPTIONS 1 168 + #define IS2_HKO_L3_TTL_GT0 (IS2_HKO_L3_OPTIONS + IS2_HKL_L3_OPTIONS) 169 + #define IS2_HKL_L3_TTL_GT0 1 170 + #define IS2_HKO_L3_TOS (IS2_HKO_L3_TTL_GT0 + IS2_HKL_L3_TTL_GT0) 171 + #define IS2_HKL_L3_TOS 8 172 + #define IS2_HKO_L3_IP4_DIP (IS2_HKO_L3_TOS + IS2_HKL_L3_TOS) 173 + #define IS2_HKL_L3_IP4_DIP 32 174 + #define IS2_HKO_L3_IP4_SIP (IS2_HKO_L3_IP4_DIP + IS2_HKL_L3_IP4_DIP) 175 + #define IS2_HKL_L3_IP4_SIP 32 176 + #define IS2_HKO_DIP_EQ_SIP (IS2_HKO_L3_IP4_SIP + IS2_HKL_L3_IP4_SIP) 177 + #define IS2_HKL_DIP_EQ_SIP 1 178 + 179 + /* IS2 half key - IP4_TCP_UDP */ 180 + #define IS2_HKO_IP4_TCP_UDP_TCP (IS2_HKO_DIP_EQ_SIP + IS2_HKL_DIP_EQ_SIP) 181 + #define IS2_HKL_IP4_TCP_UDP_TCP 1 182 + #define IS2_HKO_IP4_TCP_UDP_L4_DPORT \ 183 + (IS2_HKO_IP4_TCP_UDP_TCP + IS2_HKL_IP4_TCP_UDP_TCP) 184 + #define IS2_HKL_IP4_TCP_UDP_L4_DPORT 16 185 + #define IS2_HKO_IP4_TCP_UDP_L4_SPORT \ 186 + (IS2_HKO_IP4_TCP_UDP_L4_DPORT + IS2_HKL_IP4_TCP_UDP_L4_DPORT) 187 + #define IS2_HKL_IP4_TCP_UDP_L4_SPORT 16 188 + #define IS2_HKO_IP4_TCP_UDP_L4_RNG \ 189 + (IS2_HKO_IP4_TCP_UDP_L4_SPORT + IS2_HKL_IP4_TCP_UDP_L4_SPORT) 190 + #define IS2_HKL_IP4_TCP_UDP_L4_RNG 8 191 + #define IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT \ 192 + (IS2_HKO_IP4_TCP_UDP_L4_RNG + IS2_HKL_IP4_TCP_UDP_L4_RNG) 193 + #define IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT 1 194 + #define IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0 \ 195 + (IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT + \ 196 + IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT) 197 + #define IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0 1 198 + #define IS2_HKO_IP4_TCP_UDP_L4_FIN \ 199 + (IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0 + IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0) 200 + #define IS2_HKL_IP4_TCP_UDP_L4_FIN 1 201 + #define IS2_HKO_IP4_TCP_UDP_L4_SYN \ 202 + (IS2_HKO_IP4_TCP_UDP_L4_FIN + IS2_HKL_IP4_TCP_UDP_L4_FIN) 203 + #define IS2_HKL_IP4_TCP_UDP_L4_SYN 1 204 + #define IS2_HKO_IP4_TCP_UDP_L4_RST \ 205 + (IS2_HKO_IP4_TCP_UDP_L4_SYN + IS2_HKL_IP4_TCP_UDP_L4_SYN) 206 + #define IS2_HKL_IP4_TCP_UDP_L4_RST 1 207 + #define IS2_HKO_IP4_TCP_UDP_L4_PSH \ 208 + (IS2_HKO_IP4_TCP_UDP_L4_RST + IS2_HKL_IP4_TCP_UDP_L4_RST) 209 + #define IS2_HKL_IP4_TCP_UDP_L4_PSH 1 210 + #define IS2_HKO_IP4_TCP_UDP_L4_ACK \ 211 + (IS2_HKO_IP4_TCP_UDP_L4_PSH + IS2_HKL_IP4_TCP_UDP_L4_PSH) 212 + #define IS2_HKL_IP4_TCP_UDP_L4_ACK 1 213 + #define IS2_HKO_IP4_TCP_UDP_L4_URG \ 214 + (IS2_HKO_IP4_TCP_UDP_L4_ACK + IS2_HKL_IP4_TCP_UDP_L4_ACK) 215 + #define IS2_HKL_IP4_TCP_UDP_L4_URG 1 216 + #define IS2_HKO_IP4_TCP_UDP_L4_1588_DOM \ 217 + (IS2_HKO_IP4_TCP_UDP_L4_URG + IS2_HKL_IP4_TCP_UDP_L4_URG) 218 + #define IS2_HKL_IP4_TCP_UDP_L4_1588_DOM 8 219 + #define IS2_HKO_IP4_TCP_UDP_L4_1588_VER \ 220 + (IS2_HKO_IP4_TCP_UDP_L4_1588_DOM + IS2_HKL_IP4_TCP_UDP_L4_1588_DOM) 221 + #define IS2_HKL_IP4_TCP_UDP_L4_1588_VER 4 222 + 223 + /* IS2 half key - IP4_OTHER */ 224 + #define IS2_HKO_IP4_OTHER_L3_PROTO IS2_HKO_IP4_TCP_UDP_TCP 225 + #define IS2_HKL_IP4_OTHER_L3_PROTO 8 226 + #define IS2_HKO_IP4_OTHER_L3_PAYLOAD \ 227 + (IS2_HKO_IP4_OTHER_L3_PROTO + IS2_HKL_IP4_OTHER_L3_PROTO) 228 + #define IS2_HKL_IP4_OTHER_L3_PAYLOAD 56 229 + 230 + /* IS2 half key - IP6_STD */ 231 + #define IS2_HKO_IP6_STD_L3_TTL_GT0 IS2_HKO_L2_DMAC 232 + #define IS2_HKL_IP6_STD_L3_TTL_GT0 1 233 + #define IS2_HKO_IP6_STD_L3_IP6_SIP \ 234 + (IS2_HKO_IP6_STD_L3_TTL_GT0 + IS2_HKL_IP6_STD_L3_TTL_GT0) 235 + #define IS2_HKL_IP6_STD_L3_IP6_SIP 128 236 + #define IS2_HKO_IP6_STD_L3_PROTO \ 237 + (IS2_HKO_IP6_STD_L3_IP6_SIP + IS2_HKL_IP6_STD_L3_IP6_SIP) 238 + #define IS2_HKL_IP6_STD_L3_PROTO 8 239 + 240 + /* IS2 half key - OAM */ 241 + #define IS2_HKO_OAM_OAM_MEL_FLAGS IS2_HKO_MAC_ETYPE_ETYPE 242 + #define IS2_HKL_OAM_OAM_MEL_FLAGS 7 243 + #define IS2_HKO_OAM_OAM_VER \ 244 + (IS2_HKO_OAM_OAM_MEL_FLAGS + IS2_HKL_OAM_OAM_MEL_FLAGS) 245 + #define IS2_HKL_OAM_OAM_VER 5 246 + #define IS2_HKO_OAM_OAM_OPCODE (IS2_HKO_OAM_OAM_VER + IS2_HKL_OAM_OAM_VER) 247 + #define IS2_HKL_OAM_OAM_OPCODE 8 248 + #define IS2_HKO_OAM_OAM_FLAGS (IS2_HKO_OAM_OAM_OPCODE + IS2_HKL_OAM_OAM_OPCODE) 249 + #define IS2_HKL_OAM_OAM_FLAGS 8 250 + #define IS2_HKO_OAM_OAM_MEPID (IS2_HKO_OAM_OAM_FLAGS + IS2_HKL_OAM_OAM_FLAGS) 251 + #define IS2_HKL_OAM_OAM_MEPID 16 252 + #define IS2_HKO_OAM_OAM_CCM_CNTS_EQ0 \ 253 + (IS2_HKO_OAM_OAM_MEPID + IS2_HKL_OAM_OAM_MEPID) 254 + #define IS2_HKL_OAM_OAM_CCM_CNTS_EQ0 1 255 + 256 + /* IS2 half key - SMAC_SIP6 */ 257 + #define IS2_HKO_SMAC_SIP6_IGR_PORT IS2_HKL_TYPE 258 + #define IS2_HKL_SMAC_SIP6_IGR_PORT VCAP_PORT_WIDTH 259 + #define IS2_HKO_SMAC_SIP6_L2_SMAC \ 260 + (IS2_HKO_SMAC_SIP6_IGR_PORT + IS2_HKL_SMAC_SIP6_IGR_PORT) 261 + #define IS2_HKL_SMAC_SIP6_L2_SMAC 48 262 + #define IS2_HKO_SMAC_SIP6_L3_IP6_SIP \ 263 + (IS2_HKO_SMAC_SIP6_L2_SMAC + IS2_HKL_SMAC_SIP6_L2_SMAC) 264 + #define IS2_HKL_SMAC_SIP6_L3_IP6_SIP 128 265 + 266 + /* IS2 full key - common */ 267 + #define IS2_FKO_TYPE 0 268 + #define IS2_FKL_TYPE 2 269 + #define IS2_FKO_FIRST (IS2_FKO_TYPE + IS2_FKL_TYPE) 270 + #define IS2_FKL_FIRST 1 271 + #define IS2_FKO_PAG (IS2_FKO_FIRST + IS2_FKL_FIRST) 272 + #define IS2_FKL_PAG 8 273 + #define IS2_FKO_IGR_PORT_MASK (IS2_FKO_PAG + IS2_FKL_PAG) 274 + #define IS2_FKL_IGR_PORT_MASK (VCAP_PORT_CNT + 1) 275 + #define IS2_FKO_SERVICE_FRM (IS2_FKO_IGR_PORT_MASK + IS2_FKL_IGR_PORT_MASK) 276 + #define IS2_FKL_SERVICE_FRM 1 277 + #define IS2_FKO_HOST_MATCH (IS2_FKO_SERVICE_FRM + IS2_FKL_SERVICE_FRM) 278 + #define IS2_FKL_HOST_MATCH 1 279 + #define IS2_FKO_L2_MC (IS2_FKO_HOST_MATCH + IS2_FKL_HOST_MATCH) 280 + #define IS2_FKL_L2_MC 1 281 + #define IS2_FKO_L2_BC (IS2_FKO_L2_MC + IS2_FKL_L2_MC) 282 + #define IS2_FKL_L2_BC 1 283 + #define IS2_FKO_VLAN_TAGGED (IS2_FKO_L2_BC + IS2_FKL_L2_BC) 284 + #define IS2_FKL_VLAN_TAGGED 1 285 + #define IS2_FKO_VID (IS2_FKO_VLAN_TAGGED + IS2_FKL_VLAN_TAGGED) 286 + #define IS2_FKL_VID 12 287 + #define IS2_FKO_DEI (IS2_FKO_VID + IS2_FKL_VID) 288 + #define IS2_FKL_DEI 1 289 + #define IS2_FKO_PCP (IS2_FKO_DEI + IS2_FKL_DEI) 290 + #define IS2_FKL_PCP 3 291 + 292 + /* IS2 full key - IP6_TCP_UDP/IP6_OTHER common */ 293 + #define IS2_FKO_L3_TTL_GT0 (IS2_FKO_PCP + IS2_FKL_PCP) 294 + #define IS2_FKL_L3_TTL_GT0 1 295 + #define IS2_FKO_L3_TOS (IS2_FKO_L3_TTL_GT0 + IS2_FKL_L3_TTL_GT0) 296 + #define IS2_FKL_L3_TOS 8 297 + #define IS2_FKO_L3_IP6_DIP (IS2_FKO_L3_TOS + IS2_FKL_L3_TOS) 298 + #define IS2_FKL_L3_IP6_DIP 128 299 + #define IS2_FKO_L3_IP6_SIP (IS2_FKO_L3_IP6_DIP + IS2_FKL_L3_IP6_DIP) 300 + #define IS2_FKL_L3_IP6_SIP 128 301 + #define IS2_FKO_DIP_EQ_SIP (IS2_FKO_L3_IP6_SIP + IS2_FKL_L3_IP6_SIP) 302 + #define IS2_FKL_DIP_EQ_SIP 1 303 + 304 + /* IS2 full key - IP6_TCP_UDP */ 305 + #define IS2_FKO_IP6_TCP_UDP_TCP (IS2_FKO_DIP_EQ_SIP + IS2_FKL_DIP_EQ_SIP) 306 + #define IS2_FKL_IP6_TCP_UDP_TCP 1 307 + #define IS2_FKO_IP6_TCP_UDP_L4_DPORT \ 308 + (IS2_FKO_IP6_TCP_UDP_TCP + IS2_FKL_IP6_TCP_UDP_TCP) 309 + #define IS2_FKL_IP6_TCP_UDP_L4_DPORT 16 310 + #define IS2_FKO_IP6_TCP_UDP_L4_SPORT \ 311 + (IS2_FKO_IP6_TCP_UDP_L4_DPORT + IS2_FKL_IP6_TCP_UDP_L4_DPORT) 312 + #define IS2_FKL_IP6_TCP_UDP_L4_SPORT 16 313 + #define IS2_FKO_IP6_TCP_UDP_L4_RNG \ 314 + (IS2_FKO_IP6_TCP_UDP_L4_SPORT + IS2_FKL_IP6_TCP_UDP_L4_SPORT) 315 + #define IS2_FKL_IP6_TCP_UDP_L4_RNG 8 316 + #define IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT \ 317 + (IS2_FKO_IP6_TCP_UDP_L4_RNG + IS2_FKL_IP6_TCP_UDP_L4_RNG) 318 + #define IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT 1 319 + #define IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0 \ 320 + (IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT + \ 321 + IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT) 322 + #define IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0 1 323 + #define IS2_FKO_IP6_TCP_UDP_L4_FIN \ 324 + (IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0 + IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0) 325 + #define IS2_FKL_IP6_TCP_UDP_L4_FIN 1 326 + #define IS2_FKO_IP6_TCP_UDP_L4_SYN \ 327 + (IS2_FKO_IP6_TCP_UDP_L4_FIN + IS2_FKL_IP6_TCP_UDP_L4_FIN) 328 + #define IS2_FKL_IP6_TCP_UDP_L4_SYN 1 329 + #define IS2_FKO_IP6_TCP_UDP_L4_RST \ 330 + (IS2_FKO_IP6_TCP_UDP_L4_SYN + IS2_FKL_IP6_TCP_UDP_L4_SYN) 331 + #define IS2_FKL_IP6_TCP_UDP_L4_RST 1 332 + #define IS2_FKO_IP6_TCP_UDP_L4_PSH \ 333 + (IS2_FKO_IP6_TCP_UDP_L4_RST + IS2_FKL_IP6_TCP_UDP_L4_RST) 334 + #define IS2_FKL_IP6_TCP_UDP_L4_PSH 1 335 + #define IS2_FKO_IP6_TCP_UDP_L4_ACK \ 336 + (IS2_FKO_IP6_TCP_UDP_L4_PSH + IS2_FKL_IP6_TCP_UDP_L4_PSH) 337 + #define IS2_FKL_IP6_TCP_UDP_L4_ACK 1 338 + #define IS2_FKO_IP6_TCP_UDP_L4_URG \ 339 + (IS2_FKO_IP6_TCP_UDP_L4_ACK + IS2_FKL_IP6_TCP_UDP_L4_ACK) 340 + #define IS2_FKL_IP6_TCP_UDP_L4_URG 1 341 + #define IS2_FKO_IP6_TCP_UDP_L4_1588_DOM \ 342 + (IS2_FKO_IP6_TCP_UDP_L4_URG + IS2_FKL_IP6_TCP_UDP_L4_URG) 343 + #define IS2_FKL_IP6_TCP_UDP_L4_1588_DOM 8 344 + #define IS2_FKO_IP6_TCP_UDP_L4_1588_VER \ 345 + (IS2_FKO_IP6_TCP_UDP_L4_1588_DOM + IS2_FKL_IP6_TCP_UDP_L4_1588_DOM) 346 + #define IS2_FKL_IP6_TCP_UDP_L4_1588_VER 4 347 + 348 + /* IS2 full key - IP6_OTHER */ 349 + #define IS2_FKO_IP6_OTHER_L3_PROTO IS2_FKO_IP6_TCP_UDP_TCP 350 + #define IS2_FKL_IP6_OTHER_L3_PROTO 8 351 + #define IS2_FKO_IP6_OTHER_L3_PAYLOAD \ 352 + (IS2_FKO_IP6_OTHER_L3_PROTO + IS2_FKL_IP6_OTHER_L3_PROTO) 353 + #define IS2_FKL_IP6_OTHER_L3_PAYLOAD 56 354 + 355 + /* IS2 full key - CUSTOM */ 356 + #define IS2_FKO_CUSTOM_CUSTOM_TYPE IS2_FKO_L3_TTL_GT0 357 + #define IS2_FKL_CUSTOM_CUSTOM_TYPE 1 358 + #define IS2_FKO_CUSTOM_CUSTOM \ 359 + (IS2_FKO_CUSTOM_CUSTOM_TYPE + IS2_FKL_CUSTOM_CUSTOM_TYPE) 360 + #define IS2_FKL_CUSTOM_CUSTOM 320 361 + 362 + /* IS2 action - BASE_TYPE */ 363 + #define IS2_AO_HIT_ME_ONCE 0 364 + #define IS2_AL_HIT_ME_ONCE 1 365 + #define IS2_AO_CPU_COPY_ENA (IS2_AO_HIT_ME_ONCE + IS2_AL_HIT_ME_ONCE) 366 + #define IS2_AL_CPU_COPY_ENA 1 367 + #define IS2_AO_CPU_QU_NUM (IS2_AO_CPU_COPY_ENA + IS2_AL_CPU_COPY_ENA) 368 + #define IS2_AL_CPU_QU_NUM 3 369 + #define IS2_AO_MASK_MODE (IS2_AO_CPU_QU_NUM + IS2_AL_CPU_QU_NUM) 370 + #define IS2_AL_MASK_MODE 2 371 + #define IS2_AO_MIRROR_ENA (IS2_AO_MASK_MODE + IS2_AL_MASK_MODE) 372 + #define IS2_AL_MIRROR_ENA 1 373 + #define IS2_AO_LRN_DIS (IS2_AO_MIRROR_ENA + IS2_AL_MIRROR_ENA) 374 + #define IS2_AL_LRN_DIS 1 375 + #define IS2_AO_POLICE_ENA (IS2_AO_LRN_DIS + IS2_AL_LRN_DIS) 376 + #define IS2_AL_POLICE_ENA 1 377 + #define IS2_AO_POLICE_IDX (IS2_AO_POLICE_ENA + IS2_AL_POLICE_ENA) 378 + #define IS2_AL_POLICE_IDX 9 379 + #define IS2_AO_POLICE_VCAP_ONLY (IS2_AO_POLICE_IDX + IS2_AL_POLICE_IDX) 380 + #define IS2_AL_POLICE_VCAP_ONLY 1 381 + #define IS2_AO_PORT_MASK (IS2_AO_POLICE_VCAP_ONLY + IS2_AL_POLICE_VCAP_ONLY) 382 + #define IS2_AL_PORT_MASK VCAP_PORT_CNT 383 + #define IS2_AO_REW_OP (IS2_AO_PORT_MASK + IS2_AL_PORT_MASK) 384 + #define IS2_AL_REW_OP 9 385 + #define IS2_AO_LM_CNT_DIS (IS2_AO_REW_OP + IS2_AL_REW_OP) 386 + #define IS2_AL_LM_CNT_DIS 1 387 + #define IS2_AO_ISDX_ENA \ 388 + (IS2_AO_LM_CNT_DIS + IS2_AL_LM_CNT_DIS + 1) /* Reserved bit */ 389 + #define IS2_AL_ISDX_ENA 1 390 + #define IS2_AO_ACL_ID (IS2_AO_ISDX_ENA + IS2_AL_ISDX_ENA) 391 + #define IS2_AL_ACL_ID 6 392 + 393 + /* IS2 action - SMAC_SIP */ 394 + #define IS2_AO_SMAC_SIP_CPU_COPY_ENA 0 395 + #define IS2_AL_SMAC_SIP_CPU_COPY_ENA 1 396 + #define IS2_AO_SMAC_SIP_CPU_QU_NUM 1 397 + #define IS2_AL_SMAC_SIP_CPU_QU_NUM 3 398 + #define IS2_AO_SMAC_SIP_FWD_KILL_ENA 4 399 + #define IS2_AL_SMAC_SIP_FWD_KILL_ENA 1 400 + #define IS2_AO_SMAC_SIP_HOST_MATCH 5 401 + #define IS2_AL_SMAC_SIP_HOST_MATCH 1 402 + 403 + #endif /* _OCELOT_VCAP_H_ */