drm/amdgpu: update gc_12_0_0 headers · tjh.dev/kernel@b592d01

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

drm/amdgpu: update gc_12_0_0 headers

Add some additional registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 2 years ago b592d01d 73e1d104

+106

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

gc_12_0_0_offset.h

gc_12_0_0_sh_mask.h

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h

··· 85 85 #define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 86 86 #define regSDMA0_ATOMIC_PREOP_HI 0x0033 87 87 #define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 88 + #define regSDMA0_DCC_CNTL 0x0034 89 + #define regSDMA0_DCC_CNTL_BASE_IDX 0 88 90 #define regSDMA0_UTCL1_CNTL 0x0035 89 91 #define regSDMA0_UTCL1_CNTL_BASE_IDX 0 90 92 #define regSDMA0_UTCL1_WATERMK 0x0036 ··· 1067 1065 #define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 1068 1066 #define regSDMA1_ATOMIC_PREOP_HI 0x0633 1069 1067 #define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 1068 + #define regSDMA1_DCC_CNTL 0x0634 1069 + #define regSDMA1_DCC_CNTL_BASE_IDX 0 1070 1070 #define regSDMA1_UTCL1_CNTL 0x0635 1071 1071 #define regSDMA1_UTCL1_CNTL_BASE_IDX 0 1072 1072 #define regSDMA1_UTCL1_WATERMK 0x0636 ··· 5527 5523 #define regCHC_CTRL_BASE_IDX 1 5528 5524 #define regCHC_STATUS 0x2dc1 5529 5525 #define regCHC_STATUS_BASE_IDX 1 5526 + #define regCHC_CTRL2 0x2dc2 5527 + #define regCHC_CTRL2_BASE_IDX 1 5528 + #define regCHC_STATUS2 0x2dc3 5529 + #define regCHC_STATUS2_BASE_IDX 1 5530 5530 5531 5531 5532 5532 // addressBlock: gc_gfx_cpwd_cpwd_gl2dec

+98

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

··· 330 330 //SDMA0_ATOMIC_PREOP_HI 331 331 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 332 332 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 333 + //SDMA0_DCC_CNTL 334 + #define SDMA0_DCC_CNTL__DCC_FORCE_BYPASS__SHIFT 0x0 335 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0__SHIFT 0x1 336 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0__SHIFT 0x2 337 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0__SHIFT 0x3 338 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0__SHIFT 0x4 339 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1__SHIFT 0x5 340 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1__SHIFT 0x6 341 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1__SHIFT 0x7 342 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1__SHIFT 0x8 343 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2__SHIFT 0x9 344 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2__SHIFT 0xa 345 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2__SHIFT 0xb 346 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2__SHIFT 0xc 347 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3__SHIFT 0xd 348 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3__SHIFT 0xe 349 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3__SHIFT 0xf 350 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3__SHIFT 0x10 351 + #define SDMA0_DCC_CNTL__DCC_FORCE_BYPASS_MASK 0x00000001L 352 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0_MASK 0x00000002L 353 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0_MASK 0x00000004L 354 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0_MASK 0x00000008L 355 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0_MASK 0x00000010L 356 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1_MASK 0x00000020L 357 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1_MASK 0x00000040L 358 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1_MASK 0x00000080L 359 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1_MASK 0x00000100L 360 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2_MASK 0x00000200L 361 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2_MASK 0x00000400L 362 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2_MASK 0x00000800L 363 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2_MASK 0x00001000L 364 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3_MASK 0x00002000L 365 + #define SDMA0_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3_MASK 0x00004000L 366 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3_MASK 0x00008000L 367 + #define SDMA0_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3_MASK 0x00010000L 333 368 //SDMA0_UTCL1_CNTL 334 369 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 335 370 #define SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 ··· 3239 3204 //SDMA1_ATOMIC_PREOP_HI 3240 3205 #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 3241 3206 #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 3207 + //SDMA1_DCC_CNTL 3208 + #define SDMA1_DCC_CNTL__DCC_FORCE_BYPASS__SHIFT 0x0 3209 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0__SHIFT 0x1 3210 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0__SHIFT 0x2 3211 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0__SHIFT 0x3 3212 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0__SHIFT 0x4 3213 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1__SHIFT 0x5 3214 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1__SHIFT 0x6 3215 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1__SHIFT 0x7 3216 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1__SHIFT 0x8 3217 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2__SHIFT 0x9 3218 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2__SHIFT 0xa 3219 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2__SHIFT 0xb 3220 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2__SHIFT 0xc 3221 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3__SHIFT 0xd 3222 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3__SHIFT 0xe 3223 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3__SHIFT 0xf 3224 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3__SHIFT 0x10 3225 + #define SDMA1_DCC_CNTL__DCC_FORCE_BYPASS_MASK 0x00000001L 3226 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0_MASK 0x00000002L 3227 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0_MASK 0x00000004L 3228 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0_MASK 0x00000008L 3229 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0_MASK 0x00000010L 3230 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1_MASK 0x00000020L 3231 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1_MASK 0x00000040L 3232 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1_MASK 0x00000080L 3233 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1_MASK 0x00000100L 3234 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2_MASK 0x00000200L 3235 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2_MASK 0x00000400L 3236 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2_MASK 0x00000800L 3237 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2_MASK 0x00001000L 3238 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3_MASK 0x00002000L 3239 + #define SDMA1_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3_MASK 0x00004000L 3240 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3_MASK 0x00008000L 3241 + #define SDMA1_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3_MASK 0x00010000L 3242 3242 //SDMA1_UTCL1_CNTL 3243 3243 #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 3244 3244 #define SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 ··· 17356 17286 #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00400000L 17357 17287 #define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00800000L 17358 17288 #define CHC_STATUS__BUFFER_FULL_MASK 0x01000000L 17289 + //CHC_CTRL2 17290 + #define CHC_CTRL2__DCC_COMP_TO_CONSTANT_EN__SHIFT 0x0 17291 + #define CHC_CTRL2__DCC_COMP_TO_SINGLE_EN__SHIFT 0x1 17292 + #define CHC_CTRL2__DCC_CLEAR_ERRORS__SHIFT 0x6 17293 + #define CHC_CTRL2__DCC_COMP_TRANSFER_SIZE_ENABLE__SHIFT 0x7 17294 + #define CHC_CTRL2__DCC_COMP_SKIP_LOW_COMP_RATIOS__SHIFT 0xa 17295 + #define CHC_CTRL2__DCC_COMPRESSION_DISABLE__SHIFT 0xb 17296 + #define CHC_CTRL2__DF_COMPRESSION_MODE_OVERRIDE__SHIFT 0xc 17297 + #define CHC_CTRL2__OC_OVERRIDE_UNCOMP_LOGICAL_SIZE_DISABLE__SHIFT 0xe 17298 + #define CHC_CTRL2__EA_NACK_DISABLE__SHIFT 0xf 17299 + #define CHC_CTRL2__DCC_FORCE_BYPASS__SHIFT 0x10 17300 + #define CHC_CTRL2__DCC_CLEAR_128B_CONSTANT_ENCODE_EN__SHIFT 0x11 17301 + #define CHC_CTRL2__OC_UNCOMP_128B_COMPRESS_EN_DISABLE__SHIFT 0x12 17302 + #define CHC_CTRL2__DCC_COMP_TO_CONSTANT_EN_MASK 0x00000001L 17303 + #define CHC_CTRL2__DCC_COMP_TO_SINGLE_EN_MASK 0x00000002L 17304 + #define CHC_CTRL2__DCC_CLEAR_ERRORS_MASK 0x00000040L 17305 + #define CHC_CTRL2__DCC_COMP_TRANSFER_SIZE_ENABLE_MASK 0x00000380L 17306 + #define CHC_CTRL2__DCC_COMP_SKIP_LOW_COMP_RATIOS_MASK 0x00000400L 17307 + #define CHC_CTRL2__DCC_COMPRESSION_DISABLE_MASK 0x00000800L 17308 + #define CHC_CTRL2__DF_COMPRESSION_MODE_OVERRIDE_MASK 0x00003000L 17309 + #define CHC_CTRL2__OC_OVERRIDE_UNCOMP_LOGICAL_SIZE_DISABLE_MASK 0x00004000L 17310 + #define CHC_CTRL2__EA_NACK_DISABLE_MASK 0x00008000L 17311 + #define CHC_CTRL2__DCC_FORCE_BYPASS_MASK 0x00010000L 17312 + #define CHC_CTRL2__DCC_CLEAR_128B_CONSTANT_ENCODE_EN_MASK 0x00020000L 17313 + #define CHC_CTRL2__OC_UNCOMP_128B_COMPRESS_EN_DISABLE_MASK 0x00040000L 17314 + //CHC_STATUS2 17315 + #define CHC_STATUS2__DCC_OUT_ERROR_CODE__SHIFT 0x0 17316 + #define CHC_STATUS2__DCC_OUT_ERROR_CODE_MASK 0x00000FFFL 17359 17317 17360 17318 17361 17319 // addressBlock: gc_gfx_cpwd_cpwd_gl2dec