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kernel os linux

mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver

Add binding document for the Cadence QSPI controller.

Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alan Tull <atull@opensource.altera.com>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Graham Moore <grmoore@opensource.altera.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Yves Vandervennet <yvanderv@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>

authored by

Graham Moore and committed by
Brian Norris
b5843991 422485da

+56
+56
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
··· 1 + * Cadence Quad SPI controller 2 + 3 + Required properties: 4 + - compatible : Should be "cdns,qspi-nor". 5 + - reg : Contains two entries, each of which is a tuple consisting of a 6 + physical address and length. The first entry is the address and 7 + length of the controller register set. The second entry is the 8 + address and length of the QSPI Controller data area. 9 + - interrupts : Unit interrupt specifier for the controller interrupt. 10 + - clocks : phandle to the Quad SPI clock. 11 + - cdns,fifo-depth : Size of the data FIFO in words. 12 + - cdns,fifo-width : Bus width of the data FIFO in bytes. 13 + - cdns,trigger-address : 32-bit indirect AHB trigger address. 14 + 15 + Optional properties: 16 + - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. 17 + 18 + Optional subnodes: 19 + Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional 20 + custom properties: 21 + - cdns,read-delay : Delay for read capture logic, in clock cycles 22 + - cdns,tshsl-ns : Delay in nanoseconds for the length that the master 23 + mode chip select outputs are de-asserted between 24 + transactions. 25 + - cdns,tsd2d-ns : Delay in nanoseconds between one chip select being 26 + de-activated and the activation of another. 27 + - cdns,tchsh-ns : Delay in nanoseconds between last bit of current 28 + transaction and deasserting the device chip select 29 + (qspi_n_ss_out). 30 + - cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low 31 + and first bit transfer. 32 + 33 + Example: 34 + 35 + qspi: spi@ff705000 { 36 + compatible = "cdns,qspi-nor"; 37 + #address-cells = <1>; 38 + #size-cells = <0>; 39 + reg = <0xff705000 0x1000>, 40 + <0xffa00000 0x1000>; 41 + interrupts = <0 151 4>; 42 + clocks = <&qspi_clk>; 43 + cdns,is-decoded-cs; 44 + cdns,fifo-depth = <128>; 45 + cdns,fifo-width = <4>; 46 + cdns,trigger-address = <0x00000000>; 47 + 48 + flash0: n25q00@0 { 49 + ... 50 + cdns,read-delay = <4>; 51 + cdns,tshsl-ns = <50>; 52 + cdns,tsd2d-ns = <50>; 53 + cdns,tchsh-ns = <4>; 54 + cdns,tslch-ns = <4>; 55 + }; 56 + };