tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: tegra: apalis_t30: support v1.1 hardware revision
Support the V1.1 hardware revisions with the following change:
Changed power rail for MMC1 interface to a 3.3V/1.8V switchable rail in
order to be able to run UHS SD cards in ultra high speed 1.8V mode.
[ 207.502011] mmc2: host does not support reading read-only switch,
assuming write-enable
[ 207.517011] mmc2: new ultra high speed SDR104 SDHC card at address
aaaa
[ 207.534190] mmcblk2: mmc2:aaaa SE32G 29.7 GiB
[ 207.545096] mmcblk2: p1
root@apalis-t30:~# cat /sys/kernel/debug/mmc2/ios
clock: 208000000 Hz
actual clock: 204000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
root@apalis-t30:~# hdparm -t /dev/mmcblk2
/dev/mmcblk2:
Timing buffered disk reads: 256 MB in 3.02 seconds = 84.71 MB/sec
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Marcel Ziswiler
and committed by
Thierry Reding
b57d6b99
a472e00b
+1459
-2
+2
Documentation/devicetree/bindings/arm/tegra.txt
+2
Documentation/devicetree/bindings/arm/tegra.txt
+1
arch/arm/boot/dts/Makefile
+1
arch/arm/boot/dts/Makefile
+266
arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
+266
arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR MIT
2
+
/dts-v1/;
3
+
4
+
#include <dt-bindings/input/input.h>
5
+
#include "tegra30-apalis-v1.1.dtsi"
6
+
7
+
/ {
8
+
model = "Toradex Apalis T30 on Apalis Evaluation Board";
9
+
compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval",
10
+
"toradex,apalis_t30-v1.1", "toradex,apalis_t30",
11
+
"nvidia,tegra30";
12
+
13
+
aliases {
14
+
rtc0 = "/i2c@7000c000/rtc@68";
15
+
rtc1 = "/i2c@7000d000/pmic@2d";
16
+
rtc2 = "/rtc@7000e000";
17
+
serial0 = &uarta;
18
+
serial1 = &uartb;
19
+
serial2 = &uartc;
20
+
serial3 = &uartd;
21
+
};
22
+
23
+
chosen {
24
+
stdout-path = "serial0:115200n8";
25
+
};
26
+
27
+
pcie@3000 {
28
+
pci@1,0 {
29
+
status = "okay";
30
+
};
31
+
32
+
pci@2,0 {
33
+
status = "okay";
34
+
};
35
+
};
36
+
37
+
host1x@50000000 {
38
+
dc@54200000 {
39
+
rgb {
40
+
status = "okay";
41
+
nvidia,panel = <&panel>;
42
+
};
43
+
};
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+
45
+
hdmi@54280000 {
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+
status = "okay";
47
+
hdmi-supply = <®_5v0>;
48
+
};
49
+
};
50
+
51
+
/* Apalis UART1 */
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+
serial@70006000 {
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+
status = "okay";
54
+
};
55
+
56
+
/* Apalis UART2 */
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+
serial@70006040 {
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+
status = "okay";
59
+
};
60
+
61
+
/* Apalis UART3 */
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+
serial@70006200 {
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+
status = "okay";
64
+
};
65
+
66
+
/* Apalis UART4 */
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+
serial@70006300 {
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+
status = "okay";
69
+
};
70
+
71
+
pwm@7000a000 {
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+
status = "okay";
73
+
};
74
+
75
+
/*
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+
* GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
77
+
* board)
78
+
*/
79
+
i2c@7000c000 {
80
+
status = "okay";
81
+
clock-frequency = <400000>;
82
+
83
+
pcie-switch@58 {
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+
compatible = "plx,pex8605";
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+
reg = <0x58>;
86
+
};
87
+
88
+
/* M41T0M6 real time clock on carrier board */
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+
rtc@68 {
90
+
compatible = "st,m41t0";
91
+
reg = <0x68>;
92
+
};
93
+
};
94
+
95
+
/* GEN2_I2C: unused */
96
+
97
+
/*
98
+
* CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
99
+
* carrier board)
100
+
*/
101
+
i2c@7000c500 {
102
+
status = "okay";
103
+
clock-frequency = <400000>;
104
+
};
105
+
106
+
/* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
107
+
i2c@7000c700 {
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+
status = "okay";
109
+
};
110
+
111
+
/* SPI1: Apalis SPI1 */
112
+
spi@7000d400 {
113
+
status = "okay";
114
+
spi-max-frequency = <25000000>;
115
+
};
116
+
117
+
/* SPI5: Apalis SPI2 */
118
+
spi@7000dc00 {
119
+
status = "okay";
120
+
spi-max-frequency = <25000000>;
121
+
};
122
+
123
+
/* Apalis SD1 */
124
+
sdhci@78000000 {
125
+
status = "okay";
126
+
bus-width = <4>;
127
+
/* SD1_CD# */
128
+
cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
129
+
no-1-8-v;
130
+
};
131
+
132
+
/* Apalis MMC1 */
133
+
sdhci@78000400 {
134
+
status = "okay";
135
+
bus-width = <8>;
136
+
/* MMC1_CD# */
137
+
cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
138
+
vqmmc-supply = <®_vddio_sdmmc3>;
139
+
};
140
+
141
+
/* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
142
+
usb@7d000000 {
143
+
status = "okay";
144
+
dr_mode = "otg";
145
+
};
146
+
147
+
usb-phy@7d000000 {
148
+
status = "okay";
149
+
vbus-supply = <®_usbo1_vbus>;
150
+
};
151
+
152
+
/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
153
+
usb@7d004000 {
154
+
status = "okay";
155
+
};
156
+
157
+
usb-phy@7d004000 {
158
+
status = "okay";
159
+
vbus-supply = <®_usbh_vbus>;
160
+
};
161
+
162
+
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
163
+
usb@7d008000 {
164
+
status = "okay";
165
+
};
166
+
167
+
usb-phy@7d008000 {
168
+
status = "okay";
169
+
vbus-supply = <®_usbh_vbus>;
170
+
};
171
+
172
+
backlight: backlight {
173
+
compatible = "pwm-backlight";
174
+
brightness-levels = <255 231 223 207 191 159 127 0>;
175
+
default-brightness-level = <6>;
176
+
/* BKL1_ON */
177
+
enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
178
+
power-supply = <®_3v3>;
179
+
pwms = <&pwm 0 5000000>; /* BKL1_PWM */
180
+
};
181
+
182
+
gpio-keys {
183
+
compatible = "gpio-keys";
184
+
185
+
wakeup {
186
+
label = "WAKE1_MICO";
187
+
gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
188
+
linux,code = <KEY_WAKEUP>;
189
+
debounce-interval = <10>;
190
+
wakeup-source;
191
+
};
192
+
};
193
+
194
+
panel: panel {
195
+
/*
196
+
* edt,et057090dhu: EDT 5.7" LCD TFT
197
+
* edt,et070080dh6: EDT 7.0" LCD TFT
198
+
*/
199
+
compatible = "edt,et057090dhu", "simple-panel";
200
+
backlight = <&backlight>;
201
+
power-supply = <®_3v3>;
202
+
};
203
+
204
+
reg_3v3: regulator-3v3 {
205
+
compatible = "regulator-fixed";
206
+
regulator-name = "3.3V_SW";
207
+
regulator-min-microvolt = <3300000>;
208
+
regulator-max-microvolt = <3300000>;
209
+
};
210
+
211
+
reg_5v0: regulator-5v0 {
212
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compatible = "regulator-fixed";
213
+
regulator-name = "5V_SW";
214
+
regulator-min-microvolt = <5000000>;
215
+
regulator-max-microvolt = <5000000>;
216
+
};
217
+
218
+
/* USBO1_EN */
219
+
reg_usbo1_vbus: regulator-usbo1-vbus {
220
+
compatible = "regulator-fixed";
221
+
regulator-name = "VCC_USBO1";
222
+
regulator-min-microvolt = <5000000>;
223
+
regulator-max-microvolt = <5000000>;
224
+
gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
225
+
enable-active-high;
226
+
vin-supply = <®_5v0>;
227
+
};
228
+
229
+
/* USBH_EN */
230
+
reg_usbh_vbus: regulator-usbh-vbus {
231
+
compatible = "regulator-fixed";
232
+
regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
233
+
regulator-min-microvolt = <5000000>;
234
+
regulator-max-microvolt = <5000000>;
235
+
gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
236
+
enable-active-high;
237
+
vin-supply = <®_5v0>;
238
+
};
239
+
240
+
/*
241
+
* 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on
242
+
* EN_+3.3_SDMMC3 GPIO
243
+
*/
244
+
reg_vddio_sdmmc3: regulator-vddio-sdmmc3 {
245
+
compatible = "regulator-gpio";
246
+
regulator-name = "VDDIO_SDMMC3";
247
+
regulator-min-microvolt = <1800000>;
248
+
regulator-max-microvolt = <3300000>;
249
+
regulator-type = "voltage";
250
+
gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>;
251
+
states = <1800000 0x0
252
+
3300000 0x1>;
253
+
startup-delay-us = <100000>;
254
+
vin-supply = <&vddio_sdmmc_1v8_reg>;
255
+
};
256
+
};
257
+
258
+
&gpio {
259
+
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
260
+
pex-perst-n {
261
+
gpio-hog;
262
+
gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
263
+
output-high;
264
+
line-name = "PEX_PERST_N";
265
+
};
266
+
};
+1189
arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
+1189
arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR MIT
2
+
#include "tegra30.dtsi"
3
+
4
+
/*
5
+
* Toradex Apalis T30 Module Device Tree
6
+
* Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B;
7
+
* 2GB: V1.1A, V1.1B
8
+
*/
9
+
/ {
10
+
memory@80000000 {
11
+
reg = <0x80000000 0x40000000>;
12
+
};
13
+
14
+
pcie@3000 {
15
+
status = "okay";
16
+
avdd-pexa-supply = <&vdd2_reg>;
17
+
avdd-pexb-supply = <&vdd2_reg>;
18
+
avdd-pex-pll-supply = <&vdd2_reg>;
19
+
avdd-plle-supply = <&ldo6_reg>;
20
+
hvdd-pex-supply = <®_module_3v3>;
21
+
vddio-pex-ctl-supply = <®_module_3v3>;
22
+
vdd-pexa-supply = <&vdd2_reg>;
23
+
vdd-pexb-supply = <&vdd2_reg>;
24
+
25
+
/* Apalis type specific */
26
+
pci@1,0 {
27
+
nvidia,num-lanes = <4>;
28
+
};
29
+
30
+
/* Apalis PCIe */
31
+
pci@2,0 {
32
+
nvidia,num-lanes = <1>;
33
+
};
34
+
35
+
/* I210/I211 Gigabit Ethernet Controller (on-module) */
36
+
pci@3,0 {
37
+
status = "okay";
38
+
nvidia,num-lanes = <1>;
39
+
40
+
pcie@0 {
41
+
reg = <0 0 0 0 0>;
42
+
local-mac-address = [00 00 00 00 00 00];
43
+
};
44
+
};
45
+
};
46
+
47
+
host1x@50000000 {
48
+
hdmi@54280000 {
49
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
50
+
nvidia,hpd-gpio =
51
+
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
52
+
pll-supply = <®_1v8_avdd_hdmi_pll>;
53
+
vdd-supply = <®_3v3_avdd_hdmi>;
54
+
};
55
+
};
56
+
57
+
pinmux@70000868 {
58
+
pinctrl-names = "default";
59
+
pinctrl-0 = <&state_default>;
60
+
61
+
state_default: pinmux {
62
+
/* Analogue Audio (On-module) */
63
+
clk1-out-pw4 {
64
+
nvidia,pins = "clk1_out_pw4";
65
+
nvidia,function = "extperiph1";
66
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
67
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
68
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
69
+
};
70
+
dap3-fs-pp0 {
71
+
nvidia,pins = "dap3_fs_pp0",
72
+
"dap3_sclk_pp3",
73
+
"dap3_din_pp1",
74
+
"dap3_dout_pp2";
75
+
nvidia,function = "i2s2";
76
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
78
+
};
79
+
80
+
/* Apalis BKL1_ON */
81
+
pv2 {
82
+
nvidia,pins = "pv2";
83
+
nvidia,function = "rsvd4";
84
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
86
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87
+
};
88
+
89
+
/* Apalis BKL1_PWM */
90
+
uart3-rts-n-pc0 {
91
+
nvidia,pins = "uart3_rts_n_pc0";
92
+
nvidia,function = "pwm0";
93
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
95
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
96
+
};
97
+
/* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
98
+
uart3-cts-n-pa1 {
99
+
nvidia,pins = "uart3_cts_n_pa1";
100
+
nvidia,function = "rsvd2";
101
+
nvidia,pull = <TEGRA_PIN_PULL_UP>;
102
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
103
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
104
+
};
105
+
106
+
/* Apalis CAN1 on SPI6 */
107
+
spi2-cs0-n-px3 {
108
+
nvidia,pins = "spi2_cs0_n_px3",
109
+
"spi2_miso_px1",
110
+
"spi2_mosi_px0",
111
+
"spi2_sck_px2";
112
+
nvidia,function = "spi6";
113
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
115
+
};
116
+
/* CAN_INT1 */
117
+
spi2-cs1-n-pw2 {
118
+
nvidia,pins = "spi2_cs1_n_pw2";
119
+
nvidia,function = "spi3";
120
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
121
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
122
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
123
+
};
124
+
125
+
/* Apalis CAN2 on SPI4 */
126
+
gmi-a16-pj7 {
127
+
nvidia,pins = "gmi_a16_pj7",
128
+
"gmi_a17_pb0",
129
+
"gmi_a18_pb1",
130
+
"gmi_a19_pk7";
131
+
nvidia,function = "spi4";
132
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
134
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
135
+
};
136
+
/* CAN_INT2 */
137
+
spi2-cs2-n-pw3 {
138
+
nvidia,pins = "spi2_cs2_n_pw3";
139
+
nvidia,function = "spi3";
140
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
142
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143
+
};
144
+
145
+
/* Apalis Digital Audio */
146
+
clk1-req-pee2 {
147
+
nvidia,pins = "clk1_req_pee2";
148
+
nvidia,function = "hda";
149
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
150
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
151
+
};
152
+
clk2-out-pw5 {
153
+
nvidia,pins = "clk2_out_pw5";
154
+
nvidia,function = "extperiph2";
155
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
156
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
157
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
158
+
};
159
+
dap1-fs-pn0 {
160
+
nvidia,pins = "dap1_fs_pn0",
161
+
"dap1_din_pn1",
162
+
"dap1_dout_pn2",
163
+
"dap1_sclk_pn3";
164
+
nvidia,function = "hda";
165
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
167
+
};
168
+
169
+
/* Apalis GPIO */
170
+
kb-col0-pq0 {
171
+
nvidia,pins = "kb_col0_pq0",
172
+
"kb_col1_pq1",
173
+
"kb_row10_ps2",
174
+
"kb_row11_ps3",
175
+
"kb_row12_ps4",
176
+
"kb_row13_ps5",
177
+
"kb_row14_ps6",
178
+
"kb_row15_ps7";
179
+
nvidia,function = "kbc";
180
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
181
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
182
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
183
+
};
184
+
/* Multiplexed and therefore disabled */
185
+
owr {
186
+
nvidia,pins = "owr";
187
+
nvidia,function = "rsvd3";
188
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
189
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
190
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
191
+
};
192
+
193
+
/* Apalis HDMI1 */
194
+
hdmi-cec-pee3 {
195
+
nvidia,pins = "hdmi_cec_pee3";
196
+
nvidia,function = "cec";
197
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
199
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
200
+
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
201
+
};
202
+
hdmi-int-pn7 {
203
+
nvidia,pins = "hdmi_int_pn7";
204
+
nvidia,function = "hdmi";
205
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
207
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
208
+
};
209
+
210
+
/* Apalis I2C1 */
211
+
gen1-i2c-scl-pc4 {
212
+
nvidia,pins = "gen1_i2c_scl_pc4",
213
+
"gen1_i2c_sda_pc5";
214
+
nvidia,function = "i2c1";
215
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
217
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
218
+
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
219
+
};
220
+
221
+
/* Apalis I2C2 (DDC) */
222
+
ddc-scl-pv4 {
223
+
nvidia,pins = "ddc_scl_pv4",
224
+
"ddc_sda_pv5";
225
+
nvidia,function = "i2c4";
226
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
228
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
229
+
};
230
+
231
+
/* Apalis I2C3 (CAM) */
232
+
cam-i2c-scl-pbb1 {
233
+
nvidia,pins = "cam_i2c_scl_pbb1",
234
+
"cam_i2c_sda_pbb2";
235
+
nvidia,function = "i2c3";
236
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
237
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
238
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
239
+
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
240
+
};
241
+
242
+
/* Apalis LCD1 */
243
+
lcd-d0-pe0 {
244
+
nvidia,pins = "lcd_d0_pe0",
245
+
"lcd_d1_pe1",
246
+
"lcd_d2_pe2",
247
+
"lcd_d3_pe3",
248
+
"lcd_d4_pe4",
249
+
"lcd_d5_pe5",
250
+
"lcd_d6_pe6",
251
+
"lcd_d7_pe7",
252
+
"lcd_d8_pf0",
253
+
"lcd_d9_pf1",
254
+
"lcd_d10_pf2",
255
+
"lcd_d11_pf3",
256
+
"lcd_d12_pf4",
257
+
"lcd_d13_pf5",
258
+
"lcd_d14_pf6",
259
+
"lcd_d15_pf7",
260
+
"lcd_d16_pm0",
261
+
"lcd_d17_pm1",
262
+
"lcd_d18_pm2",
263
+
"lcd_d19_pm3",
264
+
"lcd_d20_pm4",
265
+
"lcd_d21_pm5",
266
+
"lcd_d22_pm6",
267
+
"lcd_d23_pm7",
268
+
"lcd_de_pj1",
269
+
"lcd_hsync_pj3",
270
+
"lcd_pclk_pb3",
271
+
"lcd_vsync_pj4";
272
+
nvidia,function = "displaya";
273
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
274
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
275
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
276
+
};
277
+
278
+
/* Apalis MMC1 */
279
+
sdmmc3-clk-pa6 {
280
+
nvidia,pins = "sdmmc3_clk_pa6";
281
+
nvidia,function = "sdmmc3";
282
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
283
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
284
+
};
285
+
sdmmc3-dat0-pb7 {
286
+
nvidia,pins = "sdmmc3_cmd_pa7",
287
+
"sdmmc3_dat0_pb7",
288
+
"sdmmc3_dat1_pb6",
289
+
"sdmmc3_dat2_pb5",
290
+
"sdmmc3_dat3_pb4",
291
+
"sdmmc3_dat4_pd1",
292
+
"sdmmc3_dat5_pd0",
293
+
"sdmmc3_dat6_pd3",
294
+
"sdmmc3_dat7_pd4";
295
+
nvidia,function = "sdmmc3";
296
+
nvidia,pull = <TEGRA_PIN_PULL_UP>;
297
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
298
+
};
299
+
/* Apalis MMC1_CD# */
300
+
pv3 {
301
+
nvidia,pins = "pv3";
302
+
nvidia,function = "rsvd2";
303
+
nvidia,pull = <TEGRA_PIN_PULL_UP>;
304
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
305
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
306
+
};
307
+
308
+
/* Apalis Parallel Camera */
309
+
cam-mclk-pcc0 {
310
+
nvidia,pins = "cam_mclk_pcc0";
311
+
nvidia,function = "vi_alt3";
312
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
313
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
314
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
315
+
};
316
+
vi-vsync-pd6 {
317
+
nvidia,pins = "vi_d0_pt4",
318
+
"vi_d1_pd5",
319
+
"vi_d2_pl0",
320
+
"vi_d3_pl1",
321
+
"vi_d4_pl2",
322
+
"vi_d5_pl3",
323
+
"vi_d6_pl4",
324
+
"vi_d7_pl5",
325
+
"vi_d8_pl6",
326
+
"vi_d9_pl7",
327
+
"vi_d10_pt2",
328
+
"vi_d11_pt3",
329
+
"vi_hsync_pd7",
330
+
"vi_pclk_pt0",
331
+
"vi_vsync_pd6";
332
+
nvidia,function = "vi";
333
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
334
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
335
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
336
+
};
337
+
/* Multiplexed and therefore disabled */
338
+
kb-col2-pq2 {
339
+
nvidia,pins = "kb_col2_pq2",
340
+
"kb_col3_pq3",
341
+
"kb_col4_pq4",
342
+
"kb_row4_pr4";
343
+
nvidia,function = "rsvd4";
344
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
345
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
346
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
347
+
};
348
+
kb-row0-pr0 {
349
+
nvidia,pins = "kb_row0_pr0",
350
+
"kb_row1_pr1",
351
+
"kb_row2_pr2",
352
+
"kb_row3_pr3";
353
+
nvidia,function = "rsvd3";
354
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
355
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
356
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
357
+
};
358
+
kb-row5-pr5 {
359
+
nvidia,pins = "kb_row5_pr5",
360
+
"kb_row6_pr6",
361
+
"kb_row7_pr7";
362
+
nvidia,function = "kbc";
363
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
364
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
365
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
366
+
};
367
+
/*
368
+
* VI level-shifter direction
369
+
* (pull-down => default direction input)
370
+
*/
371
+
vi-mclk-pt1 {
372
+
nvidia,pins = "vi_mclk_pt1";
373
+
nvidia,function = "vi_alt3";
374
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
375
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
376
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
377
+
};
378
+
379
+
/* Apalis PWM1 */
380
+
pu6 {
381
+
nvidia,pins = "pu6";
382
+
nvidia,function = "pwm3";
383
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
385
+
};
386
+
387
+
/* Apalis PWM2 */
388
+
pu5 {
389
+
nvidia,pins = "pu5";
390
+
nvidia,function = "pwm2";
391
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
393
+
};
394
+
395
+
/* Apalis PWM3 */
396
+
pu4 {
397
+
nvidia,pins = "pu4";
398
+
nvidia,function = "pwm1";
399
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
401
+
};
402
+
403
+
/* Apalis PWM4 */
404
+
pu3 {
405
+
nvidia,pins = "pu3";
406
+
nvidia,function = "pwm0";
407
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
408
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
409
+
};
410
+
411
+
/* Apalis RESET_MOCI# */
412
+
gmi-rst-n-pi4 {
413
+
nvidia,pins = "gmi_rst_n_pi4";
414
+
nvidia,function = "gmi";
415
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
416
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
417
+
};
418
+
419
+
/* Apalis SATA1_ACT# */
420
+
pex-l0-prsnt-n-pdd0 {
421
+
nvidia,pins = "pex_l0_prsnt_n_pdd0";
422
+
nvidia,function = "rsvd3";
423
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
424
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
425
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
426
+
};
427
+
428
+
/* Apalis SD1 */
429
+
sdmmc1-clk-pz0 {
430
+
nvidia,pins = "sdmmc1_clk_pz0";
431
+
nvidia,function = "sdmmc1";
432
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
433
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
434
+
};
435
+
sdmmc1-cmd-pz1 {
436
+
nvidia,pins = "sdmmc1_cmd_pz1",
437
+
"sdmmc1_dat0_py7",
438
+
"sdmmc1_dat1_py6",
439
+
"sdmmc1_dat2_py5",
440
+
"sdmmc1_dat3_py4";
441
+
nvidia,function = "sdmmc1";
442
+
nvidia,pull = <TEGRA_PIN_PULL_UP>;
443
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
444
+
};
445
+
/* Apalis SD1_CD# */
446
+
clk2-req-pcc5 {
447
+
nvidia,pins = "clk2_req_pcc5";
448
+
nvidia,function = "rsvd2";
449
+
nvidia,pull = <TEGRA_PIN_PULL_UP>;
450
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
451
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
452
+
};
453
+
454
+
/* Apalis SPDIF1 */
455
+
spdif-out-pk5 {
456
+
nvidia,pins = "spdif_out_pk5",
457
+
"spdif_in_pk6";
458
+
nvidia,function = "spdif";
459
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
460
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
461
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
462
+
};
463
+
464
+
/* Apalis SPI1 */
465
+
spi1-sck-px5 {
466
+
nvidia,pins = "spi1_sck_px5",
467
+
"spi1_mosi_px4",
468
+
"spi1_miso_px7",
469
+
"spi1_cs0_n_px6";
470
+
nvidia,function = "spi1";
471
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
473
+
};
474
+
475
+
/* Apalis SPI2 */
476
+
lcd-sck-pz4 {
477
+
nvidia,pins = "lcd_sck_pz4",
478
+
"lcd_sdout_pn5",
479
+
"lcd_sdin_pz2",
480
+
"lcd_cs0_n_pn4";
481
+
nvidia,function = "spi5";
482
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
483
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
484
+
};
485
+
486
+
/*
487
+
* Apalis TS (Low-speed type specific)
488
+
* pins may be used as GPIOs
489
+
*/
490
+
kb-col5-pq5 {
491
+
nvidia,pins = "kb_col5_pq5";
492
+
nvidia,function = "rsvd4";
493
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
494
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
495
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
496
+
};
497
+
kb-col6-pq6 {
498
+
nvidia,pins = "kb_col6_pq6",
499
+
"kb_col7_pq7",
500
+
"kb_row8_ps0",
501
+
"kb_row9_ps1";
502
+
nvidia,function = "kbc";
503
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
504
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
505
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
506
+
};
507
+
508
+
/* Apalis UART1 */
509
+
ulpi-data0 {
510
+
nvidia,pins = "ulpi_data0_po1",
511
+
"ulpi_data1_po2",
512
+
"ulpi_data2_po3",
513
+
"ulpi_data3_po4",
514
+
"ulpi_data4_po5",
515
+
"ulpi_data5_po6",
516
+
"ulpi_data6_po7",
517
+
"ulpi_data7_po0";
518
+
nvidia,function = "uarta";
519
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
520
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
521
+
};
522
+
523
+
/* Apalis UART2 */
524
+
ulpi-clk-py0 {
525
+
nvidia,pins = "ulpi_clk_py0",
526
+
"ulpi_dir_py1",
527
+
"ulpi_nxt_py2",
528
+
"ulpi_stp_py3";
529
+
nvidia,function = "uartd";
530
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
532
+
};
533
+
534
+
/* Apalis UART3 */
535
+
uart2-rxd-pc3 {
536
+
nvidia,pins = "uart2_rxd_pc3",
537
+
"uart2_txd_pc2";
538
+
nvidia,function = "uartb";
539
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
540
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
541
+
};
542
+
543
+
/* Apalis UART4 */
544
+
uart3-rxd-pw7 {
545
+
nvidia,pins = "uart3_rxd_pw7",
546
+
"uart3_txd_pw6";
547
+
nvidia,function = "uartc";
548
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
549
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
550
+
};
551
+
552
+
/* Apalis USBH_EN */
553
+
pex-l0-rst-n-pdd1 {
554
+
nvidia,pins = "pex_l0_rst_n_pdd1";
555
+
nvidia,function = "rsvd3";
556
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
557
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
558
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
559
+
};
560
+
561
+
/* Apalis USBH_OC# */
562
+
pex-l0-clkreq-n-pdd2 {
563
+
nvidia,pins = "pex_l0_clkreq_n_pdd2";
564
+
nvidia,function = "rsvd3";
565
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
566
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
567
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
568
+
};
569
+
570
+
/* Apalis USBO1_EN */
571
+
gen2-i2c-scl-pt5 {
572
+
nvidia,pins = "gen2_i2c_scl_pt5";
573
+
nvidia,function = "rsvd4";
574
+
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
575
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
576
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
577
+
};
578
+
579
+
/* Apalis USBO1_OC# */
580
+
gen2-i2c-sda-pt6 {
581
+
nvidia,pins = "gen2_i2c_sda_pt6";
582
+
nvidia,function = "rsvd4";
583
+
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
584
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
585
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
586
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
587
+
};
588
+
589
+
/* Apalis VGA1 not supported and therefore disabled */
590
+
crt-hsync-pv6 {
591
+
nvidia,pins = "crt_hsync_pv6",
592
+
"crt_vsync_pv7";
593
+
nvidia,function = "rsvd2";
594
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
595
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
596
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
597
+
};
598
+
599
+
/* Apalis WAKE1_MICO */
600
+
pv1 {
601
+
nvidia,pins = "pv1";
602
+
nvidia,function = "rsvd1";
603
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
604
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
605
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
606
+
};
607
+
608
+
/* eMMC (On-module) */
609
+
sdmmc4-clk-pcc4 {
610
+
nvidia,pins = "sdmmc4_clk_pcc4",
611
+
"sdmmc4_cmd_pt7",
612
+
"sdmmc4_rst_n_pcc3";
613
+
nvidia,function = "sdmmc4";
614
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
615
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
616
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
617
+
};
618
+
sdmmc4-dat0-paa0 {
619
+
nvidia,pins = "sdmmc4_dat0_paa0",
620
+
"sdmmc4_dat1_paa1",
621
+
"sdmmc4_dat2_paa2",
622
+
"sdmmc4_dat3_paa3",
623
+
"sdmmc4_dat4_paa4",
624
+
"sdmmc4_dat5_paa5",
625
+
"sdmmc4_dat6_paa6",
626
+
"sdmmc4_dat7_paa7";
627
+
nvidia,function = "sdmmc4";
628
+
nvidia,pull = <TEGRA_PIN_PULL_UP>;
629
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
630
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
631
+
};
632
+
633
+
/* EN_+3.3_SDMMC3 */
634
+
uart2-cts-n-pj5 {
635
+
nvidia,pins = "uart2_cts_n_pj5";
636
+
nvidia,function = "gmi";
637
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
639
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
640
+
};
641
+
642
+
/* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
643
+
pex-l2-prsnt-n-pdd7 {
644
+
nvidia,pins = "pex_l2_prsnt_n_pdd7",
645
+
"pex_l2_rst_n_pcc6";
646
+
nvidia,function = "pcie";
647
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
648
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
649
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
650
+
};
651
+
/* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
652
+
pex-wake-n-pdd3 {
653
+
nvidia,pins = "pex_wake_n_pdd3",
654
+
"pex_l2_clkreq_n_pcc7";
655
+
nvidia,function = "pcie";
656
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
657
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
658
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
659
+
};
660
+
/* LAN i210/i211 SMB_ALERT_N (On-module) */
661
+
sys-clk-req-pz5 {
662
+
nvidia,pins = "sys_clk_req_pz5";
663
+
nvidia,function = "rsvd2";
664
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
666
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
667
+
};
668
+
669
+
/* LVDS Transceiver Configuration */
670
+
pbb0 {
671
+
nvidia,pins = "pbb0",
672
+
"pbb7",
673
+
"pcc1",
674
+
"pcc2";
675
+
nvidia,function = "rsvd2";
676
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
677
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
678
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
679
+
};
680
+
pbb3 {
681
+
nvidia,pins = "pbb3",
682
+
"pbb4",
683
+
"pbb5",
684
+
"pbb6";
685
+
nvidia,function = "displayb";
686
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
687
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
688
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
689
+
};
690
+
691
+
/* Not connected and therefore disabled */
692
+
clk-32k-out-pa0 {
693
+
nvidia,pins = "clk3_out_pee0",
694
+
"clk3_req_pee1",
695
+
"clk_32k_out_pa0",
696
+
"dap4_din_pp5",
697
+
"dap4_dout_pp6",
698
+
"dap4_fs_pp4",
699
+
"dap4_sclk_pp7";
700
+
nvidia,function = "rsvd2";
701
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
702
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
703
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
704
+
};
705
+
dap2-fs-pa2 {
706
+
nvidia,pins = "dap2_fs_pa2",
707
+
"dap2_sclk_pa3",
708
+
"dap2_din_pa4",
709
+
"dap2_dout_pa5",
710
+
"lcd_dc0_pn6",
711
+
"lcd_m1_pw1",
712
+
"lcd_pwr1_pc1",
713
+
"pex_l1_clkreq_n_pdd6",
714
+
"pex_l1_prsnt_n_pdd4",
715
+
"pex_l1_rst_n_pdd5";
716
+
nvidia,function = "rsvd3";
717
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
718
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
719
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
720
+
};
721
+
gmi-ad0-pg0 {
722
+
nvidia,pins = "gmi_ad0_pg0",
723
+
"gmi_ad2_pg2",
724
+
"gmi_ad3_pg3",
725
+
"gmi_ad4_pg4",
726
+
"gmi_ad5_pg5",
727
+
"gmi_ad6_pg6",
728
+
"gmi_ad7_pg7",
729
+
"gmi_ad8_ph0",
730
+
"gmi_ad9_ph1",
731
+
"gmi_ad10_ph2",
732
+
"gmi_ad11_ph3",
733
+
"gmi_ad12_ph4",
734
+
"gmi_ad13_ph5",
735
+
"gmi_ad14_ph6",
736
+
"gmi_ad15_ph7",
737
+
"gmi_adv_n_pk0",
738
+
"gmi_clk_pk1",
739
+
"gmi_cs4_n_pk2",
740
+
"gmi_cs2_n_pk3",
741
+
"gmi_dqs_pi2",
742
+
"gmi_iordy_pi5",
743
+
"gmi_oe_n_pi1",
744
+
"gmi_wait_pi7",
745
+
"gmi_wr_n_pi0",
746
+
"lcd_cs1_n_pw0",
747
+
"pu0",
748
+
"pu1",
749
+
"pu2";
750
+
nvidia,function = "rsvd4";
751
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
752
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
753
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
754
+
};
755
+
gmi-cs0-n-pj0 {
756
+
nvidia,pins = "gmi_cs0_n_pj0",
757
+
"gmi_cs1_n_pj2",
758
+
"gmi_cs3_n_pk4";
759
+
nvidia,function = "rsvd1";
760
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
761
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
762
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
763
+
};
764
+
gmi-cs6-n-pi3 {
765
+
nvidia,pins = "gmi_cs6_n_pi3";
766
+
nvidia,function = "sata";
767
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
768
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
769
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
770
+
};
771
+
gmi-cs7-n-pi6 {
772
+
nvidia,pins = "gmi_cs7_n_pi6";
773
+
nvidia,function = "gmi_alt";
774
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
775
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
776
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
777
+
};
778
+
lcd-pwr0-pb2 {
779
+
nvidia,pins = "lcd_pwr0_pb2",
780
+
"lcd_pwr2_pc6",
781
+
"lcd_wr_n_pz3";
782
+
nvidia,function = "hdcp";
783
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
784
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
785
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
786
+
};
787
+
uart2-rts-n-pj6 {
788
+
nvidia,pins = "uart2_rts_n_pj6";
789
+
nvidia,function = "gmi";
790
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
791
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
792
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
793
+
};
794
+
795
+
/* Power I2C (On-module) */
796
+
pwr-i2c-scl-pz6 {
797
+
nvidia,pins = "pwr_i2c_scl_pz6",
798
+
"pwr_i2c_sda_pz7";
799
+
nvidia,function = "i2cpwr";
800
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
801
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
802
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
803
+
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
804
+
};
805
+
806
+
/*
807
+
* THERMD_ALERT#, unlatched I2C address pin of LM95245
808
+
* temperature sensor therefore requires disabling for
809
+
* now
810
+
*/
811
+
lcd-dc1-pd2 {
812
+
nvidia,pins = "lcd_dc1_pd2";
813
+
nvidia,function = "rsvd3";
814
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
815
+
nvidia,tristate = <TEGRA_PIN_ENABLE>;
816
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
817
+
};
818
+
819
+
/* TOUCH_PEN_INT# (On-module) */
820
+
pv0 {
821
+
nvidia,pins = "pv0";
822
+
nvidia,function = "rsvd1";
823
+
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
824
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
825
+
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826
+
};
827
+
};
828
+
};
829
+
830
+
serial@70006040 {
831
+
compatible = "nvidia,tegra30-hsuart";
832
+
};
833
+
834
+
serial@70006200 {
835
+
compatible = "nvidia,tegra30-hsuart";
836
+
};
837
+
838
+
serial@70006300 {
839
+
compatible = "nvidia,tegra30-hsuart";
840
+
};
841
+
842
+
hdmi_ddc: i2c@7000c700 {
843
+
clock-frequency = <10000>;
844
+
};
845
+
846
+
/*
847
+
* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
848
+
* touch screen controller
849
+
*/
850
+
i2c@7000d000 {
851
+
status = "okay";
852
+
clock-frequency = <100000>;
853
+
854
+
/* SGTL5000 audio codec */
855
+
sgtl5000: codec@a {
856
+
compatible = "fsl,sgtl5000";
857
+
reg = <0x0a>;
858
+
VDDA-supply = <®_module_3v3_audio>;
859
+
VDDD-supply = <®_1v8_vio>;
860
+
VDDIO-supply = <®_module_3v3>;
861
+
clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
862
+
};
863
+
864
+
pmic: pmic@2d {
865
+
compatible = "ti,tps65911";
866
+
reg = <0x2d>;
867
+
868
+
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
869
+
#interrupt-cells = <2>;
870
+
interrupt-controller;
871
+
872
+
ti,system-power-controller;
873
+
874
+
#gpio-cells = <2>;
875
+
gpio-controller;
876
+
877
+
vcc1-supply = <®_module_3v3>;
878
+
vcc2-supply = <®_module_3v3>;
879
+
vcc3-supply = <®_1v8_vio>;
880
+
vcc4-supply = <®_module_3v3>;
881
+
vcc5-supply = <®_module_3v3>;
882
+
vcc6-supply = <®_1v8_vio>;
883
+
vcc7-supply = <®_5v0_charge_pump>;
884
+
vccio-supply = <®_module_3v3>;
885
+
886
+
regulators {
887
+
vdd1_reg: vdd1 {
888
+
regulator-name = "+V1.35_VDDIO_DDR";
889
+
regulator-min-microvolt = <1350000>;
890
+
regulator-max-microvolt = <1350000>;
891
+
regulator-always-on;
892
+
};
893
+
894
+
vdd2_reg: vdd2 {
895
+
regulator-name = "+V1.05";
896
+
regulator-min-microvolt = <1050000>;
897
+
regulator-max-microvolt = <1050000>;
898
+
};
899
+
900
+
vddctrl_reg: vddctrl {
901
+
regulator-name = "+V1.0_VDD_CPU";
902
+
regulator-min-microvolt = <1150000>;
903
+
regulator-max-microvolt = <1150000>;
904
+
regulator-always-on;
905
+
};
906
+
907
+
reg_1v8_vio: vio {
908
+
regulator-name = "+V1.8";
909
+
regulator-min-microvolt = <1800000>;
910
+
regulator-max-microvolt = <1800000>;
911
+
regulator-always-on;
912
+
};
913
+
914
+
/*
915
+
* 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3
916
+
* is off
917
+
*/
918
+
vddio_sdmmc_1v8_reg: ldo1 {
919
+
regulator-name = "+VDDIO_SDMMC3_1V8";
920
+
regulator-min-microvolt = <1800000>;
921
+
regulator-max-microvolt = <1800000>;
922
+
regulator-always-on;
923
+
};
924
+
925
+
/*
926
+
* EN_+V3.3 switching via FET:
927
+
* +V3.3_AUDIO_AVDD_S, +V3.3
928
+
* see also +V3.3 fixed supply
929
+
*/
930
+
ldo2_reg: ldo2 {
931
+
regulator-name = "EN_+V3.3";
932
+
regulator-min-microvolt = <3300000>;
933
+
regulator-max-microvolt = <3300000>;
934
+
regulator-always-on;
935
+
};
936
+
937
+
ldo3_reg: ldo3 {
938
+
regulator-name = "+V1.2_CSI";
939
+
regulator-min-microvolt = <1200000>;
940
+
regulator-max-microvolt = <1200000>;
941
+
};
942
+
943
+
ldo4_reg: ldo4 {
944
+
regulator-name = "+V1.2_VDD_RTC";
945
+
regulator-min-microvolt = <1200000>;
946
+
regulator-max-microvolt = <1200000>;
947
+
regulator-always-on;
948
+
};
949
+
950
+
/*
951
+
* +V2.8_AVDD_VDAC:
952
+
* only required for (unsupported) analog RGB
953
+
*/
954
+
ldo5_reg: ldo5 {
955
+
regulator-name = "+V2.8_AVDD_VDAC";
956
+
regulator-min-microvolt = <2800000>;
957
+
regulator-max-microvolt = <2800000>;
958
+
regulator-always-on;
959
+
};
960
+
961
+
/*
962
+
* +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
963
+
* but LDO6 can't set voltage in 50mV
964
+
* granularity
965
+
*/
966
+
ldo6_reg: ldo6 {
967
+
regulator-name = "+V1.05_AVDD_PLLE";
968
+
regulator-min-microvolt = <1100000>;
969
+
regulator-max-microvolt = <1100000>;
970
+
};
971
+
972
+
ldo7_reg: ldo7 {
973
+
regulator-name = "+V1.2_AVDD_PLL";
974
+
regulator-min-microvolt = <1200000>;
975
+
regulator-max-microvolt = <1200000>;
976
+
regulator-always-on;
977
+
};
978
+
979
+
ldo8_reg: ldo8 {
980
+
regulator-name = "+V1.0_VDD_DDR_HS";
981
+
regulator-min-microvolt = <1000000>;
982
+
regulator-max-microvolt = <1000000>;
983
+
regulator-always-on;
984
+
};
985
+
};
986
+
};
987
+
988
+
/* STMPE811 touch screen controller */
989
+
touchscreen@41 {
990
+
compatible = "st,stmpe811";
991
+
reg = <0x41>;
992
+
irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
993
+
interrupt-controller;
994
+
id = <0>;
995
+
blocks = <0x5>;
996
+
irq-trigger = <0x1>;
997
+
998
+
stmpe_touchscreen {
999
+
compatible = "st,stmpe-ts";
1000
+
/* 3.25 MHz ADC clock speed */
1001
+
st,adc-freq = <1>;
1002
+
/* 8 sample average control */
1003
+
st,ave-ctrl = <3>;
1004
+
/* 7 length fractional part in z */
1005
+
st,fraction-z = <7>;
1006
+
/*
1007
+
* 50 mA typical 80 mA max touchscreen drivers
1008
+
* current limit value
1009
+
*/
1010
+
st,i-drive = <1>;
1011
+
/* 12-bit ADC */
1012
+
st,mod-12b = <1>;
1013
+
/* internal ADC reference */
1014
+
st,ref-sel = <0>;
1015
+
/* ADC converstion time: 80 clocks */
1016
+
st,sample-time = <4>;
1017
+
/* 1 ms panel driver settling time */
1018
+
st,settling = <3>;
1019
+
/* 5 ms touch detect interrupt delay */
1020
+
st,touch-det-delay = <5>;
1021
+
};
1022
+
};
1023
+
1024
+
/*
1025
+
* LM95245 temperature sensor
1026
+
* Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
1027
+
*/
1028
+
temp-sensor@4c {
1029
+
compatible = "national,lm95245";
1030
+
reg = <0x4c>;
1031
+
};
1032
+
1033
+
/* SW: +V1.2_VDD_CORE */
1034
+
regulator@60 {
1035
+
compatible = "ti,tps62362";
1036
+
reg = <0x60>;
1037
+
1038
+
regulator-name = "tps62362-vout";
1039
+
regulator-min-microvolt = <900000>;
1040
+
regulator-max-microvolt = <1400000>;
1041
+
regulator-boot-on;
1042
+
regulator-always-on;
1043
+
ti,vsel0-state-low;
1044
+
/* VSEL1: EN_CORE_DVFS_N low for DVFS */
1045
+
ti,vsel1-state-low;
1046
+
};
1047
+
};
1048
+
1049
+
/* SPI4: CAN2 */
1050
+
spi@7000da00 {
1051
+
status = "okay";
1052
+
spi-max-frequency = <10000000>;
1053
+
1054
+
can@1 {
1055
+
compatible = "microchip,mcp2515";
1056
+
reg = <1>;
1057
+
clocks = <&clk16m>;
1058
+
interrupt-parent = <&gpio>;
1059
+
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
1060
+
spi-max-frequency = <10000000>;
1061
+
};
1062
+
};
1063
+
1064
+
/* SPI6: CAN1 */
1065
+
spi@7000de00 {
1066
+
status = "okay";
1067
+
spi-max-frequency = <10000000>;
1068
+
1069
+
can@0 {
1070
+
compatible = "microchip,mcp2515";
1071
+
reg = <0>;
1072
+
clocks = <&clk16m>;
1073
+
interrupt-parent = <&gpio>;
1074
+
interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
1075
+
spi-max-frequency = <10000000>;
1076
+
};
1077
+
};
1078
+
1079
+
pmc@7000e400 {
1080
+
nvidia,invert-interrupt;
1081
+
nvidia,suspend-mode = <1>;
1082
+
nvidia,cpu-pwr-good-time = <5000>;
1083
+
nvidia,cpu-pwr-off-time = <5000>;
1084
+
nvidia,core-pwr-good-time = <3845 3845>;
1085
+
nvidia,core-pwr-off-time = <0>;
1086
+
nvidia,core-power-req-active-high;
1087
+
nvidia,sys-clock-req-active-high;
1088
+
1089
+
/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
1090
+
i2c-thermtrip {
1091
+
nvidia,i2c-controller-id = <4>;
1092
+
nvidia,bus-addr = <0x2d>;
1093
+
nvidia,reg-addr = <0x3f>;
1094
+
nvidia,reg-data = <0x1>;
1095
+
};
1096
+
};
1097
+
1098
+
hda@70030000 {
1099
+
status = "okay";
1100
+
};
1101
+
1102
+
ahub@70080000 {
1103
+
i2s@70080500 {
1104
+
status = "okay";
1105
+
};
1106
+
};
1107
+
1108
+
/* eMMC */
1109
+
sdhci@78000600 {
1110
+
status = "okay";
1111
+
bus-width = <8>;
1112
+
non-removable;
1113
+
vmmc-supply = <®_module_3v3>; /* VCC */
1114
+
vqmmc-supply = <®_1v8_vio>; /* VCCQ */
1115
+
mmc-ddr-1_8v;
1116
+
};
1117
+
1118
+
clk32k_in: xtal1 {
1119
+
compatible = "fixed-clock";
1120
+
#clock-cells = <0>;
1121
+
clock-frequency = <32768>;
1122
+
};
1123
+
1124
+
clk16m: osc4 {
1125
+
compatible = "fixed-clock";
1126
+
#clock-cells = <0>;
1127
+
clock-frequency = <16000000>;
1128
+
};
1129
+
1130
+
reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
1131
+
compatible = "regulator-fixed";
1132
+
regulator-name = "+V1.8_AVDD_HDMI_PLL";
1133
+
regulator-min-microvolt = <1800000>;
1134
+
regulator-max-microvolt = <1800000>;
1135
+
enable-active-high;
1136
+
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1137
+
vin-supply = <®_1v8_vio>;
1138
+
};
1139
+
1140
+
reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1141
+
compatible = "regulator-fixed";
1142
+
regulator-name = "+V3.3_AVDD_HDMI";
1143
+
regulator-min-microvolt = <3300000>;
1144
+
regulator-max-microvolt = <3300000>;
1145
+
enable-active-high;
1146
+
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1147
+
vin-supply = <®_module_3v3>;
1148
+
};
1149
+
1150
+
reg_5v0_charge_pump: regulator-5v0-charge-pump {
1151
+
compatible = "regulator-fixed";
1152
+
regulator-name = "+V5.0";
1153
+
regulator-min-microvolt = <5000000>;
1154
+
regulator-max-microvolt = <5000000>;
1155
+
regulator-always-on;
1156
+
};
1157
+
1158
+
reg_module_3v3: regulator-module-3v3 {
1159
+
compatible = "regulator-fixed";
1160
+
regulator-name = "+V3.3";
1161
+
regulator-min-microvolt = <3300000>;
1162
+
regulator-max-microvolt = <3300000>;
1163
+
regulator-always-on;
1164
+
};
1165
+
1166
+
reg_module_3v3_audio: regulator-module-3v3-audio {
1167
+
compatible = "regulator-fixed";
1168
+
regulator-name = "+V3.3_AUDIO_AVDD_S";
1169
+
regulator-min-microvolt = <3300000>;
1170
+
regulator-max-microvolt = <3300000>;
1171
+
regulator-always-on;
1172
+
};
1173
+
1174
+
sound {
1175
+
compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
1176
+
"nvidia,tegra-audio-sgtl5000";
1177
+
nvidia,model = "Toradex Apalis T30";
1178
+
nvidia,audio-routing =
1179
+
"Headphone Jack", "HP_OUT",
1180
+
"LINE_IN", "Line In Jack",
1181
+
"MIC_IN", "Mic Jack";
1182
+
nvidia,i2s-controller = <&tegra_i2s2>;
1183
+
nvidia,audio-codec = <&sgtl5000>;
1184
+
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1185
+
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1186
+
<&tegra_car TEGRA30_CLK_EXTERN1>;
1187
+
clock-names = "pll_a", "pll_a_out0", "mclk";
1188
+
};
1189
+
};
+1
-2
arch/arm/boot/dts/tegra30-apalis.dtsi
+1
-2
arch/arm/boot/dts/tegra30-apalis.dtsi