Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Ingo Molnar:
"Fix uncore PMU enumeration for CofeeLake CPUs"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/intel/uncore: Support CoffeeLake 8th CBOX
perf/x86/intel/uncore: Add more IMC PCI IDs for KabyLake and CoffeeLake CPUs

Changed files
+144 -10
arch
x86
events
+25 -8
arch/x86/events/intel/uncore.h
··· 129 129 struct intel_uncore_extra_reg shared_regs[0]; 130 130 }; 131 131 132 - #define UNCORE_BOX_FLAG_INITIATED 0 133 - #define UNCORE_BOX_FLAG_CTL_OFFS8 1 /* event config registers are 8-byte apart */ 132 + /* CFL uncore 8th cbox MSRs */ 133 + #define CFL_UNC_CBO_7_PERFEVTSEL0 0xf70 134 + #define CFL_UNC_CBO_7_PER_CTR0 0xf76 135 + 136 + #define UNCORE_BOX_FLAG_INITIATED 0 137 + /* event config registers are 8-byte apart */ 138 + #define UNCORE_BOX_FLAG_CTL_OFFS8 1 139 + /* CFL 8th CBOX has different MSR space */ 140 + #define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS 2 134 141 135 142 struct uncore_event_desc { 136 143 struct kobj_attribute attr; ··· 304 297 static inline 305 298 unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx) 306 299 { 307 - return box->pmu->type->event_ctl + 308 - (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + 309 - uncore_msr_box_offset(box); 300 + if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) { 301 + return CFL_UNC_CBO_7_PERFEVTSEL0 + 302 + (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx); 303 + } else { 304 + return box->pmu->type->event_ctl + 305 + (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + 306 + uncore_msr_box_offset(box); 307 + } 310 308 } 311 309 312 310 static inline 313 311 unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx) 314 312 { 315 - return box->pmu->type->perf_ctr + 316 - (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + 317 - uncore_msr_box_offset(box); 313 + if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) { 314 + return CFL_UNC_CBO_7_PER_CTR0 + 315 + (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx); 316 + } else { 317 + return box->pmu->type->perf_ctr + 318 + (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) + 319 + uncore_msr_box_offset(box); 320 + } 318 321 } 319 322 320 323 static inline
+119 -2
arch/x86/events/intel/uncore_snb.c
··· 15 15 #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910 16 16 #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f 17 17 #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f 18 + #define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c 19 + #define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904 20 + #define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914 21 + #define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f 22 + #define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f 23 + #define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc 24 + #define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0 25 + #define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10 26 + #define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4 27 + #define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC 0x3e0f 28 + #define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC 0x3e1f 29 + #define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC 0x3ec2 30 + #define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC 0x3e30 31 + #define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC 0x3e18 32 + #define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC 0x3ec6 33 + #define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC 0x3e31 34 + #define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC 0x3e33 35 + #define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC 0x3eca 36 + #define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC 0x3e32 18 37 19 38 /* SNB event control */ 20 39 #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff ··· 221 202 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 222 203 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL); 223 204 } 205 + 206 + /* The 8th CBOX has different MSR space */ 207 + if (box->pmu->pmu_idx == 7) 208 + __set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags); 224 209 } 225 210 226 211 static void skl_uncore_msr_enable_box(struct intel_uncore_box *box) ··· 251 228 static struct intel_uncore_type skl_uncore_cbox = { 252 229 .name = "cbox", 253 230 .num_counters = 4, 254 - .num_boxes = 5, 231 + .num_boxes = 8, 255 232 .perf_ctr_bits = 44, 256 233 .fixed_ctr_bits = 48, 257 234 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0, ··· 592 569 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC), 593 570 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 594 571 }, 595 - 572 + { /* IMC */ 573 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC), 574 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 575 + }, 576 + { /* IMC */ 577 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_U_IMC), 578 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 579 + }, 580 + { /* IMC */ 581 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_UQ_IMC), 582 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 583 + }, 584 + { /* IMC */ 585 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SD_IMC), 586 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 587 + }, 588 + { /* IMC */ 589 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SQ_IMC), 590 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 591 + }, 592 + { /* IMC */ 593 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2U_IMC), 594 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 595 + }, 596 + { /* IMC */ 597 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4U_IMC), 598 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 599 + }, 600 + { /* IMC */ 601 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4H_IMC), 602 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 603 + }, 604 + { /* IMC */ 605 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6H_IMC), 606 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 607 + }, 608 + { /* IMC */ 609 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC), 610 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 611 + }, 612 + { /* IMC */ 613 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC), 614 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 615 + }, 616 + { /* IMC */ 617 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC), 618 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 619 + }, 620 + { /* IMC */ 621 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC), 622 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 623 + }, 624 + { /* IMC */ 625 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC), 626 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 627 + }, 628 + { /* IMC */ 629 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC), 630 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 631 + }, 632 + { /* IMC */ 633 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC), 634 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 635 + }, 636 + { /* IMC */ 637 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC), 638 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 639 + }, 640 + { /* IMC */ 641 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC), 642 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 643 + }, 644 + { /* IMC */ 645 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC), 646 + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), 647 + }, 596 648 { /* end: all zeroes */ }, 597 649 }; 598 650 ··· 716 618 IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */ 717 619 IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */ 718 620 IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */ 621 + IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver), /* 7th Gen Core Y */ 622 + IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U */ 623 + IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U Quad Core */ 624 + IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Dual Core */ 625 + IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Quad Core */ 626 + IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 2 Cores */ 627 + IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 4 Cores */ 628 + IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 4 Cores */ 629 + IMC_DEV(CFL_6H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 6 Cores */ 630 + IMC_DEV(CFL_2S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 2 Cores Desktop */ 631 + IMC_DEV(CFL_4S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Desktop */ 632 + IMC_DEV(CFL_6S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Desktop */ 633 + IMC_DEV(CFL_8S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Desktop */ 634 + IMC_DEV(CFL_4S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Work Station */ 635 + IMC_DEV(CFL_6S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Work Station */ 636 + IMC_DEV(CFL_8S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Work Station */ 637 + IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Server */ 638 + IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Server */ 639 + IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Server */ 719 640 { /* end marker */ } 720 641 }; 721 642