Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: Add pixel_clock to amd_pp_display_configuration

This commit adds the pixel_clock field to the display config
struct so that power management (DPM) can use it.

We currently don't have a proper bandwidth calculation on old
GPUs with DCE 6-10 because dce_calcs only supports DCE 11+.
So the power management (DPM) on these GPUs may need to make
ad-hoc decisions for display based on the pixel clock.

Also rename sym_clock to pixel_clock in dm_pp_single_disp_config
to avoid confusion with other code where the sym_clock refers to
the DisplayPort symbol clock.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Timur Kristóf and committed by
Alex Deucher
b515dcb0 92d6295a

+4 -2
+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
··· 98 98 const struct dm_pp_single_disp_config *dc_cfg = 99 99 &pp_display_cfg->disp_configs[i]; 100 100 adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1; 101 + adev->pm.pm_display_cfg.displays[i].pixel_clock = dc_cfg->pixel_clock; 101 102 } 102 103 103 104 amdgpu_dpm_display_configuration_change(adev, &adev->pm.pm_display_cfg);
+1 -1
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
··· 164 164 stream->link->cur_link_settings.link_rate; 165 165 cfg->link_settings.link_spread = 166 166 stream->link->cur_link_settings.link_spread; 167 - cfg->sym_clock = stream->phy_pix_clk; 167 + cfg->pixel_clock = stream->phy_pix_clk; 168 168 /* Round v_refresh*/ 169 169 cfg->v_refresh = stream->timing.pix_clk_100hz * 100; 170 170 cfg->v_refresh /= stream->timing.h_total;
+1 -1
drivers/gpu/drm/amd/display/dc/dm_services_types.h
··· 127 127 uint32_t src_height; 128 128 uint32_t src_width; 129 129 uint32_t v_refresh; 130 - uint32_t sym_clock; /* HDMI only */ 130 + uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */ 131 131 struct dc_link_settings link_settings; /* DP only */ 132 132 }; 133 133
+1
drivers/gpu/drm/amd/include/dm_pp_interface.h
··· 65 65 uint32_t view_resolution_cy; 66 66 enum amd_pp_display_config_type displayconfigtype; 67 67 uint32_t vertical_refresh; /* for active display */ 68 + uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */ 68 69 }; 69 70 70 71 #define MAX_NUM_DISPLAY 32