sparc64: Make %pil level 15 a pseudo-NMI.

+4 -2

arch/sparc/include/asm/irqflags_64.h

··· 10 10 #ifndef _ASM_IRQFLAGS_H 11 11 #define _ASM_IRQFLAGS_H 12 12 13 + #include <asm/pil.h> 14 + 13 15 #ifndef __ASSEMBLY__ 14 16 15 17 static inline unsigned long __raw_local_save_flags(void) ··· 42 40 static inline void raw_local_irq_disable(void) 43 41 { 44 42 __asm__ __volatile__( 45 - "wrpr 15, %%pil" 43 + "wrpr %0, %%pil" 46 44 : /* no outputs */ 47 - : /* no inputs */ 45 + : "i" (PIL_NORMAL_MAX) 48 46 : "memory" 49 47 ); 50 48 }

+8 -1

arch/sparc/include/asm/pil.h

··· 10 10 * 11 11 * In fact any XCALL which has to etrap/rtrap has a problem because 12 12 * it is difficult to prevent rtrap from running BH's, and that would 13 - * need to be done if the XCALL arrived while %pil==15. 13 + * need to be done if the XCALL arrived while %pil==PIL_NORMAL_MAX. 14 + * 15 + * Finally, in order to handle profiling events even when a 16 + * local_irq_disable() is in progress, we only disable up to level 14 17 + * interrupts. Profile counter overflow interrupts arrive at level 18 + * 15. 14 19 */ 15 20 #define PIL_SMP_CALL_FUNC 1 16 21 #define PIL_SMP_RECEIVE_SIGNAL 2 ··· 23 18 #define PIL_SMP_CTX_NEW_VERSION 4 24 19 #define PIL_DEVICE_IRQ 5 25 20 #define PIL_SMP_CALL_FUNC_SNGL 6 21 + #define PIL_NORMAL_MAX 14 22 + #define PIL_NMI 15 26 23 27 24 #endif /* !(_SPARC64_PIL_H) */

+13 -2

arch/sparc/include/asm/ttable.h

··· 2 2 #define _SPARC64_TTABLE_H 3 3 4 4 #include <asm/utrap.h> 5 + #include <asm/pil.h> 5 6 6 7 #ifdef __ASSEMBLY__ 7 8 #include <asm/thread_info.h> ··· 124 123 125 124 #define TRAP_IRQ(routine, level) \ 126 125 rdpr %pil, %g2; \ 127 - wrpr %g0, 15, %pil; \ 126 + wrpr %g0, PIL_NORMAL_MAX, %pil; \ 128 127 sethi %hi(1f-4), %g7; \ 129 128 ba,pt %xcc, etrap_irq; \ 130 129 or %g7, %lo(1f-4), %g7; \ ··· 144 143 145 144 #define TRAP_IRQ(routine, level) \ 146 145 rdpr %pil, %g2; \ 147 - wrpr %g0, 15, %pil; \ 146 + wrpr %g0, PIL_NORMAL_MAX, %pil; \ 148 147 ba,pt %xcc, etrap_irq; \ 149 148 rd %pc, %g7; \ 150 149 mov level, %o0; \ ··· 153 152 ba,a,pt %xcc, rtrap_irq; 154 153 155 154 #endif 155 + 156 + #define TRAP_NMI_IRQ(routine, level) \ 157 + rdpr %pil, %g2; \ 158 + wrpr %g0, PIL_NMI, %pil; \ 159 + ba,pt %xcc, etrap_irq; \ 160 + rd %pc, %g7; \ 161 + mov level, %o0; \ 162 + call routine; \ 163 + add %sp, PTREGS_OFF, %o1; \ 164 + ba,a,pt %xcc, rtrap_irq; 156 165 157 166 #define TRAP_IVEC TRAP_NOSAVE(do_ivec) 158 167

+2 -2

arch/sparc/mm/ultra.S

··· 466 466 .previous 467 467 468 468 rdpr %pil, %g2 469 - wrpr %g0, 15, %pil 469 + wrpr %g0, PIL_NORMAL_MAX, %pil 470 470 sethi %hi(109f), %g7 471 471 b,pt %xcc, etrap_irq 472 472 109: or %g7, %lo(109b), %g7 ··· 688 688 .previous 689 689 690 690 rdpr %pil, %g2 691 - wrpr %g0, 15, %pil 691 + wrpr %g0, PIL_NORMAL_MAX, %pil 692 692 sethi %hi(109f), %g7 693 693 ba,pt %xcc, etrap_irq 694 694 109: or %g7, %lo(109b), %g7

+5 -5

arch/sparc64/kernel/cherrs.S

··· 102 102 .type do_cheetah_plus_data_parity,#function 103 103 do_cheetah_plus_data_parity: 104 104 rdpr %pil, %g2 105 - wrpr %g0, 15, %pil 105 + wrpr %g0, PIL_NORMAL_MAX, %pil 106 106 ba,pt %xcc, etrap_irq 107 107 rd %pc, %g7 108 108 #ifdef CONFIG_TRACE_IRQFLAGS ··· 144 144 .type do_cheetah_plus_insn_parity,#function 145 145 do_cheetah_plus_insn_parity: 146 146 rdpr %pil, %g2 147 - wrpr %g0, 15, %pil 147 + wrpr %g0, PIL_NORMAL_MAX, %pil 148 148 ba,pt %xcc, etrap_irq 149 149 rd %pc, %g7 150 150 #ifdef CONFIG_TRACE_IRQFLAGS ··· 492 492 .type c_fast_ecc,#function 493 493 c_fast_ecc: 494 494 rdpr %pil, %g2 495 - wrpr %g0, 15, %pil 495 + wrpr %g0, PIL_NORMAL_MAX, %pil 496 496 ba,pt %xcc, etrap_irq 497 497 rd %pc, %g7 498 498 #ifdef CONFIG_TRACE_IRQFLAGS ··· 528 528 .type c_cee,#function 529 529 c_cee: 530 530 rdpr %pil, %g2 531 - wrpr %g0, 15, %pil 531 + wrpr %g0, PIL_NORMAL_MAX, %pil 532 532 ba,pt %xcc, etrap_irq 533 533 rd %pc, %g7 534 534 #ifdef CONFIG_TRACE_IRQFLAGS ··· 564 564 .type c_deferred,#function 565 565 c_deferred: 566 566 rdpr %pil, %g2 567 - wrpr %g0, 15, %pil 567 + wrpr %g0, PIL_NORMAL_MAX, %pil 568 568 ba,pt %xcc, etrap_irq 569 569 rd %pc, %g7 570 570 #ifdef CONFIG_TRACE_IRQFLAGS

+1 -1

arch/sparc64/kernel/head.S

··· 706 706 andn %l0, PSTATE_IE, %o1 707 707 wrpr %o1, 0x0, %pstate 708 708 rdpr %pil, %l1 709 - wrpr %g0, 15, %pil 709 + wrpr %g0, PIL_NORMAL_MAX, %pil 710 710 711 711 /* Make the firmware call to jump over to the Linux trap table. */ 712 712 sethi %hi(is_sun4v), %o0

+3 -2

arch/sparc64/kernel/hvtramp.S

··· 1 1 /* hvtramp.S: Hypervisor start-cpu trampoline code. 2 2 * 3 - * Copyright (C) 2007 David S. Miller <davem@davemloft.net> 3 + * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net> 4 4 */ 5 5 6 6 #include <linux/init.h> ··· 14 14 #include <asm/ptrace.h> 15 15 #include <asm/head.h> 16 16 #include <asm/asi.h> 17 + #include <asm/pil.h> 17 18 18 19 __CPUINIT 19 20 .align 8 ··· 33 32 */ 34 33 hv_cpu_startup: 35 34 SET_GL(0) 36 - wrpr %g0, 15, %pil 35 + wrpr %g0, PIL_NORMAL_MAX, %pil 37 36 wrpr %g0, 0, %canrestore 38 37 wrpr %g0, 0, %otherwin 39 38 wrpr %g0, 6, %cansave

+2 -2

arch/sparc64/kernel/smp.c

··· 1146 1146 } 1147 1147 } 1148 1148 1149 - /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they 1150 - * can service tlb flush xcalls... 1149 + /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE 1150 + * set, so they can service tlb flush xcalls... 1151 1151 */ 1152 1152 extern void prom_world(int); 1153 1153

+1 -1

arch/sparc64/kernel/spiterrs.S

··· 80 80 cmp %g2, 1 81 81 rdpr %pil, %g2 82 82 bleu,pt %xcc, 1f 83 - wrpr %g0, 15, %pil 83 + wrpr %g0, PIL_NORMAL_MAX, %pil 84 84 85 85 ba,pt %xcc, etraptl1 86 86 rd %pc, %g7

+4 -4

arch/sparc64/kernel/sun4v_ivec.S

··· 186 186 * when it's done. 187 187 */ 188 188 rdpr %pil, %g2 189 - wrpr %g0, 15, %pil 189 + wrpr %g0, PIL_NORMAL_MAX, %pil 190 190 mov %g1, %g4 191 191 ba,pt %xcc, etrap_irq 192 192 rd %pc, %g7 ··· 216 216 membar #Sync 217 217 218 218 rdpr %pil, %g2 219 - wrpr %g0, 15, %pil 219 + wrpr %g0, PIL_NORMAL_MAX, %pil 220 220 ba,pt %xcc, etrap_irq 221 221 rd %pc, %g7 222 222 #ifdef CONFIG_TRACE_IRQFLAGS ··· 297 297 * when it's done. 298 298 */ 299 299 rdpr %pil, %g2 300 - wrpr %g0, 15, %pil 300 + wrpr %g0, PIL_NORMAL_MAX, %pil 301 301 mov %g1, %g4 302 302 ba,pt %xcc, etrap_irq 303 303 rd %pc, %g7 ··· 327 327 membar #Sync 328 328 329 329 rdpr %pil, %g2 330 - wrpr %g0, 15, %pil 330 + wrpr %g0, PIL_NORMAL_MAX, %pil 331 331 ba,pt %xcc, etrap_irq 332 332 rd %pc, %g7 333 333 #ifdef CONFIG_TRACE_IRQFLAGS

+2 -2

arch/sparc64/kernel/traps.c

··· 1832 1832 } 1833 1833 } 1834 1834 1835 - /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate. 1835 + /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate. 1836 1836 * Log the event and clear the first word of the entry. 1837 1837 */ 1838 1838 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset) ··· 1880 1880 atomic_inc(&sun4v_resum_oflow_cnt); 1881 1881 } 1882 1882 1883 - /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate. 1883 + /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate. 1884 1884 * Log the event, clear the first word of the entry, and die. 1885 1885 */ 1886 1886 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)

+1 -1

arch/sparc64/kernel/ttable.S

··· 66 66 tl0_irq7: BTRAP(0x47) BTRAP(0x48) BTRAP(0x49) 67 67 tl0_irq10: BTRAP(0x4a) BTRAP(0x4b) BTRAP(0x4c) BTRAP(0x4d) 68 68 tl0_irq14: TRAP_IRQ(timer_interrupt, 14) 69 - tl0_irq15: TRAP_IRQ(perfctr_irq, 15) 69 + tl0_irq15: TRAP_NMI_IRQ(perfctr_irq, 15) 70 70 tl0_resv050: BTRAP(0x50) BTRAP(0x51) BTRAP(0x52) BTRAP(0x53) BTRAP(0x54) BTRAP(0x55) 71 71 tl0_resv056: BTRAP(0x56) BTRAP(0x57) BTRAP(0x58) BTRAP(0x59) BTRAP(0x5a) BTRAP(0x5b) 72 72 tl0_resv05c: BTRAP(0x5c) BTRAP(0x5d) BTRAP(0x5e) BTRAP(0x5f)