[media] DiBxxxx: Codingstype updates

This patchs fix several conding-style violations.

Signed-off-by: Olivier Grenie <[e-mail]>
Signed-off-by: Patrick Boettcher <[e-mail]>
Signed-off-by: Mauro Carvalho Chehab <[e-mail]>

drivers/media/dvb/dvb-usb/dib0700_core.c

···
 	b[6] = (u8) (divider >> 8);
 	b[7] = (u8) (divider & 0xff);
 
-	deb_info("setting I2C speed: %04x %04x %04x (%d kHz).", (b[2] << 8) | (b[3]), (b[4] << 8) | b[5], (b[6] << 8) | b[7], scl_kHz);
+	deb_info("setting I2C speed: %04x %04x %04x (%d kHz).",
+		(b[2] << 8) | (b[3]), (b[4] << 8) | b[5], (b[6] << 8) | b[7], scl_kHz);
 	return dib0700_ctrl_wr(d, b, 8);
 }
 
···
 	deb_info("modifying (%d) streaming state for %d\n", onoff, adap->id);
 
 	st->channel_state &= ~0x3;
-	if ((adap->stream.props.endpoint != 2) && (adap->stream.props.endpoint != 3)) {
+	if ((adap->stream.props.endpoint != 2)
+			&& (adap->stream.props.endpoint != 3)) {
 		deb_info("the endpoint number (%i) is not correct, use the adapter id instead", adap->stream.props.endpoint);
 		if (onoff)
 			st->channel_state |=	1 << (adap->id);
 		else
 			st->channel_state |=	1 << ~(adap->id);
-	}
-	else {
+	} else {
 		if (onoff)
 			st->channel_state |=	1 << (adap->stream.props.endpoint-2);
 		else

drivers/media/dvb/dvb-usb/dib0700_devices.c

···
 	.drives = 0x2d98,
 	.diversity_delay = 48,
 	.refclksel = 3,
-	},{
+	}, {
 	.output_mpeg2_in_188_bytes = 1,
 
 	.agc_config_count = 2,
···
 
 
 	if (band == BAND_CBAND) {
-	deb_info("tuning in CBAND - soft-AGC startup\n");
-	/* TODO specific wbd target for dib0090 - needed for startup ? */
-	dib0090_set_tune_state(fe, CT_AGC_START);
-	do {
-		ret = dib0090_gain_control(fe);
-		msleep(ret);
-		tune_state = dib0090_get_tune_state(fe);
-		if (tune_state == CT_AGC_STEP_0)
-			dib8000_set_gpio(fe, 6, 0, 1);
-		else if (tune_state == CT_AGC_STEP_1) {
-			dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
-			if (rf_gain_limit == 0)
-				dib8000_set_gpio(fe, 6, 0, 0);
-		}
-	} while (tune_state < CT_AGC_STOP);
-	dib0090_pwm_gain_reset(fe);
-	dib8000_pwm_agc_reset(fe);
-	dib8000_set_tune_state(fe, CT_DEMOD_START);
+		deb_info("tuning in CBAND - soft-AGC startup\n");
+		dib0090_set_tune_state(fe, CT_AGC_START);
+		do {
+			ret = dib0090_gain_control(fe);
+			msleep(ret);
+			tune_state = dib0090_get_tune_state(fe);
+			if (tune_state == CT_AGC_STEP_0)
+				dib8000_set_gpio(fe, 6, 0, 1);
+			else if (tune_state == CT_AGC_STEP_1) {
+				dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
+				if (rf_gain_limit == 0)
+					dib8000_set_gpio(fe, 6, 0, 0);
+			}
+		} while (tune_state < CT_AGC_STOP);
+		dib0090_pwm_gain_reset(fe);
+		dib8000_pwm_agc_reset(fe);
+		dib8000_set_tune_state(fe, CT_DEMOD_START);
 	} else {
-	deb_info("not tuning in CBAND - standard AGC startup\n");
-	dib0090_pwm_gain_reset(fe);
+		deb_info("not tuning in CBAND - standard AGC startup\n");
+		dib0090_pwm_gain_reset(fe);
 	}
 
 	return 0;
···
 	struct dvb_frontend *fe_slave;
 
 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
 	msleep(1000);
 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
···
 
 	dib0700_ctrl_clock(adap->dev, 72, 1);
 
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
 
 	dib8000_i2c_enumeration(&adap->dev->i2c_adap, 2, 18, 0x80);
···
 	u8 wb[4] = { 0xc >> 8, 0xc & 0xff, 0, 0 };
 	u8 rb[2];
 	struct i2c_msg msg[2] = {
-		{.addr = 0x1e >> 1,.flags = 0,.buf = wb,.len = 2},
-		{.addr = 0x1e >> 1,.flags = I2C_M_RD,.buf = rb,.len = 2},
+		{.addr = 0x1e >> 1, .flags = 0, .buf = wb, .len = 2},
+		{.addr = 0x1e >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
 	};
 	u8 index_data;
 
···
 		return -EIO;
 
 	switch (rb[0] << 8 | rb[1]) {
-		case 0:
+	case 0:
 			deb_info("Found DiB0170 rev1: This version of DiB0170 is not supported any longer.\n");
 			return -EIO;
-		case 1:
+	case 1:
 			deb_info("Found DiB0170 rev2");
 			break;
-		case 2:
+	case 2:
 			deb_info("Found DiB0190 rev2");
 			break;
-		default:
+	default:
 			deb_info("DiB01x0 not found");
 			return -EIO;
-		}
+	}
 
 	for (index_data = 0; index_data < len; index_data += 2) {
 		wb[2] = (data[index_data + 1] >> 8) & 0xff;
···
 			wb[3] |= rb[1] & ~(3 << 4);
 		}
 
-		wb[0] = (data[index_data  ] >> 8)&0xff;
-		wb[1] = (data[index_data  ]     )&0xff;
+		wb[0] = (data[index_data] >> 8)&0xff;
+		wb[1] = (data[index_data])&0xff;
 		msg[0].len = 4;
 		if (i2c_transfer(i2c, &msg[0], 1) != 1)
 			return -EIO;
···
 		.clkoutdrive = 0,
 		.freq_offset_khz_uhf = 0,
 		.freq_offset_khz_vhf = 0,
-	},{
+	}, {
 		.io.pll_bypass = 0,
 		.io.pll_range = 1,
 		.io.pll_prediv = 1,
···
 	dib0700_set_i2c_speed(adap->dev, 340);
 
 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
···
 
 	dib0700_ctrl_clock(adap->dev, 72, 1);
 
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
 
 	dib9000_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, 0x80);
···
 	dib0700_set_i2c_speed(adap->dev, 2000);
 	if (dib9000_firmware_post_pll_init(adap->fe) < 0)
 		return -ENODEV;
-    release_firmware(state->frontend_firmware);
+	release_firmware(state->frontend_firmware);
 	return 0;
 }
 
···
 	dib0700_set_i2c_speed(adap->dev, 340);
 
 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
···
 
 	dib0700_ctrl_clock(adap->dev, 72, 1);
 
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
 
 	if (request_firmware(&state->frontend_firmware, "dib9090.fw", &adap->dev->udev->dev)) {
···
 		if (dib9000_firmware_post_pll_init(fe_slave) < 0)
 			return -ENODEV;
 	}
-    release_firmware(state->frontend_firmware);
+	release_firmware(state->frontend_firmware);
 
 	return 0;
 }
···
 	deb_info("bandwidth = %d fdem_min =%d", fe->dtv_property_cache.bandwidth_hz, fdem_min);
 
 	/* Find Min and Max prediv */
-	while((xtal/max_prediv) >= fcp_min)
+	while ((xtal/max_prediv) >= fcp_min)
 		max_prediv++;
 
 	max_prediv--;
 	min_prediv = max_prediv;
-	while((xtal/min_prediv) <= fcp_max) {
+	while ((xtal/min_prediv) <= fcp_max) {
 		min_prediv--;
-		if(min_prediv == 1)
+		if (min_prediv == 1)
 			break;
 	}
 	deb_info("MIN prediv = %d : MAX prediv = %d", min_prediv, max_prediv);
 
 	min_prediv = 2;
 
-	for(prediv = min_prediv ; prediv < max_prediv; prediv ++) {
+	for (prediv = min_prediv ; prediv < max_prediv; prediv++) {
 		fcp = xtal / prediv;
-		if(fcp > fcp_min && fcp < fcp_max) {
-			for(loopdiv = 1 ; loopdiv < 64 ; loopdiv++) {
+		if (fcp > fcp_min && fcp < fcp_max) {
+			for (loopdiv = 1 ; loopdiv < 64 ; loopdiv++) {
 				fdem = ((xtal/prediv) * loopdiv);
 				fs   = fdem / 4;
 				/* test min/max system restrictions */
 
-				if((fdem >= fdem_min) && (fdem <= fdem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz/1000)) {
+				if ((fdem >= fdem_min) && (fdem <= fdem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz/1000)) {
 					spur = 0;
 					/* test fs harmonics positions */
-					for(harmonic_id = (fe->dtv_property_cache.frequency / (1000*fs)) ;  harmonic_id <= ((fe->dtv_property_cache.frequency / (1000*fs))+1) ; harmonic_id++) {
-						if(((fs*harmonic_id) >= ((fe->dtv_property_cache.frequency/1000) - (fe->dtv_property_cache.bandwidth_hz/2000))) &&  ((fs*harmonic_id) <= ((fe->dtv_property_cache.frequency/1000) + (fe->dtv_property_cache.bandwidth_hz/2000)))) {
+					for (harmonic_id = (fe->dtv_property_cache.frequency / (1000*fs)) ;  harmonic_id <= ((fe->dtv_property_cache.frequency / (1000*fs))+1) ; harmonic_id++) {
+						if (((fs*harmonic_id) >= ((fe->dtv_property_cache.frequency/1000) - (fe->dtv_property_cache.bandwidth_hz/2000))) &&  ((fs*harmonic_id) <= ((fe->dtv_property_cache.frequency/1000) + (fe->dtv_property_cache.bandwidth_hz/2000)))) {
 							spur = 1;
 							break;
 						}
 					}
 
-					if(!spur) {
+					if (!spur) {
 						adc->pll_loopdiv = loopdiv;
 						adc->pll_prediv = prediv;
-						adc->timf = 2396745143UL/fdem*(1<<9);
-						adc->timf+= ((2396745143UL%fdem)<< 9)/fdem;
+						adc->timf = 2396745143UL/fdem*(1 << 9);
+						adc->timf += ((2396745143UL%fdem) << 9)/fdem;
 						deb_info("loopdiv=%i prediv=%i timf=%i", loopdiv, prediv, adc->timf);
 						break;
 					}
···
 	}
 
 
-	if(adc->pll_loopdiv == 0 && adc->pll_prediv == 0) {
+	if (adc->pll_loopdiv == 0 && adc->pll_prediv == 0)
 		return -EINVAL;
-	} else
+	else
 		return 0;
 }
 
···
 	target = (dib0090_get_wbd_offset(fe) * 8 + 1) / 2;
 	dib7000p_set_wbd_ref(fe, target);
 
-	if(dib7090p_get_best_sampling(fe, &adc) == 0) {
+	if (dib7090p_get_best_sampling(fe, &adc) == 0) {
 		pll.pll_ratio  = adc.pll_loopdiv;
 		pll.pll_prediv = adc.pll_prediv;
 
···
 }
 
 static struct dib0090_wbd_slope dib7090_wbd_table[] = {
-	{ 380,   81, 850, 64, 540 ,4},
-	{ 860,   51, 866, 21,  375 ,4},
-	{1700,    0, 250, 0,   100, 6}, //LBAND Predefinition , NOT tested Yet
-	{2600,    0, 250, 0,   100, 6}, //SBAND Predefinition , NOT tested Yet
-	{ 0xFFFF, 0,   0, 0,   0   ,0},
+	{ 380,   81, 850, 64, 540,  4},
+	{ 860,   51, 866, 21,  375, 4},
+	{1700,    0, 250, 0,   100, 6},
+	{2600,    0, 250, 0,   100, 6},
+	{ 0xFFFF, 0,   0, 0,   0,   0},
 };
 
 struct dibx000_agc_config dib7090_agc_config[2] = {
···
 		.band_caps      = BAND_UHF,
 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
 		* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
-		.setup          = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup
+		.setup          = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
 
-		.inv_gain       = 687,// inv_gain = 1/ 95.4dB // no boost, lower gain due to ramp quantification
-		.time_stabiliz  = 10,  // time_stabiliz
+		.inv_gain       = 687,
+		.time_stabiliz  = 10,
 
-		.alpha_level    = 0,  // alpha_level
-		.thlock         = 118,  // thlock
+		.alpha_level    = 0,
+		.thlock         = 118,
 
-		.wbd_inv        = 0,     // wbd_inv
-		.wbd_ref        = 1200,  // wbd_ref
-		.wbd_sel        = 3,     // wbd_sel
-		.wbd_alpha      = 5,     // wbd_alpha
+		.wbd_inv        = 0,
+		.wbd_ref        = 1200,
+		.wbd_sel        = 3,
+		.wbd_alpha      = 5,
 
-		.agc1_max       = 65535,  // agc1_max
-		.agc1_min       = 0,  // agc1_min
+		.agc1_max       = 65535,
+		.agc1_min       = 0,
 
-		.agc2_max       = 65535,  // agc2_max
-		.agc2_min       = 0,      // agc2_min
+		.agc2_max       = 65535,
+		.agc2_min       = 0,
 
-		.agc1_pt1       = 0,      // agc1_pt1
-		.agc1_pt2       = 32,     // agc1_pt2
-		.agc1_pt3       = 114,    // agc1_pt3  // 40.4dB
-		.agc1_slope1    = 143,    // agc1_slope1
-		.agc1_slope2    = 144,    // agc1_slope2
-		.agc2_pt1       = 114,    // agc2_pt1
-		.agc2_pt2       = 227,    // agc2_pt2
-		.agc2_slope1    = 116,    // agc2_slope1
-		.agc2_slope2    = 117,    // agc2_slope2
+		.agc1_pt1       = 0,
+		.agc1_pt2       = 32,
+		.agc1_pt3       = 114,
+		.agc1_slope1    = 143,
+		.agc1_slope2    = 144,
+		.agc2_pt1       = 114,
+		.agc2_pt2       = 227,
+		.agc2_slope1    = 116,
+		.agc2_slope2    = 117,
 
-		.alpha_mant     = 18,  // alpha_mant // 5Hz with 95.4dB
-		.alpha_exp      = 0,   // alpha_exp
-		.beta_mant      = 20,  // beta_mant
-		.beta_exp       = 59,  // beta_exp
+		.alpha_mant     = 18,
+		.alpha_exp      = 0,
+		.beta_mant      = 20,
+		.beta_exp       = 59,
 
-		.perform_agc_softsplit = 0,  // perform_agc_softsplit
+		.perform_agc_softsplit = 0,
 	} , {
 		.band_caps      = BAND_FM | BAND_VHF | BAND_CBAND,
 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
 		* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
-		.setup          = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup
+		.setup          = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
 
-		.inv_gain       = 732,// inv_gain = 1/ 89.5dB // no boost, lower gain due to ramp quantification
-		.time_stabiliz  = 10,  // time_stabiliz
+		.inv_gain       = 732,
+		.time_stabiliz  = 10,
 
-		.alpha_level    = 0,  // alpha_level
-		.thlock         = 118,  // thlock
+		.alpha_level    = 0,
+		.thlock         = 118,
 
-		.wbd_inv        = 0,     // wbd_inv
-		.wbd_ref        = 1200,  // wbd_ref
-		.wbd_sel        = 3,     // wbd_sel
-		.wbd_alpha      = 5,     // wbd_alpha
+		.wbd_inv        = 0,
+		.wbd_ref        = 1200,
+		.wbd_sel        = 3,
+		.wbd_alpha      = 5,
 
-		.agc1_max       = 65535,  // agc1_max : 1
-		.agc1_min       = 0,      // agc1_min
+		.agc1_max       = 65535,
+		.agc1_min       = 0,
 
-		.agc2_max       = 65535,  // agc2_max
-		.agc2_min       = 0,      // agc2_min
+		.agc2_max       = 65535,
+		.agc2_min       = 0,
 
-		.agc1_pt1       = 0,      // agc1_pt1
-		.agc1_pt2       = 0,      // agc1_pt2
-		.agc1_pt3       = 98,     // agc1_pt3  // 34.5dB CBAND P1G + 55dB BB boost = 89.5dB
-		.agc1_slope1    = 0,      // agc1_slope1
-		.agc1_slope2    = 167,    // agc1_slope2 = Dy/Dx * 2**6 * 2**8 = 1/98 * 2**6 *2**8 : Dy = 1
-		.agc1_pt1       = 98,     // agc2_pt1
-		.agc2_pt2       = 255,    // agc2_pt2
-		.agc2_slope1    = 104,    // agc2_slope1 = Dy/Dx * 2**6 * 2**8 = 1/(255-98) * 2**6 *2**8
-		.agc2_slope2    = 0,      // agc2_slope2
+		.agc1_pt1       = 0,
+		.agc1_pt2       = 0,
+		.agc1_pt3       = 98,
+		.agc1_slope1    = 0,
+		.agc1_slope2    = 167,
+		.agc1_pt1       = 98,
+		.agc2_pt2       = 255,
+		.agc2_slope1    = 104,
+		.agc2_slope2    = 0,
 
-		.alpha_mant     = 18,  // alpha_mant // 5Hz with 95.4dB
-		.alpha_exp      = 0,   // alpha_exp
-		.beta_mant      = 20,  // beta_mant
-		.beta_exp       = 59,  // beta_exp
+		.alpha_mant     = 18,
+		.alpha_exp      = 0,
+		.beta_mant      = 20,
+		.beta_exp       = 59,
 
-		.perform_agc_softsplit = 0,  // perform_agc_softsplit
+		.perform_agc_softsplit = 0,
 	}
 };
 
 static struct dibx000_bandwidth_config dib7090_clock_config_12_mhz = {
-	60000, 15000, // internal, sampling
-	1, 5, 0, 0, 0, // pll_cfg: prediv, ratio, range, reset, bypass
-	0, 0, 1, 1, 2, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc, modulo
-	(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k
-	(0 << 25) | 0, // ifreq = 0.000000 MHz
-	20452225, // timf
-	15000000, // xtal_hz
+	60000, 15000,
+	1, 5, 0, 0, 0,
+	0, 0, 1, 1, 2,
+	(3 << 14) | (1 << 12) | (524 << 0),
+	(0 << 25) | 0,
+	20452225,
+	15000000,
 };
 
 static struct dib7000p_config nim7090_dib7000p_config = {
···
 		.output_mode				= OUTMODE_MPEG2_PAR_GATED_CLK,
 		.default_i2c_addr			= 0x90,
 		.enMpegOutput				= 1,
-	},{
+	}, {
 		.output_mpeg2_in_188_bytes  = 1,
 		.hostbus_diversity			= 1,
 		.tuner_is_baseband			= 1,
···
 		.data_tx_drv = 0,
 		.low_if = NULL,
 		.in_soc = 1,
-	},{
+	}, {
 		.io.clock_khz = 12000,
 		.io.pll_bypass = 0,
 		.io.pll_range = 0,
···
 static int nim7090_frontend_attach(struct dvb_usb_adapter *adap)
 {
 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
 
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
 
 	if (dib7000p_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, &nim7090_dib7000p_config) != 0) {
···
 	st->disable_streaming_master_mode = 1;
 
 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
 
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
-	msleep(10);
+	msleep(20);
 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
 
 	/* initialize IC 0 */
···
 	dib0700_set_i2c_speed(adap->dev, 340);
 	adap->fe = dvb_attach(dib7000p_attach, &adap->dev->i2c_adap, 0x90, &tfe7090pvr_dib7000p_config[0]);
 
-    dib7090_slave_reset(adap->fe);
+	dib7090_slave_reset(adap->fe);
 
 	if (adap->fe == NULL)
 		return -ENODEV;

drivers/media/dvb/frontends/dib0090.c

···
 {
 	u8 b[2];
 	struct i2c_msg msg[2] = {
-		{.addr = state->config->i2c_address,.flags = 0,.buf = &reg,.len = 1},
-		{.addr = state->config->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2},
+		{.addr = state->config->i2c_address, .flags = 0, .buf = &reg, .len = 1},
+		{.addr = state->config->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2},
 	};
 	if (i2c_transfer(state->i2c, msg, 2) != 2) {
 		printk(KERN_WARNING "DiB0090 I2C read failed\n");
···
 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
 {
 	u8 b[3] = { reg & 0xff, val >> 8, val & 0xff };
-	struct i2c_msg msg = {.addr = state->config->i2c_address,.flags = 0,.buf = b,.len = 3 };
+	struct i2c_msg msg = {.addr = state->config->i2c_address, .flags = 0, .buf = b, .len = 3 };
 	if (i2c_transfer(state->i2c, &msg, 1) != 1) {
 		printk(KERN_WARNING "DiB0090 I2C write failed\n");
 		return -EREMOTEIO;
···
 static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
 {
 	u8 b[2];
-	struct i2c_msg msg = {.addr = reg,.flags = I2C_M_RD,.buf = b,.len = 2 };
+	struct i2c_msg msg = {.addr = reg, .flags = I2C_M_RD, .buf = b, .len = 2 };
 	if (i2c_transfer(state->i2c, &msg, 1) != 1) {
 		printk(KERN_WARNING "DiB0090 I2C read failed\n");
 		return 0;
···
 static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
 {
 	u8 b[2] = { val >> 8, val & 0xff };
-	struct i2c_msg msg = {.addr = reg,.flags = 0,.buf = b,.len = 2 };
+	struct i2c_msg msg = {.addr = reg, .flags = 0, .buf = b, .len = 2 };
 	if (i2c_transfer(state->i2c, &msg, 1) != 1) {
 		printk(KERN_WARNING "DiB0090 I2C write failed\n");
 		return -EREMOTEIO;
···
 
 	return 0;
 
- identification_error:
+identification_error:
 	return -EIO;
 }
 
···
 
 	if (identity->product != KROSUS)
 		goto identification_error;
-
-	//From the SOC the version definition has changed
 
 	if ((identity->version & 0x3) == SOC) {
 		identity->in_soc = 1;
···
 
 	return 0;
 
- identification_error:
+identification_error:
 	return -EIO;;
 }
 
···
 		if (state->current_band == BAND_VHF) {
 			if (state->identity.in_soc) {
 				dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
-				//dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf_socs); /* TODO */
 			} else {
 				dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
 				dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
···
 static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
 {
 	u16 adc_val = dib0090_read_reg(state, 0x1d);
-	if (state->identity.in_soc) {
+	if (state->identity.in_soc)
 		adc_val >>= 2;
-	}
 	return adc_val;
 }
 
···
 #ifdef DEBUG_AGC
 		dprintk
 			("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
-			 (u32) * tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
+			 (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
 			 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
 #endif
 	}
···
 	if (current_temp > 128)
 		current_temp = 128;
 
-	//What Wbd gain to apply for this range of frequency
 	state->wbdmux &= ~(7 << 13);
 	if (wbd->wbd_gain != 0)
 		state->wbdmux |= (wbd->wbd_gain << 13);
 	else
-		state->wbdmux |= (4 << 13);	// 4 is the default WBD gain
+		state->wbdmux |= (4 << 13);
 
 	dib0090_write_reg(state, 0x10, state->wbdmux);
 
-	//All the curves are linear with slope*f/64+offset
 	wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
 	wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
 
-	// Iet assumes that thot-tcold = 130 equiv 128, current temperature ref is -30deg
-
 	wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
 
-	//for (offset = 0; offset < 1000; offset += 4)
-	//	dbgp("offset = %d -> %d\n", offset, dib0090_wbd_to_db(state, offset));
-	state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);	// get the value in dBm from the offset
+	state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);
 	dprintk("wbd-target: %d dB", (u32) state->wbd_target);
 	dprintk("wbd offset applied is %d", wbd_tcold);
 
···
 };
 
 static const u16 dib0090_p1g_additionnal_defaults[] = {
-	// additionnal INITIALISATION for p1g to be written after dib0090_defaults
 	1, 0x05,
 	0xabcd,
 
···
 
 void dib0090_set_EFUSE(struct dib0090_state *state)
 {
-    u8 c,h,n;
-    u16 e2,e4;
-    u16 cal;
+	u8 c, h, n;
+	u16 e2, e4;
+	u16 cal;
 
-    e2=dib0090_read_reg(state,0x26);
-    e4=dib0090_read_reg(state,0x28);
+	e2 = dib0090_read_reg(state, 0x26);
+	e4 = dib0090_read_reg(state, 0x28);
 
-    if ((state->identity.version == P1D_E_F) || // All P1F uses the internal calibration
-        (state->identity.version == P1G) || (e2 == 0xffff)) {	//W0090G11R1 and W0090G11R1-D  : We will find the calibration Value of the Baseband
+	if ((state->identity.version == P1D_E_F) ||
+			(state->identity.version == P1G) || (e2 == 0xffff)) {
 
-        dib0090_write_reg(state,0x22,0x10); //Start the Calib
-        cal = (dib0090_read_reg(state,0x22)>>6) & 0x3ff;
+		dib0090_write_reg(state, 0x22, 0x10);
+		cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;
 
-        if ((cal<670) || (cal==1023)) //Cal at 800 would give too high value for the n
-            cal=850; //Recenter the n to 32
-        n = 165 - ((cal * 10)>>6) ;
-        e2 = e4 = (3<<12) | (34<<6) | (n);
-    }
+		if ((cal < 670) || (cal == 1023))
+			cal = 850;
+		n = 165 - ((cal * 10)>>6) ;
+		e2 = e4 = (3<<12) | (34<<6) | (n);
+	}
 
-    if (e2!=e4) {
-        e2 &= e4; /* Remove the redundancy  */
-    }
+	if (e2 != e4)
+		e2 &= e4; /* Remove the redundancy  */
 
-    if (e2 != 0xffff) {
-        c = e2 & 0x3f;
-        n = (e2 >> 12) & 0xf;
-        h= (e2 >> 6) & 0x3f;
+	if (e2 != 0xffff) {
+		c = e2 & 0x3f;
+		n = (e2 >> 12) & 0xf;
+		h = (e2 >> 6) & 0x3f;
 
-        if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
-            c=32;
-        if ((h >= HR_MAX) || (h <= HR_MIN))
-            h=34;
-        if ((n >= POLY_MAX) || (n <= POLY_MIN))
-            n=3;
+		if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
+			c = 32;
+		if ((h >= HR_MAX) || (h <= HR_MIN))
+			h = 34;
+		if ((n >= POLY_MAX) || (n <= POLY_MIN))
+			n = 3;
 
-        dib0090_write_reg(state,0x13, (h << 10)) ;
-        e2 = (n<<11) | ((h>>2)<<6) | (c);
-        dib0090_write_reg(state,0x2, e2) ; /* Load the BB_2 */
-    }
+		dib0090_write_reg(state, 0x13, (h << 10)) ;
+		e2 = (n<<11) | ((h>>2)<<6) | (c);
+		dib0090_write_reg(state, 0x2, e2) ; /* Load the BB_2 */
+	}
 }
 
 static int dib0090_reset(struct dvb_frontend *fe)
···
 
 	dib0090_set_default_config(state, dib0090_defaults);
 
-    if (state->identity.in_soc)
-        dib0090_write_reg(state, 0x18, 0x2910);  /* charge pump current = 0 */
+	if (state->identity.in_soc)
+		dib0090_write_reg(state, 0x18, 0x2910);  /* charge pump current = 0 */
 
 	if (state->identity.p1g)
 		dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
 
-    if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc)) /* Update the efuse : Only available for KROSUS > P1C  and SOC as well*/
-        dib0090_set_EFUSE(state);
+	/* Update the efuse : Only available for KROSUS > P1C  and SOC as well*/
+	if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc))
+		dib0090_set_EFUSE(state);
 
 	/* Congigure in function of the crystal */
 	if (state->config->io.clock_khz >= 24000)
···
 static const struct dc_calibration dc_p1g_table[] = {
 	/* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
 	/* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
-	{0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},	// offset_trim2_i_chann  0   0   5    0    0    1    6     9    5
-	{0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},	// offset_trim2_q_chann  0   0   5    0    0    1    7     15   11
+	{0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
+	{0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
 	/* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
-	{0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},	// offset_trim1_i_chann  0   0   5    0    0    1    6     4    0
-	{0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},	// offset_trim1_q_chann  0   0   5    0    0    1    6     14   10
+	{0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
+	{0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
 	{0},
 };
 
···
 		dib0090_write_reg(state, 0x24, reg);
 
 		state->wbdmux = dib0090_read_reg(state, 0x10);
-		dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);	// connect BB, disable WDB enable*
-		dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));	//Discard the DataTX
+		dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);
+		dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
 
 		state->dc = dc_table;
 
···
 		if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
 			/* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
 			state->step++;
-			state->min_adc_diff = state->adc_diff;	//min is used as N-1
+			state->min_adc_diff = state->adc_diff;
 			*tune_state = CT_TUNER_STEP_1;
 		} else {
 			/* the minimum was what we have seen in the step before */
-			if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) {	//Come back to the previous state since the delta was better
+			if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) {
 				dprintk("Since adc_diff N = %d  > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_diff);
 				state->step--;
 			}
···
 		break;
 
 	case CT_TUNER_STEP_6:
-		dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);	//Force the test bus to be off
+		dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
 		dib0090_write_reg(state, 0x1f, 0x7);
 		*tune_state = CT_TUNER_START;	/* reset done -> real tuning can now begin */
 		state->calibrate &= ~DC_CAL;
···
 			return 0;
 		}
 
-		dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));	// Force: WBD enable,gain to 4, mux to WBD
+		dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));
 
-		dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));	//Discard all LNA but crystal !!!
+		dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));
 		*tune_state = CT_TUNER_STEP_0;
 		state->wbd_calibration_gain = wbd_gain;
 		return 90;	/* wait for the WBDMUX to switch and for the ADC to sample */
···
 };
 
 static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
-	//max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
 #ifdef CONFIG_BAND_CBAND
-	{170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},	// FM EN_CAB
+	{170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
 #endif
 #ifdef CONFIG_BAND_VHF
-	{184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},	// VHF EN_VHF
-	{227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},	// VHF EN_VHF
-	{380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},	// VHF EN_VHF
+	{184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+	{227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+	{380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
 #endif
 #ifdef CONFIG_BAND_UHF
-	{510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
+	{510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
 #endif
 #ifdef CONFIG_BAND_LBAND
-	{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},	// LBD EN_LBD
-	{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},	// LBD EN_LBD
-	{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},	// LBD EN_LBD
+	{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+	{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+	{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
 #endif
 #ifdef CONFIG_BAND_SBAND
-	{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},	// SBD EN_SBD
-	{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},	// SBD EN_SBD
+	{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
+	{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
 #endif
 };
 
 static const struct dib0090_pll dib0090_p1g_pll_table[] = {
 #ifdef CONFIG_BAND_CBAND
-	{57000, 0, 11, 48, 6},	// CAB
-	{70000, 1, 11, 48, 6},	// CAB
-	{86000, 0, 10, 32, 4},	// CAB
-	{105000, 1, 10, 32, 4},	// FM
-	{115000, 0, 9, 24, 6},	// FM
-	{140000, 1, 9, 24, 6},	// MID FM VHF
-	{170000, 0, 8, 16, 4},	// MID FM VHF
+	{57000, 0, 11, 48, 6},
+	{70000, 1, 11, 48, 6},
+	{86000, 0, 10, 32, 4},
+	{105000, 1, 10, 32, 4},
+	{115000, 0, 9, 24, 6},
+	{140000, 1, 9, 24, 6},
+	{170000, 0, 8, 16, 4},
 #endif
 #ifdef CONFIG_BAND_VHF
-	{200000, 1, 8, 16, 4},	// VHF
-	{230000, 0, 7, 12, 6},	// VHF
-	{280000, 1, 7, 12, 6},	// MID VHF UHF
-	{340000, 0, 6, 8, 4},	// MID VHF UHF
-	{380000, 1, 6, 8, 4},	// MID VHF UHF
-	{455000, 0, 5, 6, 6},	// MID VHF UHF
+	{200000, 1, 8, 16, 4},
+	{230000, 0, 7, 12, 6},
+	{280000, 1, 7, 12, 6},
+	{340000, 0, 6, 8, 4},
+	{380000, 1, 6, 8, 4},
+	{455000, 0, 5, 6, 6},
 #endif
 #ifdef CONFIG_BAND_UHF
-	{580000, 1, 5, 6, 6},	// UHF
-	{680000, 0, 4, 4, 4},	// UHF
-	{860000, 1, 4, 4, 4},	// UHF
+	{580000, 1, 5, 6, 6},
+	{680000, 0, 4, 4, 4},
+	{860000, 1, 4, 4, 4},
 #endif
 #ifdef CONFIG_BAND_LBAND
-	{1800000, 1, 2, 2, 4},	// LBD
+	{1800000, 1, 2, 2, 4},
 #endif
 #ifdef CONFIG_BAND_SBAND
-	{2900000, 0, 1, 1, 6},	// SBD
+	{2900000, 0, 1, 1, 6},
 #endif
 };
 
 static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
-	//max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
 #ifdef CONFIG_BAND_CBAND
-	{184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},	// FM EN_CAB      // 0x8190 Good perf but higher current //0x4187 Low current
-	{227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},	// FM EN_CAB
-	{380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},	// FM EN_CAB
+	{184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
+	{227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
+	{380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
 #endif
 #ifdef CONFIG_BAND_UHF
-	{520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
-	{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},	// UHF
+	{520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+	{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
 #endif
 #ifdef CONFIG_BAND_LBAND
-	{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},	// LBD EN_LBD
-	{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},	// LBD EN_LBD
-	{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},	// LBD EN_LBD
+	{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+	{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+	{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
 #endif
 #ifdef CONFIG_BAND_SBAND
-	{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},	// SBD EN_SBD
-	{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},	// SBD EN_SBD
+	{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
+	{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
 #endif
 };
 
 static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
-	//max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
 #ifdef CONFIG_BAND_CBAND
-	//{ 184000,  4,  3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB }, // 0x81ce 0x8190 Good perf but higher current //0x4187 Low current
 	{300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
-	{380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},	//0x4187
+	{380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
 	{570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
 	{858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
 #endif
···
 				state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
 			}
 		}
-		state->adc_diff = 3000;	// start with a unreachable high number : only set for KROSUS < P1G */
+		state->adc_diff = 3000;
 		*tune_state = CT_TUNER_STEP_0;
 
 	} else if (*tune_state == CT_TUNER_STEP_0) {
 		if (state->identity.p1g && !force_soft_search) {
-			// 30MHz => Code 15 for the ration => 128us to lock. Giving approximately
-			u8 ratio = 31;	// (state->config->io.clock_khz / 1024 + 1) & 0x1f;
+			u8 ratio = 31;
 
 			dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
 			dib0090_read_reg(state, 0x40);
-			//dib0090_write_reg(state, 0x40, (3<<7) | ((((state->config->io.clock_khz >> 11)+1) & 0x1f)<<2) | (1<<1) | 1);
 			ret = 50;
 		} else {
 			state->step /= 2;
···
 				dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
 				state->adc_diff = adc;
 				state->fcaptrim = state->captrim;
-				//we could break here, to save time, if we reached a close-enough value
-				//e.g.: if (state->adc_diff < 20)
-				//break;
 			}
 
 			state->captrim += step_sign * state->step;
···
 			else
 				*tune_state = CT_TUNER_STEP_2;
 
-			ret = 25;	//LOLO changed from 15
+			ret = 25;
 		}
 	} else if (*tune_state == CT_TUNER_STEP_2) {	/* this step is only used by krosus < P1G */
 		/*write the final cptrim config */
···
 	int ret = 15;
 	s16 val;
 
-	//The assumption is that the AGC is not active
 	switch (*tune_state) {
 	case CT_TUNER_START:
 		state->wbdmux = dib0090_read_reg(state, 0x10);
-		dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));	//Move to the bias and clear the wbd enable
+		dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));
 
 		state->bias = dib0090_read_reg(state, 0x13);
-		dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));	//Move to the Ref
+		dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));
 
 		*tune_state = CT_TUNER_STEP_0;
 		/* wait for the WBDMUX to switch and for the ADC to sample */
 		break;
 
 	case CT_TUNER_STEP_0:
-		state->adc_diff = dib0090_get_slow_adc_val(state);	// Get the value for the Ref
-		dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));	//Move to the Ptat
+		state->adc_diff = dib0090_get_slow_adc_val(state);
+		dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));
 		*tune_state = CT_TUNER_STEP_1;
 		break;
 
 	case CT_TUNER_STEP_1:
-		val = dib0090_get_slow_adc_val(state);	// Get the value for the Ptat
-		state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;	// +55 is defined as = -30deg
+		val = dib0090_get_slow_adc_val(state);
+		state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;
 
 		dprintk("temperature: %d C", state->temperature - 30);
 
···
 		break;
 
 	case CT_TUNER_STEP_2:
-		//Reload the start values.
 		dib0090_write_reg(state, 0x13, state->bias);
 		dib0090_write_reg(state, 0x10, state->wbdmux);	/* write back original WBDMUX */
 
 		*tune_state = CT_TUNER_START;
 		state->calibrate &= ~TEMP_CAL;
 		if (state->config->analog_output == 0)
-			dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));	//Set the DataTX
+			dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
 
 		break;
 
···
 		/* deactivate DataTX before some calibrations */
 		if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
 			dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
-		else /* Activate DataTX in case a calibration has been done before */ if (state->config->analog_output == 0)
-			dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
+		else
+			/* Activate DataTX in case a calibration has been done before */
+			if (state->config->analog_output == 0)
+				dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
 	}
 
 	if (state->calibrate & DC_CAL)
 		return dib0090_dc_offset_calibration(state, tune_state);
 	else if (state->calibrate & WBD_CAL) {
-		if (state->current_rf == 0) {
+		if (state->current_rf == 0)
 			state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
-		}
 		return dib0090_wbd_calibration(state, tune_state);
 	} else if (state->calibrate & TEMP_CAL)
 		return dib0090_get_temperature(state, tune_state);
···
 		if (state->config->use_pwm_agc && state->identity.in_soc) {
 			tmp = dib0090_read_reg(state, 0x39);
 			if ((tmp >> 10) & 0x1)
-				dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));	// disengage mux : en_mux_bb1 = 0
+				dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));
 		}
 
 		state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
···
 			state->current_tune_table_index = tune;
 			state->current_pll_table_index = pll;
 
-			// select internal switch
 			dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
 
-			// Find the VCO frequency in MHz
 			VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
 
-			FREF = state->config->io.clock_khz;	// REFDIV is 1FREF Has to be as Close as possible to 10MHz
+			FREF = state->config->io.clock_khz;
 			if (state->config->fref_clock_ratio != 0)
 				FREF /= state->config->fref_clock_ratio;
 
-			// Determine the FB divider
-			// The reference is 10MHz, Therefore the FBdivider is on the first digits
 			FBDiv = (VCOF_kHz / pll->topresc / FREF);
-			Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;	//in kHz
+			Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
 
-			// Avoid Spurs in the loopfilter bandwidth
 			if (Rest < LPF)
 				Rest = 0;
 			else if (Rest < 2 * LPF)
···
 			else if (Rest > (FREF - LPF)) {
 				Rest = 0;
 				FBDiv += 1;
-			}	//Go to the next FB
-			else if (Rest > (FREF - 2 * LPF))
+			} else if (Rest > (FREF - 2 * LPF))
 				Rest = FREF - 2 * LPF;
 			Rest = (Rest * 6528) / (FREF / 10);
 			state->rest = Rest;
···
 			if (Rest == 0) {
 				if (pll->vco_band)
 					lo5 = 0x049f;
-				//else if (state->config->analog_output)
-				//	lo5 = 0x041f;
 				else
 					lo5 = 0x041f;
 			} else {
···
 					else
 						lo5 = 0x42f;
 				} else
-					lo5 = 0x42c;	//BIAS Lo set to 4 by default in case of the Captrim search does not take care of the VCO Bias
+					lo5 = 0x42c;
 			}
 
 			lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7);	/* bit 15 is the split to the slave, we do not do it here */
 
-			//Internal loop filter set...
 			if (!state->config->io.pll_int_loop_filt) {
 				if (state->identity.in_soc)
 					lo6 = 0xff98;
···
 				else
 					lo6 = 0xff28;
 			} else
-				lo6 = (state->config->io.pll_int_loop_filt << 3);	// take the loop filter value given by the layout
-			//dprintk("lo6 = 0x%04x", (u32)lo6);
+				lo6 = (state->config->io.pll_int_loop_filt << 3);
 
 			Den = 1;
 
 			if (Rest > 0) {
 				if (state->config->analog_output)
-					lo6 |= (1 << 2) | 2;	//SigmaDelta and Dither
+					lo6 |= (1 << 2) | 2;
 				else {
 					if (state->identity.in_soc)
-						lo6 |= (1 << 2) | 2;	//SigmaDelta and Dither
+						lo6 |= (1 << 2) | 2;
 					else
-						lo6 |= (1 << 2) | 2;	//SigmaDelta and Dither
+						lo6 |= (1 << 2) | 2;
 				}
 				Den = 255;
 			}
-			// Now we have to define the Num and Denum
-			// LO1 gets the FBdiv
 			dib0090_write_reg(state, 0x15, (u16) FBDiv);
-			// LO2 gets the REFDiv
 			if (state->config->fref_clock_ratio != 0)
 				dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
 			else
 				dib0090_write_reg(state, 0x16, (Den << 8) | 1);
-			// LO3 for the Numerator
 			dib0090_write_reg(state, 0x17, (u16) Rest);
-			// VCO and HF DIV
 			dib0090_write_reg(state, 0x19, lo5);
-			// SIGMA Delta
 			dib0090_write_reg(state, 0x1c, lo6);
 
-			// Check if the 0090 is analogged configured
-			//Disable ADC and DigPLL =0xFF9F, 0xffbf for test purposes.
-			//Enable The Outputs of the BB on DATA_Tx
 			lo6 = tune->tuner_enable;
 			if (state->config->analog_output)
 				lo6 = (lo6 & 0xff9f) | 0x2;
···
 	else if (*tune_state == CT_TUNER_STEP_0) {	/* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
 		const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
 
-//	if(!state->identity.p1g) {
 		while (state->current_rf / 1000 > wbd->max_freq)
 			wbd++;
-//	}
 
 		dib0090_write_reg(state, 0x1e, 0x07ff);
 		dprintk("Final Captrim: %d", (u32) state->fcaptrim);
···
 
 #define WBD     0x781		/* 1 1 1 1 0000 0 0 1 */
 		c = 4;
-		i = 3;		//wbdmux_bias
+		i = 3;
 
-		if (wbd->wbd_gain != 0)	//&& !state->identity.p1g)
+		if (wbd->wbd_gain != 0)
 			c = wbd->wbd_gain;
 
-		//Store wideband mux register.
 		state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
 		dib0090_write_reg(state, 0x10, state->wbdmux);
 
···
 	} else if (*tune_state == CT_TUNER_STEP_1) {
 		/* initialize the lt gain register */
 		state->rf_lt_def = 0x7c00;
-		// dib0090_write_reg(state, 0x0f, state->rf_lt_def);
 
 		dib0090_set_bandwidth(state);
 		state->tuner_is_tuned = 1;
 
-//	if(!state->identity.p1g)
-		state->calibrate |= WBD_CAL;	// TODO: only do the WBD calibration for new tune
-//
-		state->calibrate |= TEMP_CAL;	// Force the Temperature to be remesured at next TUNE.
+		state->calibrate |= WBD_CAL;
+		state->calibrate |= TEMP_CAL;
 		*tune_state = CT_TUNER_STOP;
 	} else
 		ret = FE_CALLBACK_TIME_NEVER;
···
 static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
 	{470, 0, 250, 0, 100, 4},
 	{860, 51, 866, 21, 375, 4},
-	{1700, 0, 800, 0, 850, 4},	//LBAND Predefinition , to calibrate
-	{2900, 0, 250, 0, 100, 6},	//SBAND Predefinition , NOT tested Yet
+	{1700, 0, 800, 0, 850, 4},
+	{2900, 0, 250, 0, 100, 6},
 	{0xFFFF, 0, 0, 0, 0, 0},
 };
 
···
 	memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
 
 	return fe;
- free_mem:
+free_mem:
 	kfree(st);
 	fe->tuner_priv = NULL;
 	return NULL;
 }
-
 EXPORT_SYMBOL(dib0090_fw_register);
 
 MODULE_AUTHOR("Patrick Boettcher <[e-mail]>");

drivers/media/dvb/frontends/dib7000p.c

···
 	u8 wb[2] = { reg >> 8, reg & 0xff };
 	u8 rb[2];
 	struct i2c_msg msg[2] = {
-		{.addr = state->i2c_addr >> 1,.flags = 0,.buf = wb,.len = 2},
-		{.addr = state->i2c_addr >> 1,.flags = I2C_M_RD,.buf = rb,.len = 2},
+		{.addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
+		{.addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
 	};
 
 	if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
···
 		(val >> 8) & 0xff, val & 0xff,
 	};
 	struct i2c_msg msg = {
-		.addr = state->i2c_addr >> 1,.flags = 0,.buf = b,.len = 4
+		.addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
 	};
 	return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
 }
···
 	dprintk("setting output mode for demod %p to %d", &state->demod, mode);
 
 	switch (mode) {
-	case OUTMODE_MPEG2_PAR_GATED_CLK:	// STBs with parallel gated clock
+	case OUTMODE_MPEG2_PAR_GATED_CLK:
 		outreg = (1 << 10);	/* 0x0400 */
 		break;
-	case OUTMODE_MPEG2_PAR_CONT_CLK:	// STBs with parallel continues clock
+	case OUTMODE_MPEG2_PAR_CONT_CLK:
 		outreg = (1 << 10) | (1 << 6);	/* 0x0440 */
 		break;
-	case OUTMODE_MPEG2_SERIAL:	// STBs with serial input
+	case OUTMODE_MPEG2_SERIAL:
 		outreg = (1 << 10) | (2 << 6) | (0 << 1);	/* 0x0480 */
 		break;
 	case OUTMODE_DIVERSITY:
···
 		else
 			outreg = (1 << 11);
 		break;
-	case OUTMODE_MPEG2_FIFO:	// e.g. USB feeding
+	case OUTMODE_MPEG2_FIFO:
 		smo_mode |= (3 << 1);
 		fifo_threshold = 512;
 		outreg = (1 << 10) | (5 << 6);
···
 	case OUTMODE_ANALOG_ADC:
 		outreg = (1 << 10) | (3 << 6);
 		break;
-	case OUTMODE_HIGH_Z:	// disable
+	case OUTMODE_HIGH_Z:
 		outreg = 0;
 		break;
 	default:
···
 		reg_909 &= 0x0003;
 		break;
 
-	case DIBX000_ADC_OFF:	// leave the VBG voltage on
+	case DIBX000_ADC_OFF:
 		reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
 		reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
 		break;
···
 static int dib7000p_sad_calib(struct dib7000p_state *state)
 {
 /* internal */
-//	dib7000p_write_word(state, 72, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth
 	dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
 
 	if (state->version == SOC7090)
-		dib7000p_write_word(state, 74, 2048);	// P_sad_calib_value = (0.9/1.8)*4096
+		dib7000p_write_word(state, 74, 2048);
 	else
-		dib7000p_write_word(state, 74, 776);	// P_sad_calib_value = 0.625*3.3 / 4096
+		dib7000p_write_word(state, 74, 776);
 
 	/* do the calibration */
 	dib7000p_write_word(state, 73, (1 << 0));
···
 	if (state->version == SOC7090) {
 		dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
 
-		while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1) {
-		}
+		while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
+			;
 
 		dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
 	} else {
···
 		dprintk("Updating pll (prediv: old =  %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
 		reg_1856 &= 0xf000;
 		reg_1857 = dib7000p_read_word(state, 1857);
-		dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));	// desable pll
+		dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
 
 		dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
 
···
 		dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
 		dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
 
-		dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));	// enable pll
+		dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
 
-		while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1) {
+		while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
 			dprintk("Waiting for PLL to lock");
-		}
 
 		return 0;
 	}
···
 	0xd4c0,
 
 	1, 26,
-	0x6680,			// P_timf_alpha=6, P_corm_alpha=6, P_corm_thres=128 default: 6,4,26
+	0x6680,
 
 	/* set ADC level to -16 */
 	11, 79,
···
 	(1 << 13) - 501 - 117,
 
 	1, 142,
-	0x0410,			// P_palf_filter_on=1, P_palf_filter_freeze=0, P_palf_alpha_regul=16
+	0x0410,
 
 	/* disable power smoothing */
 	8, 145,
···
 	0,
 
 	1, 154,
-	1 << 13,		// P_fft_freq_dir=1, P_fft_nb_to_cut=0
+	1 << 13,
 
 	1, 168,
-	0x0ccd,			// P_pha3_thres, default 0x3000
-
-//	1, 169,
-//		0x0010, // P_cti_use_cpe=0, P_cti_use_prog=0, P_cti_win_len=16, default: 0x0010
+	0x0ccd,
 
 	1, 183,
-	0x200f,			// P_cspu_regul=512, P_cspu_win_cut=15, default: 0x2005
+	0x200f,
 
 	1, 212,
-		0x169,  // P_vit_ksi_dwn = 5 P_vit_ksi_up = 5       0x1e1, // P_vit_ksi_dwn = 4 P_vit_ksi_up = 7
+		0x169,
 
 	5, 187,
-	0x023d,			// P_adp_regul_cnt=573, default: 410
-	0x00a4,			// P_adp_noise_cnt=
-	0x00a4,			// P_adp_regul_ext
-	0x7ff0,			// P_adp_noise_ext
-	0x3ccc,			// P_adp_fil
+	0x023d,
+	0x00a4,
+	0x00a4,
+	0x7ff0,
+	0x3ccc,
 
 	1, 198,
-	0x800,			// P_equal_thres_wgn
+	0x800,
 
 	1, 222,
-	0x0010,			// P_fec_ber_rs_len=2
+	0x0010,
 
 	1, 235,
-	0x0062,			// P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
+	0x0062,
 
 	2, 901,
-	0x0006,			// P_clk_cfg1
-	(3 << 10) | (1 << 6),	// P_divclksel=3 P_divbitsel=1
+	0x0006,
+	(3 << 10) | (1 << 6),
 
 	1, 905,
-	0x2c8e,			// Tuner IO bank: max drive (14mA) + divout pads max drive
+	0x2c8e,
 
 	0,
 };
···
 		dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
 		dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
 		dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
-		//dib7000p_write_word(state, 273, (1<<6) | 10); /* P_vit_inoise_sel = 1, P_vit_inoise_gain = 10*/
-		dib7000p_write_word(state, 273, (1<<6) | 30); //26/* P_vit_inoise_sel = 1, P_vit_inoise_gain = 26*/// FAG
+		dib7000p_write_word(state, 273, (1<<6) | 30);
 	}
 	if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
 		dprintk("OUTPUT_MODE could not be reset.");
···
 
 	dib7000p_set_bandwidth(state, 8000);
 
-	if(state->version == SOC7090) {
+	if (state->version == SOC7090) {
 		dib7000p_write_word(state, 36, 0x5755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
-	} else { // P_iqc_alpha_pha, P_iqc_alpha_amp_dcc_alpha, ...
+	} else {
 		if (state->cfg.tuner_is_baseband)
 			dib7000p_write_word(state, 36, 0x0755);
 		else
···
 {
 	u16 tmp = 0;
 	tmp = dib7000p_read_word(state, 903);
-	dib7000p_write_word(state, 903, (tmp | 0x1));	//pwr-up pll
+	dib7000p_write_word(state, 903, (tmp | 0x1));
 	tmp = dib7000p_read_word(state, 900);
-	dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));	//use High freq clock
+	dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
 }
 
 static void dib7000p_restart_agc(struct dib7000p_state *state)
···
 {
 	u16 dyn_gain;
 
-	// when there is no LNA to program return immediatly
 	if (state->cfg.update_lna) {
-		// read dyn_gain here (because it is demod-dependent and not fe)
 		dyn_gain = dib7000p_read_word(state, 394);
-		if (state->cfg.update_lna(&state->demod, dyn_gain)) {	// LNA has changed
+		if (state->cfg.update_lna(&state->demod, dyn_gain)) {
 			dib7000p_restart_agc(state);
 			return 1;
 		}
···
 
 	switch (state->agc_state) {
 	case 0:
-		// set power-up level: interf+analog+AGC
 		dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
 		if (state->version == SOC7090) {
 			reg = dib7000p_read_word(state, 0x79b) & 0xff00;
 			dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF);	/* lsb */
-			dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));	// bit 14 = enDemodGain
+			dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
 
 			/* enable adc i & q */
 			reg = dib7000p_read_word(state, 0x780);
···
 		break;
 
 	case 1:
-		// AGC initialization
 		if (state->cfg.agc_control)
 			state->cfg.agc_control(&state->demod, 1);
 
···
 		break;
 
 	case 4:		/* LNA startup */
-		// wait AGC accurate lock time
 		ret = 7;
 
 		if (dib7000p_update_lna(state))
-			// wait only AGC rough lock time
 			ret = 5;
-		else		// nothing was done, go to the next state
+		else
 			(*agc_state)++;
 		break;
 
···
 	dib7000p_write_word(state, 208, value);
 
 	/* offset loop parameters */
-	dib7000p_write_word(state, 26, 0x6680);	// timf(6xxx)
-	dib7000p_write_word(state, 32, 0x0003);	// pha_off_max(xxx3)
-	dib7000p_write_word(state, 29, 0x1273);	// isi
-	dib7000p_write_word(state, 33, 0x0005);	// sfreq(xxx5)
+	dib7000p_write_word(state, 26, 0x6680);
+	dib7000p_write_word(state, 32, 0x0003);
+	dib7000p_write_word(state, 29, 0x1273);
+	dib7000p_write_word(state, 33, 0x0005);
 
 	/* P_dvsy_sync_wait */
 	switch (ch->u.ofdm.transmission_mode) {
···
 		break;
 	}
 	if (state->cfg.diversity_delay == 0)
-		state->div_sync_wait = (value * 3) / 2 + 48;	// add 50% SFN margin + compensate for one DVSY-fifo
+		state->div_sync_wait = (value * 3) / 2 + 48;
 	else
-		state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;	// add 50% SFN margin + compensate for one DVSY-fifo
+		state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
 
 	/* deactive the possibility of diversity reception if extended interleaver */
 	state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K;
···
 	else
 		factor = 6;
 
-	// always use the setting for 8MHz here lock_time for 7,6 MHz are longer
 	value = 30 * internal * factor;
-	dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));	// lock0 wait time
-	dib7000p_write_word(state, 7, (u16) (value & 0xffff));	// lock0 wait time
+	dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
+	dib7000p_write_word(state, 7, (u16) (value & 0xffff));
 	value = 100 * internal * factor;
-	dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));	// lock1 wait time
-	dib7000p_write_word(state, 9, (u16) (value & 0xffff));	// lock1 wait time
+	dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
+	dib7000p_write_word(state, 9, (u16) (value & 0xffff));
 	value = 500 * internal * factor;
-	dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));	// lock2 wait time
-	dib7000p_write_word(state, 11, (u16) (value & 0xffff));	// lock2 wait time
+	dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
+	dib7000p_write_word(state, 11, (u16) (value & 0xffff));
 
 	value = dib7000p_read_word(state, 0);
 	dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
···
 	struct dib7000p_state *state = demod->demodulator_priv;
 	u16 irq_pending = dib7000p_read_word(state, 1284);
 
-	if (irq_pending & 0x1)	// failed
+	if (irq_pending & 0x1)
 		return 1;
 
-	if (irq_pending & 0x2)	// succeeded
+	if (irq_pending & 0x2)
 		return 2;
 
-	return 0;		// still pending
+	return 0;
 }
 
 static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
···
 	if (state->sfn_workaround_active) {
 		dprintk("SFN workaround is active");
 		tmp |= (1 << 9);
-		dib7000p_write_word(state, 166, 0x4000);	// P_pha3_force_pha_shift
+		dib7000p_write_word(state, 166, 0x4000);
 	} else {
-		dib7000p_write_word(state, 166, 0x0000);	// P_pha3_force_pha_shift
+		dib7000p_write_word(state, 166, 0x0000);
 	}
 	dib7000p_write_word(state, 29, tmp);
 
···
 	if (state->version == SOC7090) {
 		dib7090_set_diversity_in(fe, 0);
 		dib7090_set_output_mode(fe, OUTMODE_HIGH_Z);
-	}
-	else
+	} else
 		dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
 
 	/* maybe the parameter has been changed */
···
 
 		dprintk("autosearch returns: %d", found);
 		if (found == 0 || found == 1)
-			return 0;	// no channel found
+			return 0;
 
 		dib7000p_get_frontend(fe, fep);
 	}
···
 {
 	u8 tx[2], rx[2];
 	struct i2c_msg msg[2] = {
-		{.addr = 18 >> 1,.flags = 0,.buf = tx,.len = 2},
-		{.addr = 18 >> 1,.flags = I2C_M_RD,.buf = rx,.len = 2},
+		{.addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2},
+		{.addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2},
 	};
 
 	tx[0] = 0x03;
···
 		msg->buf[0] -= 3;
 	else if (msg->buf[0] == 28)
 		msg->buf[0] = 23;
-	else {
+	else
 		return -EINVAL;
-	}
 	return 0;
 }
 
···
 		if (num == 1) {	/* write */
 			word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
 			word &= 0x3;
-			word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);	//Mask bit 12,13
+			word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
 			dib7000p_write_word(state, 72, word);	/* Set the proper input */
 			return num;
 		}
···
 	u16 rx_copy_buf[22];
 
 	dprintk("Configure DibStream Tx");
-	for (index_buf = 0; index_buf<22; index_buf++)
+	for (index_buf = 0; index_buf < 22; index_buf++)
 		rx_copy_buf[index_buf] = dib7000p_read_word(state, 1536+index_buf);
 
 	dib7000p_write_word(state, 1615, 1);
···
 	dib7000p_write_word(state, 1612, syncSize);
 	dib7000p_write_word(state, 1615, 0);
 
-	for (index_buf = 0; index_buf<22; index_buf++)
+	for (index_buf = 0; index_buf < 22; index_buf++)
 		dib7000p_write_word(state, 1536+index_buf, rx_copy_buf[index_buf]);
 
 	return 0;
···
 	u32 syncFreq;
 
 	dprintk("Configure DibStream Rx");
-	if ((P_Kin != 0) && (P_Kout != 0))
-	{
+	if ((P_Kin != 0) && (P_Kout != 0)) {
 		syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
 		dib7000p_write_word(state, 1542, syncFreq);
 	}
···
 	u16 reg;
 
 	dprintk("Enable Diversity on host bus");
-	reg = (1 << 8) | (1 << 5);	// P_enDivOutOnDibTx = 1 ; P_enDibTxOnHostBus = 1
+	reg = (1 << 8) | (1 << 5);
 	dib7000p_write_word(state, 1288, reg);
 
 	return dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
···
 	u16 reg;
 
 	dprintk("Enable ADC on host bus");
-	reg = (1 << 7) | (1 << 5);	//P_enAdcOnDibTx = 1 ; P_enDibTxOnHostBus = 1
+	reg = (1 << 7) | (1 << 5);
 	dib7000p_write_word(state, 1288, reg);
 
 	return dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
···
 	u16 reg;
 
 	dprintk("Enable Mpeg on host bus");
-	reg = (1 << 9) | (1 << 5);	//P_enMpegOnDibTx = 1 ; P_enDibTxOnHostBus = 1
+	reg = (1 << 9) | (1 << 5);
 	dib7000p_write_word(state, 1288, reg);
 
 	return dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
···
 	dprintk("Enable Mpeg mux");
 	dib7000p_write_word(state, 1287, reg);
 
-	reg &= ~(1 << 7);	// P_restart_mpegMux = 0
+	reg &= ~(1 << 7);
 	dib7000p_write_word(state, 1287, reg);
 
-	reg = (1 << 4);		//P_enMpegMuxOnHostBus = 1
+	reg = (1 << 4);
 	dib7000p_write_word(state, 1288, reg);
 
 	return 0;
···
 	u16 reg;
 
 	dprintk("Disable Mpeg mux");
-	dib7000p_write_word(state, 1288, 0);	//P_enMpegMuxOnHostBus = 0
+	dib7000p_write_word(state, 1288, 0);
 
 	reg = dib7000p_read_word(state, 1287);
-	reg &= ~(1 << 7);	// P_restart_mpegMux = 0
+	reg &= ~(1 << 7);
 	dib7000p_write_word(state, 1287, reg);
 
 	return 0;
···
 {
 	struct dib7000p_state *state = fe->demodulator_priv;
 
-	switch(mode) {
-		case INPUT_MODE_DIVERSITY:
+	switch (mode) {
+	case INPUT_MODE_DIVERSITY:
 			dprintk("Enable diversity INPUT");
-			dib7090_cfg_DibRx(state, 5,5,0,0,0,0,0);
+			dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
 			break;
-		case INPUT_MODE_MPEG:
+	case INPUT_MODE_MPEG:
 			dprintk("Enable Mpeg INPUT");
-			dib7090_cfg_DibRx(state, 8,5,0,0,0,8,0); /*outputRate = 8 */
+			dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
 			break;
-		case INPUT_MODE_OFF:
-		default:
+	case INPUT_MODE_OFF:
+	default:
 			dprintk("Disable INPUT");
-			dib7090_cfg_DibRx(state, 0,0,0,0,0,0,0);
+			dib7090_cfg_DibRx(state, 0, 0, 0, 0, 0, 0, 0);
 			break;
 	}
 	return 0;
···
 		} else {	/* Use Smooth block */
 			dprintk("Sip 7090P setting output mode TS_SERIAL using Smooth bloc");
 			dib7090_disableMpegMux(state);
-			dib7000p_write_word(state, 1288, (1 << 6));	//P_enDemOutInterfOnHostBus = 1
+			dib7000p_write_word(state, 1288, (1 << 6));
 			outreg |= (2 << 6) | (0 << 1);
 		}
 		break;
···
 		} else {	/* Use Smooth block */
 			dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Smooth block");
 			dib7090_disableMpegMux(state);
-			dib7000p_write_word(state, 1288, (1 << 6));	//P_enDemOutInterfOnHostBus = 1
+			dib7000p_write_word(state, 1288, (1 << 6));
 			outreg |= (0 << 6);
 		}
 		break;
···
 	case OUTMODE_MPEG2_PAR_CONT_CLK:	/* Using Smooth block only */
 		dprintk("Sip 7090P setting output mode TS_PARALLEL_CONT using Smooth block");
 		dib7090_disableMpegMux(state);
-		dib7000p_write_word(state, 1288, (1 << 6));	//P_enDemOutInterfOnHostBus = 1
+		dib7000p_write_word(state, 1288, (1 << 6));
 		outreg |= (1 << 6);
 		break;
 
 	case OUTMODE_MPEG2_FIFO:	/* Using Smooth block because not supported by new Mpeg Mux bloc */
 		dprintk("Sip 7090P setting output mode TS_FIFO using Smooth block");
 		dib7090_disableMpegMux(state);
-		dib7000p_write_word(state, 1288, (1 << 6));	//P_enDemOutInterfOnHostBus = 1
+		dib7000p_write_word(state, 1288, (1 << 6));
 		outreg |= (5 << 6);
 		smo_mode |= (3 << 1);
 		fifo_threshold = 512;
···
 
 	en_cur_state = dib7000p_read_word(state, 1922);
 
-	if (en_cur_state > 0xff) {	//LNAs and MIX are ON and therefore it is a valid configuration
+	if (en_cur_state > 0xff)
 		state->tuner_enable = en_cur_state;
-	}
 
 	if (onoff)
-		en_cur_state &= 0x00ff;	//Mask to be applied
+		en_cur_state &= 0x00ff;
 	else {
 		if (state->tuner_enable != 0)
 			en_cur_state = state->tuner_enable;
···
 int dib7090_slave_reset(struct dvb_frontend *fe)
 {
 	struct dib7000p_state *state = fe->demodulator_priv;
-    u16 reg;
+	u16 reg;
 
-    reg = dib7000p_read_word(state, 1794);
-    dib7000p_write_word(state, 1794, reg | (4 << 12));
+	reg = dib7000p_read_word(state, 1794);
+	dib7000p_write_word(state, 1794, reg | (4 << 12));
 
-    dib7000p_write_word(state, 1032, 0xffff);
-    return 0;
+	dib7000p_write_word(state, 1032, 0xffff);
+	return 0;
 }
 EXPORT_SYMBOL(dib7090_slave_reset);
 
···
 
 	return demod;
 
- error:
+error:
 	kfree(st);
 	return NULL;
 }

drivers/media/dvb/frontends/dib7000p.h

···
 	u16 diversity_delay;
 
 	u8 default_i2c_addr;
-	u8 enMpegOutput : 1;
+	u8 enMpegOutput:1;
 };
 
 #define DEFAULT_DIB7000P_I2C_ADDRESS 18

drivers/media/dvb/frontends/dib8000.c

···
 	fifo_threshold = 1792;
 	smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
 
-	dprintk("-I-	Setting output mode for demod %p to %d", &state->fe[0], mode);
+	dprintk("-I-	Setting output mode for demod %p to %d",
+			&state->fe[0], mode);
 
 	switch (mode) {
 	case OUTMODE_MPEG2_PAR_GATED_CLK:	// STBs with parallel gated clock
···
 		break;
 
 	default:
-		dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]);
+		dprintk("Unhandled output_mode passed to be set for demod %p",
+				&state->fe[0]);
 		return -EINVAL;
 	}
 
···
 {
 	/* by default everything is going to be powered off */
 	u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
-		reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
+		reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
+		reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
 
 	/* now, depending on the requested mode, we power on */
 	switch (mode) {
···
 
 	// clk_cfg1
 	clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
-		(pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | (pll->pll_range << 1) | (pll->pll_reset << 0);
+		(pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) |
+		(pll->pll_range << 1) | (pll->pll_reset << 0);
 
 	dib8000_write_word(state, 902, clk_cfg1);
 	clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
···
 
 	/* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
 	if (state->cfg.pll->ADClkSrc == 0)
-		dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
+		dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) |
+				(pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
 	else if (state->cfg.refclksel != 0)
-		dib8000_write_word(state, 904,
-					(0 << 15) | (1 << 12) | ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) | (pll->
-															ADClkSrc << 7) | (0 << 1));
+		dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
+				((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) |
+				(pll->ADClkSrc << 7) | (0 << 1));
 	else
 		dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
 
···
 	1, 285,
 	0x0020,			//p_fec_
 	1, 299,
-	0x0062,			// P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
+	0x0062,			/* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
 
 	1, 338,
 	(1 << 12) |		// P_ctrl_corm_thres4pre_freq_inh=1
-		(1 << 10) |		// P_ctrl_pre_freq_mode_sat=1
-		(0 << 9) |		// P_ctrl_pre_freq_inh=0
-		(3 << 5) |		// P_ctrl_pre_freq_step=3
-		(1 << 0),		// P_pre_freq_win_len=1
+		(1 << 10) |
+		(0 << 9) |		/* P_ctrl_pre_freq_inh=0 */
+		(3 << 5) |		/* P_ctrl_pre_freq_step=3 */
+		(1 << 0),		/* P_pre_freq_win_len=1 */
 
 	1, 903,
 	(0 << 4) | 2,		// P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW)
···
 		// read dyn_gain here (because it is demod-dependent and not tuner)
 		dyn_gain = dib8000_read_word(state, 390);
 
-		if (state->cfg.update_lna(state->fe[0], dyn_gain)) {	// LNA has changed
+		if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
 			dib8000_restart_agc(state);
 			return 1;
 		}
···
 		split_offset = state->current_agc->split.max;
 	else
 		split_offset = state->current_agc->split.max *
-			(agc - state->current_agc->split.min_thres) / (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
+			(agc - state->current_agc->split.min_thres) /
+			(state->current_agc->split.max_thres - state->current_agc->split.min_thres);
 
 	dprintk("AGC split_offset: %d", split_offset);
 
···
 	s32 val;
 
 	val = dib8000_read32(state, 384);
-	/* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */
 	if (mode) {
 		tmp_val = val;
 		while (tmp_val >>= 1)
 			exp++;
 		mant = (val * 1000 / (1<<exp));
 		ix = (u8)((mant-1000)/100); /* index of the LUT */
-		val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */
+		val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
 		val = (val*256)/1000;
 	}
 	return val;
···
 		dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
 
 	i = dib8000_read_word(state, 26) & 1;	// P_dds_invspec
-	dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion ^ i);
+	dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion^i);
 
 	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
 		//compute new dds_freq for the seg and adjust prbs
 		int seg_offset =
-			state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx - (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) -
+			state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx -
+			(state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) -
 			(state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2);
 		int clk = state->cfg.pll->internal;
 		u32 segtodds = ((u32) (430 << 23) / clk) << 3;	// segtodds = SegBW / Fclk * pow(2,26)
 		int dds_offset = seg_offset * segtodds;
 		int new_dds, sub_channel;
-		if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)	// if even
+		if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
 			dds_offset -= (int)(segtodds / 2);
 
 		if (state->cfg.pll->ifreq == 0) {
···
 			//  - the segment of center frequency with an odd total number of segments
 			//  - the segment to the left of center frequency with an even total number of segments
 			//  - the segment to the right of center frequency with an even total number of segments
-			if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT) && (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
+			if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT)
+				&& (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
 					&& (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
 					  && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
 				  ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
···
 		}
 		dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff));
 		dib8000_write_word(state, 28, (u16) (new_dds & 0xffff));
-		if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)	// if odd
+		if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
 			sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3;
-		else		// if even
+		else
 			sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3;
 		sub_channel -= 6;
 
···
 			}
 			break;
 		}
-	} else {		// if not state->fe[0]->dtv_property_cache.isdbt_sb_mode
+	} else {
 		dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff));
 		dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff));
 		dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003));
···
 	state->differential_constellation = (seg_diff_mask != 0);
 	dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
 
-	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {	// ISDB-Tsb
-		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)	// 3-segments
+	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
+		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
 			seg_mask13 = 0x00E0;
 		else		// 1-segment
 			seg_mask13 = 0x0040;
···
 	dib8000_write_word(state, 353, seg_mask13);	// ADDR 353
 
 /*	// P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */
-	// dib8000_write_word(state, 351, (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5 );
 
 	// ---- SMALL ----
 	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
 		switch (state->fe[0]->dtv_property_cache.transmission_mode) {
 		case TRANSMISSION_MODE_2K:
-			if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {	// 1-seg
-				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)	// DQPSK
+			if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
+				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
 					ncoeff = coeff_2k_sb_1seg_dqpsk;
 				else	// QPSK or QAM
 					ncoeff = coeff_2k_sb_1seg;
 			} else {	// 3-segments
-				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {	// DQPSK on central segment
-					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)	// DQPSK on external segments
+				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
+					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
 						ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
 					else	// QPSK or QAM on external segments
 						ncoeff = coeff_2k_sb_3seg_0dqpsk;
 				} else {	// QPSK or QAM on central segment
-					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)	// DQPSK on external segments
+					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
 						ncoeff = coeff_2k_sb_3seg_1dqpsk;
 					else	// QPSK or QAM on external segments
 						ncoeff = coeff_2k_sb_3seg;
···
 			break;
 
 		case TRANSMISSION_MODE_4K:
-			if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {	// 1-seg
-				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)	// DQPSK
+			if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
+				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
 					ncoeff = coeff_4k_sb_1seg_dqpsk;
 				else	// QPSK or QAM
 					ncoeff = coeff_4k_sb_1seg;
 			} else {	// 3-segments
-				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {	// DQPSK on central segment
-					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {	// DQPSK on external segments
+				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
+					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
 						ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
 					} else {	// QPSK or QAM on external segments
 						ncoeff = coeff_4k_sb_3seg_0dqpsk;
 					}
 				} else {	// QPSK or QAM on central segment
-					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {	// DQPSK on external segments
+					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
 						ncoeff = coeff_4k_sb_3seg_1dqpsk;
 					} else	// QPSK or QAM on external segments
 						ncoeff = coeff_4k_sb_3seg;
···
 		case TRANSMISSION_MODE_AUTO:
 		case TRANSMISSION_MODE_8K:
 		default:
-			if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {	// 1-seg
-				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)	// DQPSK
+			if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
+				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
 					ncoeff = coeff_8k_sb_1seg_dqpsk;
 				else	// QPSK or QAM
 					ncoeff = coeff_8k_sb_1seg;
 			} else {	// 3-segments
-				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {	// DQPSK on central segment
-					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {	// DQPSK on external segments
+				if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
+					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
 						ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
 					} else {	// QPSK or QAM on external segments
 						ncoeff = coeff_8k_sb_3seg_0dqpsk;
 					}
 				} else {	// QPSK or QAM on central segment
-					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {	// DQPSK on external segments
+					if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
 						ncoeff = coeff_8k_sb_3seg_1dqpsk;
 					} else	// QPSK or QAM on external segments
 						ncoeff = coeff_8k_sb_3seg;
···
 
 	// ---- COFF ----
 	// Carloff, the most robust
-	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {	// Sound Broadcasting mode - use both TMCC and AC pilots
+	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
 
 		// P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64
 		// P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1
···
 /*		// P_small_coef_ext_enable = 1 */
 /*		dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */
 
-		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {	// Sound Broadcasting mode 1 seg
+		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
 
 			// P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1)
 			if (mode == 3)
···
 		dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
 	}
 	// ---- FFT ----
-	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)	// 1-seg
+	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
 		dib8000_write_word(state, 178, 64);	// P_fft_powrange=64
 	else
 		dib8000_write_word(state, 178, 32);	// P_fft_powrange=32
···
 
 	/* offset loop parameters */
 	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
-		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)	// Sound Broadcasting mode 1 seg
+		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
 			/* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
 			dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40);
 
···
 		dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80);
 
 	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
-		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)	// Sound Broadcasting mode 1 seg
+		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
 			/* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P_ctrl_sfreq_step = (11-P_mode)  */
 			dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode));
 
···
 
 	// ---- ANA_FE ----
 	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
-		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)	// 3-segments
+		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
 			ana_fe = ana_fe_coeff_3seg;
 		else		// 1-segment
 			ana_fe = ana_fe_coeff_1seg;
···
 	// "P_cspu_left_edge"  not used => do not care
 	// "P_cspu_right_edge" not used => do not care
 
-	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {	// ISDB-Tsb
+	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
 		dib8000_write_word(state, 228, 1);	// P_2d_mode_byp=1
 		dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0);	// P_cspu_win_cut = 0
-		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0	// 1-segment
+		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0
 			&& state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) {
 			//dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0
 			dib8000_write_word(state, 265, 15);	// P_equal_noise_sel = 15
···
 	// never achieved a lock before - wait for timfreq to update
 	if (state->timf == 0) {
 		if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
-			if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)	// Sound Broadcasting mode 1 seg
+			if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
 				msleep(300);
 			else	// Sound Broadcasting mode 3 seg
 				msleep(500);
···
 			msleep(200);
 	}
 	if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
-		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {	// Sound Broadcasting mode 1 seg
+		if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
 
 			/* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40  alpha to check on board */
 			dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40);
···
 	if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
 		dprintk("could not start Slow ADC");
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
-		if (ret<0)
+		if (ret < 0)
 			return ret;
 	}
 
···
 	u8 index_frontend;
 	int ret;
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
 		if (ret < 0)
 			return ret;
···
 
 	fe->dtv_property_cache.bandwidth_hz = 6000000;
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
 		if (stat&FE_HAS_SYNC) {
 			dprintk("TMCC lock on the slave%i", index_frontend);
 			/* synchronize the cache with the other frontends */
 			state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
-			for (sub_index_frontend=0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
+			for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
 				if (sub_index_frontend != index_frontend) {
 					state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
 					state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
···
 	}
 
 	/* synchronize the cache with the other frontends */
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode;
 		state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
 		state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
···
 		state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000;
 	}
 
-	for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		/* synchronization of the cache */
 		state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
 		memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
···
 	/* start up the AGC */
 	do {
 		time = dib8000_agc_startup(state->fe[0]);
-		for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+		for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 			time_slave = dib8000_agc_startup(state->fe[index_frontend]);
 			if (time == FE_CALLBACK_TIME_NEVER)
 				time = time_slave;
···
 		else
 			break;
 		exit_condition = 1;
-		for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+		for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 			if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
 				exit_condition = 0;
 				break;
···
 		}
 	} while (exit_condition == 0);
 
-	for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+	for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
 		dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
 
 	if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) ||
···
 				 u8 found = 0;
 				 u8 tune_failed = 0;
 
-				 for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+				 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 					 dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000);
 					 dib8000_autosearch_start(state->fe[index_frontend]);
 				 }
 
 				 do {
-					 msleep(10);
+					 msleep(20);
 					 nbr_pending = 0;
 					 exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
-					 for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+					 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 						 if (((tune_failed >> index_frontend) & 0x1) == 0) {
 							 found = dib8000_autosearch_irq(state->fe[index_frontend]);
 							 switch (found) {
-								 case 0: /* tune pending */
+							 case 0: /* tune pending */
 									 nbr_pending++;
 									 break;
-								 case 2:
+							 case 2:
 									 dprintk("autosearch succeed on the frontend%i", index_frontend);
 									 exit_condition = 2;
 									 index_frontend_success = index_frontend;
 									 break;
-								 default:
+							 default:
 									 dprintk("unhandled autosearch result");
-								 case 1:
-									 tune_failed |= (1 << index_frontend);
+							 case 1:
 									 dprintk("autosearch failed for the frontend%i", index_frontend);
 									 break;
 							 }
···
 				 dib8000_get_frontend(fe, fep);
 			 }
 
-	for (index_frontend=0, ret=0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
 		ret = dib8000_tune(state->fe[index_frontend]);
-	}
 
 	/* set output mode and diversity input */
 	dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
 		dib8000_set_diversity_in(state->fe[index_frontend-1], 1);
 	}
···
 	return ret;
 }
 
-static u16 dib8000_read_lock(struct dvb_frontend *fe) {
+static u16 dib8000_read_lock(struct dvb_frontend *fe)
+{
 	struct dib8000_state *state = fe->demodulator_priv;
 
 	return dib8000_read_word(state, 568);
···
 	u16 lock_slave = 0, lock = dib8000_read_word(state, 568);
 	u8 index_frontend;
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
 		lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
 
 	*stat = 0;
···
 	u16 val;
 
 	*strength = 0;
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
 		if (val > 65535 - *strength)
 			*strength = 65535;
···
 	u32 snr_master;
 
 	snr_master = dib8000_get_snr(fe);
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
 		snr_master += dib8000_get_snr(state->fe[index_frontend]);
 
 	if (snr_master != 0) {
···
 }
 EXPORT_SYMBOL(dib8000_remove_slave_frontend);
 
-struct dvb_frontend * dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
+struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
 {
 	struct dib8000_state *state = fe->demodulator_priv;
 
···
 	struct dib8000_state *st = fe->demodulator_priv;
 	u8 index_frontend;
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
 		dvb_frontend_detach(st->fe[index_frontend]);
 
 	dibx000_exit_i2c_master(&st->i2c_master);

drivers/media/dvb/frontends/dib8000.h

···
 extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
 extern int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
 extern int dib8000_remove_slave_frontend(struct dvb_frontend *fe);
-extern struct dvb_frontend * dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
+extern struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
 #else
 static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
 {
···
 	return -ENODEV;
 }
 
-static inline struct dvb_frontend * dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index) {
+static inline struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
+{
 	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-    return NULL;
+	return NULL;
 }
 #endif
 

drivers/media/dvb/frontends/dib9000.c

···
 
 /* lock */
 #define DIB_LOCK struct mutex
-#define DibAcquireLock(lock) do { if (mutex_lock_interruptible(lock)<0) dprintk("could not get the lock"); } while (0)
+#define DibAcquireLock(lock) do { if (mutex_lock_interruptible(lock) < 0) dprintk("could not get the lock"); } while (0)
 #define DibReleaseLock(lock) mutex_unlock(lock)
 #define DibInitLock(lock) mutex_init(lock)
 #define DibFreeLock(lock)
···
 
 #define FE_MM_W_COMPONENT_ACCESS         16
 #define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
-static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen,
-					u8 * b, u32 len);
+static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
 static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
 
 static u16 to_fw_output_mode(u16 mode)
···
 	int ret;
 	u8 wb[2] = { reg >> 8, reg & 0xff };
 	struct i2c_msg msg[2] = {
-		{.addr = state->i2c.i2c_addr >> 1,.flags = 0,.buf = wb,.len = 2},
-		{.addr = state->i2c.i2c_addr >> 1,.flags = I2C_M_RD,.buf = b,.len = len},
+		{.addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
+		{.addr = state->i2c.i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = len},
 	};
 
 	if (state->platform.risc.fw_is_running && (reg < 1024))
···
 	u8 b[2];
 	u8 wb[2] = { reg >> 8, reg & 0xff };
 	struct i2c_msg msg[2] = {
-		{.addr = i2c->i2c_addr >> 1,.flags = 0,.buf = wb,.len = 2},
-		{.addr = i2c->i2c_addr >> 1,.flags = I2C_M_RD,.buf = b,.len = 2},
+		{.addr = i2c->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
+		{.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = 2},
 	};
 
 	if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
···
 	int ret;
 
 	struct i2c_msg msg = {
-		.addr = state->i2c.i2c_addr >> 1,.flags = 0,.buf = b,.len = len + 2
+		.addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = b, .len = len + 2
 	};
 
 	if (state->platform.risc.fw_is_running && (reg < 1024)) {
 		if (dib9000_risc_apb_access_write
-				(state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
+		    (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
 			return -EINVAL;
 		return 0;
 	}
···
 {
 	u8 b[4] = { (reg >> 8) & 0xff, reg & 0xff, (val >> 8) & 0xff, val & 0xff };
 	struct i2c_msg msg = {
-		.addr = i2c->i2c_addr >> 1,.flags = 0,.buf = b,.len = 4
+		.addr = i2c->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
 	};
 
 	return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
···
 {
 	u8 b[14] = { 0 };
 
-//	dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len);
-//	b[0] = 0 << 7;
+/*      dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */
+/*      b[0] = 0 << 7; */
 	b[1] = 1;
 
-//	b[2] = 0; // 1057
-//	b[3] = 0;
-	b[4] = (u8) (addr >> 8);	// 1058
+/*      b[2] = 0; */
+/*      b[3] = 0; */
+	b[4] = (u8) (addr >> 8);
 	b[5] = (u8) (addr & 0xff);
 
-//	b[10] = 0;        // 1061
-//	b[11] = 0;
-	b[12] = (u8) (addr >> 8);	// 1062
+/*      b[10] = 0; */
+/*      b[11] = 0; */
+	b[12] = (u8) (addr >> 8);
 	b[13] = (u8) (addr & 0xff);
 
 	addr += len;
-//	b[6] = 0;      // 1059
-//	b[7] = 0;
-	b[8] = (u8) (addr >> 8);	// 1060
+/*      b[6] = 0; */
+/*      b[7] = 0; */
+	b[8] = (u8) (addr >> 8);
 	b[9] = (u8) (addr & 0xff);
 
 	dib9000_write(state, 1056, b, 14);
···
 	struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
 	/* decide whether we need to "refresh" the memory controller */
 	if (state->platform.risc.memcmd == cmd &&	/* same command */
-			!(cmd & 0x80 && m->size < 67))	/* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
+	    !(cmd & 0x80 && m->size < 67))	/* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
 		return;
 	dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
 	state->platform.risc.memcmd = cmd;
···
 			break;
 	} while (1);
 
-	//dprintk( "MBX: size: %d", size);
+	/*dprintk( "MBX: size: %d", size); */
 
 	if (tmp == 0) {
 		ret = -EINVAL;
···
 	/* update register nb_mes_in_RX */
 	ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
 
- out:
+out:
 	DibReleaseLock(&state->platform.risc.mbx_if_lock);
 
 	return ret;
···
 		if (*block == 0) {
 			size = dib9000_mbx_read(state, block, 1, attr);
 
-//			dprintk( "MBX: fetched %04x message to cache", *block);
+/*                      dprintk( "MBX: fetched %04x message to cache", *block); */
 
 			switch (*block >> 8) {
 			case IN_MSG_DEBUG_BUF:
···
 		ret = dib9000_mbx_fetch_to_cache(state, attr);
 
 	tmp = dib9000_read_word_attr(state, 1229, attr);	/* Clear the IRQ */
-//	if (tmp)
-//		dprintk( "cleared IRQ: %x", tmp);
+/*      if (tmp) */
+/*              dprintk( "cleared IRQ: %x", tmp); */
 	DibReleaseLock(&state->platform.risc.mbx_lock);
 
 	return ret;
···
 {
 	u16 value;
 
-	if ((value = dib9000_i2c_read16(client, 896)) != 0x01b3) {
+	value = dib9000_i2c_read16(client, 896);
+	if (value != 0x01b3) {
 		dprintk("wrong Vendor ID (0x%x)", value);
 		return 0;
 	}
···
 {
 	struct dib9000_state *state = fe->demodulator_priv;
 
-	dib9000_write_word(state, 1817, 0x0003);	// SRAM read lead in + P_host_rdy_cmos=1
+	dib9000_write_word(state, 1817, 0x0003);
 
 	dib9000_write_word(state, 1227, 1);
 	dib9000_write_word(state, 1227, 0);
···
 	return 0;
 }
 
-static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen,
-					u8 * b, u32 len)
+static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len)
 {
 	u16 mb[10];
 	u8 i, s;
···
 	if (address >= 1024 || !state->platform.risc.fw_is_running)
 		return -EINVAL;
 
-	//dprintk( "APB access thru rd fw %d %x", address, attribute);
+	/* dprintk( "APB access thru rd fw %d %x", address, attribute); */
 
 	mb[0] = (u16) address;
 	mb[1] = len / 2;
 	dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
 	switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
 	case 1:
-		s--;		// address
+		s--;
 		for (i = 0; i < s; i++) {
 			b[i * 2] = (mb[i + 1] >> 8) & 0xff;
 			b[i * 2 + 1] = (mb[i + 1]) & 0xff;
···
 	if (address >= 1024 || !state->platform.risc.fw_is_running)
 		return -EINVAL;
 
-	//dprintk( "APB access thru wr fw %d %x", address, attribute);
+	/* dprintk( "APB access thru wr fw %d %x", address, attribute); */
 
 	mb[0] = (unsigned short)address;
-	for (i = 0; i < len && i < 20; i += 2)	// 20 bytes max
+	for (i = 0; i < len && i < 20; i += 2)
 		mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]);
 
 	dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute);
···
 	u8 size;
 
 	if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
-		//if (dib9000_fw_boot(state, microcode_A_buffer, microcode_A_size, microcode_B_buffer, microcode_B_size) != 0)
 		return -EIO;
 
 	/* initialize the firmware */
···
 		b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
 		b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
 		b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
-		//dprintk( "SBS: %d %d %x %x %x\n", i, b[1 + i*4], b[2 + i*4], b[3 + i*4], b[4 + i*4]);
 	}
 	b[1 + i * 4] = 0;	/* fe_id */
 	if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
···
 	/* 0 - id, 1 - no_of_frontends */
 	b[0] = (0 << 8) | 1;
 	/* 0 = i2c-address demod, 0 = tuner */
-	b[1] = (0 << 8) | (0);	//st->i2c_addr ) );
+	b[1] = (0 << 8) | (0);
 	b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
 	b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
 	b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
···
 		return -EIO;
 
 	if (size > ARRAY_SIZE(b)) {
-		dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size, (int)ARRAY_SIZE(b));
+		dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size,
+			(int)ARRAY_SIZE(b));
 		return -EINVAL;
 	}
 
 	for (i = 0; i < size; i += 2) {
 		state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
 		state->platform.risc.fe_mm[i / 2].size = b[i + 1];
-		//dprintk( "MM: %d %d %d", state->platform.risc.fe_mm[i/2].addr, state->platform.risc.fe_mm[i/2].size, ARRAY_SIZE(state->platform.risc.fe_mm));
 	}
 
 	return 0;
···
 		ret = -EIO;
 	}
 
-	dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) & ch, sizeof(struct dibDVBTChannel));
+	dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) &ch, sizeof(struct dibDVBTChannel));
 
-	switch (ch.spectrum_inversion&0x7) {
+	switch (ch.spectrum_inversion & 0x7) {
 	case 1:
 		state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
 		break;
···
 		break;
 	}
 
- error:
+error:
 	DibReleaseLock(&state->platform.risc.mem_mbx_lock);
 	return ret;
 }
···
 	ch.select_hp = 1;
 	ch.intlv_native = 1;
 
-	dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) & ch);
+	dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch);
 
 	return 0;
 }
···
 		break;
 	case CT_DEMOD_STEP_1:
 		if (search)
-			dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) & i, 1);
+			dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) &i, 1);
 		else
-			dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) & i, 1);
+			dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) &i, 1);
 		switch (i) {	/* something happened */
 		case 0:
 			break;
···
 	dprintk("setting output mode for demod %p to %d", fe, mode);
 
 	switch (mode) {
-	case OUTMODE_MPEG2_PAR_GATED_CLK:	// STBs with parallel gated clock
+	case OUTMODE_MPEG2_PAR_GATED_CLK:
 		outreg = (1 << 10);	/* 0x0400 */
 		break;
-	case OUTMODE_MPEG2_PAR_CONT_CLK:	// STBs with parallel continues clock
+	case OUTMODE_MPEG2_PAR_CONT_CLK:
 		outreg = (1 << 10) | (1 << 6);	/* 0x0440 */
 		break;
-	case OUTMODE_MPEG2_SERIAL:	// STBs with serial input
+	case OUTMODE_MPEG2_SERIAL:
 		outreg = (1 << 10) | (2 << 6) | (0 << 1);	/* 0x0482 */
 		break;
 	case OUTMODE_DIVERSITY:
 		outreg = (1 << 10) | (4 << 6);	/* 0x0500 */
 		break;
-	case OUTMODE_MPEG2_FIFO:	// e.g. USB feeding
+	case OUTMODE_MPEG2_FIFO:
 		outreg = (1 << 10) | (5 << 6);
 		break;
-	case OUTMODE_HIGH_Z:	// disable
+	case OUTMODE_HIGH_Z:
 		outreg = 0;
 		break;
 	default:
···
 		return -EINVAL;
 	}
 
-	dib9000_write_word(state, 1795, outreg);	// has to be written from outside
+	dib9000_write_word(state, 1795, outreg);
 
 	switch (mode) {
 	case OUTMODE_MPEG2_PAR_GATED_CLK:
···
 static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
 {
 	struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
-	u8 type = 0;	/* I2C */
+	u8 type = 0;		/* I2C */
 	u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
-	u16 scl = state->component_bus_speed; /* SCL frequency */
-	//u16 scl = 208; /* SCL frequency */
+	u16 scl = state->component_bus_speed;	/* SCL frequency */
 	struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
 	u8 p[13] = { 0 };
 
···
 	p[3] = (u8) scl & 0xff;	/* scl */
 	p[4] = (u8) (scl >> 8);
 
-//	p[5] = 0; /* attr */
-//	p[6] = 0;
-
-//	p[7] = (u8) (msg[0].addr << 1 );
-//	p[8] = (u8) (msg[0].addr >> 7 );
 	p[7] = 0;
 	p[8] = 0;
 
···
 	struct dib9000_state *st = fe->demodulator_priv;
 	return &st->tuner_adap;
 }
-
 EXPORT_SYMBOL(dib9000_get_tuner_interface);
 
 struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
···
 	struct dib9000_state *st = fe->demodulator_priv;
 	return &st->component_bus;
 }
-
 EXPORT_SYMBOL(dib9000_get_component_bus_interface);
 
 struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
···
 	struct dib9000_state *st = fe->demodulator_priv;
 	return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
 }
-
 EXPORT_SYMBOL(dib9000_get_i2c_master);
 
 int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
···
 	st->i2c.i2c_adap = i2c;
 	return 0;
 }
-
 EXPORT_SYMBOL(dib9000_set_i2c_adapter);
 
 static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
···
 	struct dib9000_state *state = fe->demodulator_priv;
 	return dib9000_cfg_gpio(state, num, dir, val);
 }
-
 EXPORT_SYMBOL(dib9000_set_gpio);
+
 int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
 {
 	struct dib9000_state *state = fe->demodulator_priv;
···
 	dprintk("PID filter enabled %d", onoff);
 	return dib9000_write_word(state, 294 + 1, val);
 }
-
 EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
+
 int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
 {
 	struct dib9000_state *state = fe->demodulator_priv;
 	dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
 	return dib9000_write_word(state, 300 + 1 + id, onoff ? (1 << 13) | pid : 0);
 }
-
 EXPORT_SYMBOL(dib9000_fw_pid_filter);
 
 int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
···
 	struct dib9000_state *state = fe->demodulator_priv;
 	return dib9000_fw_init(state);
 }
-
 EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
 
 static void dib9000_release(struct dvb_frontend *demod)
···
 	struct dib9000_state *st = demod->demodulator_priv;
 	u8 index_frontend;
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
 		dvb_frontend_detach(st->fe[index_frontend]);
 
 	DibFreeLock(&state->platform.risc.mbx_if_lock);
···
 	u8 index_frontend;
 	int ret;
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
 		if (ret < 0)
 			return ret;
···
 	fe_status_t stat;
 	int ret;
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
 		if (stat & FE_HAS_SYNC) {
 			dprintk("TPS lock on the slave%i", index_frontend);
 
 			/* synchronize the cache with the other frontends */
 			state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
-			for (sub_index_frontend=0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
+			for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
+			     sub_index_frontend++) {
 				if (sub_index_frontend != index_frontend) {
-					state->fe[sub_index_frontend]->dtv_property_cache.modulation = state->fe[index_frontend]->dtv_property_cache.modulation;
-					state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
-					state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
-					state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
-					state->fe[sub_index_frontend]->dtv_property_cache.hierarchy = state->fe[index_frontend]->dtv_property_cache.hierarchy;
-					state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP = state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
-					state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP = state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
-					state->fe[sub_index_frontend]->dtv_property_cache.rolloff = state->fe[index_frontend]->dtv_property_cache.rolloff;
+					state->fe[sub_index_frontend]->dtv_property_cache.modulation =
+					    state->fe[index_frontend]->dtv_property_cache.modulation;
+					state->fe[sub_index_frontend]->dtv_property_cache.inversion =
+					    state->fe[index_frontend]->dtv_property_cache.inversion;
+					state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode =
+					    state->fe[index_frontend]->dtv_property_cache.transmission_mode;
+					state->fe[sub_index_frontend]->dtv_property_cache.guard_interval =
+					    state->fe[index_frontend]->dtv_property_cache.guard_interval;
+					state->fe[sub_index_frontend]->dtv_property_cache.hierarchy =
+					    state->fe[index_frontend]->dtv_property_cache.hierarchy;
+					state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP =
+					    state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
+					state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP =
+					    state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
+					state->fe[sub_index_frontend]->dtv_property_cache.rolloff =
+					    state->fe[index_frontend]->dtv_property_cache.rolloff;
 				}
 			}
 			return 0;
···
 		return ret;
 
 	/* synchronize the cache with the other frontends */
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
 		state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
 		state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
···
 
 	/* set the master status */
 	if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
-		fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
+	    fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
 		/* no channel specified, autosearch the channel */
 		state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
 	} else
 		state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
 
 	/* set mode and status for the different frontends */
-	for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
 
 		/* synchronization of the cache */
···
 	}
 
 	/* actual tune */
-	exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
+	exit_condition = 0;	/* 0: tune pending; 1: tune failed; 2:tune success */
 	index_frontend_success = 0;
 	do {
 		sleep_time = dib9000_fw_tune(state->fe[0], NULL);
-		for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+		for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 			sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
 			if (sleep_time == FE_CALLBACK_TIME_NEVER)
 				sleep_time = sleep_time_slave;
···
 		nbr_pending = 0;
 		exit_condition = 0;
 		index_frontend_success = 0;
-		for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+		for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 			frontend_status = -dib9000_get_status(state->fe[index_frontend]);
 			if (frontend_status > -FE_STATUS_TUNE_PENDING) {
-				exit_condition = 2; /* tune success */
+				exit_condition = 2;	/* tune success */
 				index_frontend_success = index_frontend;
 				break;
 			}
 			if (frontend_status == -FE_STATUS_TUNE_PENDING)
-				nbr_pending++; /* some frontends are still tuning */
+				nbr_pending++;	/* some frontends are still tuning */
 		}
 		if ((exit_condition != 2) && (nbr_pending == 0))
-			exit_condition = 1; /* if all tune are done and no success, exit: tune failed */
+			exit_condition = 1;	/* if all tune are done and no success, exit: tune failed */
 
 	} while (exit_condition == 0);
 
 	/* check the tune result */
-	if (exit_condition == 1) { /* tune failed */
+	if (exit_condition == 1) {	/* tune failed */
 		dprintk("tune failed");
 		return 0;
 	}
···
 
 	/* retune the other frontends with the found channel */
 	channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
-	for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		/* only retune the frontends which was not tuned success */
 		if (index_frontend != index_frontend_success) {
 			dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
···
 	}
 	do {
 		sleep_time = FE_CALLBACK_TIME_NEVER;
-		for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+		for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 			if (index_frontend != index_frontend_success) {
 				sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
 				if (sleep_time == FE_CALLBACK_TIME_NEVER)
···
 			break;
 
 		nbr_pending = 0;
-		for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+		for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 			if (index_frontend != index_frontend_success) {
 				frontend_status = -dib9000_get_status(state->fe[index_frontend]);
 				if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
-					nbr_pending++; /* some frontends are still tuning */
+					nbr_pending++;	/* some frontends are still tuning */
 			}
 		}
 	} while (nbr_pending != 0);
 
 	/* set the output mode */
 	dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
 		dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
 
 	/* turn off the diversity for the last frontend */
-	dib9000_fw_set_diversity_in(state->fe[index_frontend-1], 0);
+	dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0);
 
 	return 0;
 }
···
 	u8 index_frontend;
 	u16 lock = 0, lock_slave = 0;
 
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
 		lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
 
 	lock = dib9000_read_word(state, 535);
···
 	u16 val;
 
 	*strength = 0;
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
 		state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
 		if (val > 65535 - *strength)
 			*strength = 65535;
···
 	u32 snr_master;
 
 	snr_master = dib9000_get_snr(fe);
-	for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+	for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
 		snr_master += dib9000_get_snr(state->fe[index_frontend]);
 
 	if ((snr_master >> 16) != 0) {
···
 	struct i2c_device client = {.i2c_adap = i2c };
 
 	client.i2c_addr = default_addr + 16;
-	dib9000_i2c_write16(&client, 1796, 0x0);	// select DVB-T output
+	dib9000_i2c_write16(&client, 1796, 0x0);
 
 	for (k = no_of_demods - 1; k >= 0; k--) {
 		/* designated i2c address */
···
 
 	return 0;
 }
-
 EXPORT_SYMBOL(dib9000_i2c_enumeration);
 
 int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
···
 	while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
 		index_frontend++;
 	if (index_frontend != 1) {
-		dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);
+		dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1);
 		state->fe[index_frontend] = NULL;
 		return 0;
 	}
···
 }
 EXPORT_SYMBOL(dib9000_remove_slave_frontend);
 
-struct dvb_frontend * dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
+struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
 {
 	struct dib9000_state *state = fe->demodulator_priv;
 
···
 
 	return fe;
 
- component_bus_add_error:
+component_bus_add_error:
 	i2c_del_adapter(&st->tuner_adap);
- error:
+error:
 	kfree(st);
 	return NULL;
 }
-
 EXPORT_SYMBOL(dib9000_attach);
 
 static struct dvb_frontend_ops dib9000_ops = {

drivers/media/dvb/frontends/dib9000.h

···
 extern int dib9000_firmware_post_pll_init(struct dvb_frontend *fe);
 extern int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
 extern int dib9000_remove_slave_frontend(struct dvb_frontend *fe);
-extern struct dvb_frontend * dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
+extern struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
 extern struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe);
 extern int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c);
 extern int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed);
···
 	return -ENODEV;
 }
 
-static inline struct dvb_frontend * dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index) {
+static inline struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
+{
 	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
 	return NULL;
 }

drivers/media/dvb/frontends/dibx000_common.c

···
 	u8 wb[2] = { reg >> 8, reg & 0xff };
 	u8 rb[2];
 	struct i2c_msg msg[2] = {
-		{.addr = mst->i2c_addr,.flags = 0,.buf = wb,.len = 2},
-		{.addr = mst->i2c_addr,.flags = I2C_M_RD,.buf = rb,.len = 2},
+		{.addr = mst->i2c_addr, .flags = 0, .buf = wb, .len = 2},
+		{.addr = mst->i2c_addr, .flags = I2C_M_RD, .buf = rb, .len = 2},
 	};
 
 	if (i2c_transfer(mst->i2c_adap, msg, 2) != 2)
···
 
 static int dibx000_is_i2c_done(struct dibx000_i2c_master *mst)
 {
-	int i = 100; // max_i2c_polls;
+	int i = 100;
 	u16 status;
 
-	while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0);
+	while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0)
+		;
 
 	/* i2c timed out */
 	if (i == 0)
···
 	const u8 *b = msg->buf;
 
 	while (txlen) {
-		dibx000_read_word(mst, mst->base_reg + 2);   // reset fifo ptr
+		dibx000_read_word(mst, mst->base_reg + 2);
 
 		len = txlen > 8 ? 8 : txlen;
 		for (i = 0; i < len; i += 2) {
···
 				data |= *b++;
 			dibx000_write_word(mst, mst->base_reg, data);
 		}
-		da = (((u8) (msg->addr))  << 9) | // addr
-			(1           << 8) | // master
-			(1           << 7) | // rq
-			(0           << 6) | // stop
-			(0           << 5) | // start
-			((len & 0x7) << 2) | // nb 8 bytes == 0 here
-			(0           << 1) | // rw
-			(0           << 0);  // irqen
+		da = (((u8) (msg->addr))  << 9) |
+			(1           << 8) |
+			(1           << 7) |
+			(0           << 6) |
+			(0           << 5) |
+			((len & 0x7) << 2) |
+			(0           << 1) |
+			(0           << 0);
 
 		if (txlen == msg->len)
 			da |= 1 << 5; /* start */
···
 
 	while (rxlen) {
 		len = rxlen > 8 ? 8 : rxlen;
-		da = (((u8) (msg->addr)) << 9) | // addr
-			(1           << 8) | // master
-			(1           << 7) | // rq
-			(0           << 6) | // stop
-			(0           << 5) | // start
-			((len & 0x7) << 2) | // nb
-			(1           << 1) | // rw
-			(0           << 0);  // irqen
+		da = (((u8) (msg->addr)) << 9) |
+			(1           << 8) |
+			(1           << 7) |
+			(0           << 6) |
+			(0           << 5) |
+			((len & 0x7) << 2) |
+			(1           << 1) |
+			(0           << 0);
 
 		if (rxlen == msg->len)
 			da |= 1 << 5; /* start */
···
 	int ret = 0;
 
 	dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_1_2);
-	for (msg_index = 0; msg_index<num; msg_index++) {
-		if (msg[msg_index].flags & I2C_M_RD)
-		{
+	for (msg_index = 0; msg_index < num; msg_index++) {
+		if (msg[msg_index].flags & I2C_M_RD) {
 			ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
 			if (ret != 0)
 				return 0;
-		}
-		else
-		{
+		} else {
 			ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
 			if (ret != 0)
 				return 0;
···
 	int ret = 0;
 
 	dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_3_4);
-	for (msg_index = 0; msg_index<num; msg_index++) {
-		if (msg[msg_index].flags & I2C_M_RD)
-		{
+	for (msg_index = 0; msg_index < num; msg_index++) {
+		if (msg[msg_index].flags & I2C_M_RD) {
 			ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
 			if (ret != 0)
 				return 0;
-		}
-		else
-		{
+		} else {
 			ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
 			if (ret != 0)
 				return 0;

drivers/media/dvb/frontends/dibx000_common.h

···
 
 	enum dibx000_i2c_interface selected_interface;
 
-//	struct i2c_adapter  tuner_i2c_adap;
+/*	struct i2c_adapter  tuner_i2c_adap; */
 	struct i2c_adapter gated_tuner_i2c_adap;
 	struct i2c_adapter master_i2c_adap_gpio12;
 	struct i2c_adapter master_i2c_adap_gpio34;
···
 #define BAND_FM	   0x10
 #define BAND_CBAND 0x20
 
-#define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 170000 ? BAND_CBAND : \
+#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
 									(freq_kHz) <= 115000 ? BAND_FM : \
 									(freq_kHz) <= 250000 ? BAND_VHF : \
 									(freq_kHz) <= 863000 ? BAND_UHF : \
···
 	DIBX000_VBG_DISABLE,
 };
 
-#define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ  ? 8000 : \
+#define BANDWIDTH_TO_KHZ(v) ((v) == BANDWIDTH_8_MHZ  ? 8000 : \
 				(v) == BANDWIDTH_7_MHZ  ? 7000 : \
-				(v) == BANDWIDTH_6_MHZ  ? 6000 : 8000 )
+				(v) == BANDWIDTH_6_MHZ  ? 6000 : 8000)
 
 #define BANDWIDTH_TO_INDEX(v) ( \
 	(v) == 8000 ? BANDWIDTH_8_MHZ : \
···
 
 #define FE_CALLBACK_TIME_NEVER 0xffffffff
 
-#define ABS(x) ((x<0)?(-x):(x))
+#define ABS(x) ((x < 0) ? (-x) : (x))
 
 #define DATA_BUS_ACCESS_MODE_8BIT                 0x01
 #define DATA_BUS_ACCESS_MODE_16BIT                0x02