···1010 - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks1111 - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks1212 - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks1313- - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks1313+ - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks1414+ - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks1515+ - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks1416 - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks1515- - "renesas,cpg-div6-clock" for generic DIV6 clocks1717+ and "renesas,cpg-div6-clock" as a fallback.1618 - reg: Base address and length of the memory resource used by the DIV6 clock1719 - clocks: Reference to the parent clock(s); either one, four, or eight1820 clocks must be specified. For clocks with multiple parents, invalid
···1313 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks1414 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks1515 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks1616+ - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks1617 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks1718 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks1818- - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks1919+ - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks2020+ - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks1921 - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks2022 - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks2121- - "renesas,cpg-mstp-clock" for generic MSTP gate clocks2323+ and "renesas,cpg-mstp-clocks" as a fallback.2224 - reg: Base address and length of the I/O mapped registers used by the MSTP2325 clocks. The first register is the clock control register and is mandatory.2426 The second register is the clock status register and is optional when not
···1010 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG1111 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG1212 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG1313- - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG1313+ and "renesas,rcar-gen2-cpg-clocks" as a fallback.14141515 - reg: Base address and length of the memory resource used by the CPG1616
···7788 - compatible: Must be one of99 - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG1010- - "renesas,rz-cpg-clocks" for the generic RZ CPG1010+ and "renesas,rz-cpg-clocks" as a fallback.1111 - reg: Base address and length of the memory resource used by the CPG1212 - clocks: References to possible parent clocks. Order must match clock modes1313 in the datasheet. For the r7s72100, this is extal, usb_x1.