[ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.

Only System PLL clock source is selectable by CSCR_SYSTEM_SEL
bit. MPU PLL is driven by 512*CLK32 for each case.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by Pavel Pisa and committed by Russell King b3c6b76f 83b84c4e

+8 -7
+3 -3
arch/arm/mach-imx/cpufreq.c
··· 83 * imx_compute_mpctl - compute new PLL parameters 84 * @new_mpctl: pointer to location assigned by new PLL control register value 85 * @cur_mpctl: current PLL control register parameters 86 * @freq: required frequency in Hz 87 * @relation: is one of %CPUFREQ_RELATION_L (supremum) 88 * and %CPUFREQ_RELATION_H (infimum) 89 */ 90 - long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, unsigned long freq, int relation) 91 { 92 - u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); 93 u32 mfi; 94 u32 mfn; 95 u32 mfd; ··· 204 sysclk = imx_get_system_clk(); 205 206 if (freq > sysclk / bclk_div_at_boot + 1000000) { 207 - freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, freq, relation); 208 if (freq < 0) { 209 printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq); 210 return -EINVAL;
··· 83 * imx_compute_mpctl - compute new PLL parameters 84 * @new_mpctl: pointer to location assigned by new PLL control register value 85 * @cur_mpctl: current PLL control register parameters 86 + * @f_ref: reference source frequency Hz 87 * @freq: required frequency in Hz 88 * @relation: is one of %CPUFREQ_RELATION_L (supremum) 89 * and %CPUFREQ_RELATION_H (infimum) 90 */ 91 + long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation) 92 { 93 u32 mfi; 94 u32 mfn; 95 u32 mfd; ··· 204 sysclk = imx_get_system_clk(); 205 206 if (freq > sysclk / bclk_div_at_boot + 1000000) { 207 + freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation); 208 if (freq < 0) { 209 printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq); 210 return -EINVAL;
+5 -4
arch/arm/mach-imx/generic.c
··· 102 * f = 2 * f_ref * -------------------- 103 * pd + 1 104 */ 105 - static unsigned int imx_decode_pll(unsigned int pll) 106 { 107 unsigned long long ll; 108 unsigned long quot; ··· 111 u32 mfn = pll & 0x3ff; 112 u32 mfd = (pll >> 16) & 0x3ff; 113 u32 pd = (pll >> 26) & 0xf; 114 - u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); 115 116 mfi = mfi <= 5 ? 5 : mfi; 117 ··· 123 124 unsigned int imx_get_system_clk(void) 125 { 126 - return imx_decode_pll(SPCTL0); 127 } 128 EXPORT_SYMBOL(imx_get_system_clk); 129 130 unsigned int imx_get_mcu_clk(void) 131 { 132 - return imx_decode_pll(MPCTL0); 133 } 134 EXPORT_SYMBOL(imx_get_mcu_clk); 135
··· 102 * f = 2 * f_ref * -------------------- 103 * pd + 1 104 */ 105 + static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref) 106 { 107 unsigned long long ll; 108 unsigned long quot; ··· 111 u32 mfn = pll & 0x3ff; 112 u32 mfd = (pll >> 16) & 0x3ff; 113 u32 pd = (pll >> 26) & 0xf; 114 115 mfi = mfi <= 5 ? 5 : mfi; 116 ··· 124 125 unsigned int imx_get_system_clk(void) 126 { 127 + u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); 128 + 129 + return imx_decode_pll(SPCTL0, f_ref); 130 } 131 EXPORT_SYMBOL(imx_get_system_clk); 132 133 unsigned int imx_get_mcu_clk(void) 134 { 135 + return imx_decode_pll(MPCTL0, CLK32 * 512); 136 } 137 EXPORT_SYMBOL(imx_get_mcu_clk); 138