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linux
dt-bindings: watchdog: aspeed,ast2400-wdt: Add support for AST2700
Add support for the AST2700 SoC in the ASPEED watchdog device tree
bindings. This includes:
- Adding "aspeed,ast2700-wdt" to the compatible string list.
- Extending the "aspeed,reset-mask" property description for AST2700.
- Defining AST2700-specific reset mask bits in aspeed-wdt.h,
covering RESET1 to RESET5.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
authored by
Chin-Ting Kuo
and committed by
Wim Van Sebroeck
b3bc229b
1cafd2a8
+144
-2
+6
-2
Documentation/devicetree/bindings/watchdog/aspeed,ast2400-wdt.yaml
+6
-2
Documentation/devicetree/bindings/watchdog/aspeed,ast2400-wdt.yaml
···
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- aspeed,ast2400-wdt
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- aspeed,ast2500-wdt
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- aspeed,ast2600-wdt
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+
- aspeed,ast2700-wdt
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reg:
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maxItems: 1
···
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aspeed,reset-mask:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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-
maxItems: 2
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maxItems: 5
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description: >
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A bitmask indicating which peripherals will be reset if the watchdog
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timer expires. On AST2500 SoCs this should be a single word defined using
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the AST2500_WDT_RESET_* macros; on AST2600 SoCs this should be a two-word
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array with the first word defined using the AST2600_WDT_RESET1_* macros,
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-
and the second word defined using the AST2600_WDT_RESET2_* macros.
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and the second word defined using the AST2600_WDT_RESET2_* macros; on
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AST2700 SoCs, this should be five-word array from AST2700_WDT_RESET1_*
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macros to AST2700_WDT_RESET5_* macros.
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required:
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- compatible
···
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enum:
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- aspeed,ast2500-wdt
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- aspeed,ast2600-wdt
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- aspeed,ast2700-wdt
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- if:
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required:
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- aspeed,ext-active-high
+138
include/dt-bindings/watchdog/aspeed-wdt.h
+138
include/dt-bindings/watchdog/aspeed-wdt.h
···
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#define AST2600_WDT_RESET2_DEFAULT 0x03fffff1
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#define AST2700_WDT_RESET1_CPU (1 << 0)
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#define AST2700_WDT_RESET1_DRAM (1 << 1)
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#define AST2700_WDT_RESET1_SLI0 (1 << 2)
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#define AST2700_WDT_RESET1_EHCI (1 << 3)
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#define AST2700_WDT_RESET1_HACE (1 << 4)
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#define AST2700_WDT_RESET1_SOC_MISC0 (1 << 5)
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#define AST2700_WDT_RESET1_VIDEO (1 << 6)
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#define AST2700_WDT_RESET1_2D_GRAPHIC (1 << 7)
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#define AST2700_WDT_RESET1_RAVS0 (1 << 8)
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#define AST2700_WDT_RESET1_RAVS1 (1 << 9)
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#define AST2700_WDT_RESET1_GPIO0 (1 << 10)
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#define AST2700_WDT_RESET1_SSP (1 << 11)
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#define AST2700_WDT_RESET1_TSP (1 << 12)
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#define AST2700_WDT_RESET1_CRT (1 << 13)
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#define AST2700_WDT_RESET1_USB20_HOST (1 << 14)
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#define AST2700_WDT_RESET1_USB11_HOST (1 << 15)
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#define AST2700_WDT_RESET1_UFS (1 << 16)
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#define AST2700_WDT_RESET1_EMMC (1 << 17)
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#define AST2700_WDT_RESET1_AHB_TO_PCIE1 (1 << 18)
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#define AST2700_WDT_RESET1_XDMA0 (1 << 22)
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#define AST2700_WDT_RESET1_MCTP1 (1 << 23)
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#define AST2700_WDT_RESET1_MCTP0 (1 << 24)
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#define AST2700_WDT_RESET1_JTAG0 (1 << 25)
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#define AST2700_WDT_RESET1_ECC (1 << 26)
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#define AST2700_WDT_RESET1_XDMA1 (1 << 27)
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#define AST2700_WDT_RESET1_DP (1 << 28)
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#define AST2700_WDT_RESET1_DP_MCU (1 << 29)
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#define AST2700_WDT_RESET1_AHB_TO_PCIE0 (1 << 31)
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#define AST2700_WDT_RESET1_DEFAULT 0x8207ff71
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#define AST2700_WDT_RESET2_USB3_A_HOST (1 << 0)
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#define AST2700_WDT_RESET2_USB3_A_VHUB3 (1 << 1)
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#define AST2700_WDT_RESET2_USB3_A_VHUB2 (1 << 2)
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#define AST2700_WDT_RESET2_USB3_B_HOST (1 << 3)
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#define AST2700_WDT_RESET2_USB3_B_VHUB3 (1 << 4)
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#define AST2700_WDT_RESET2_USB3_B_VHUB2 (1 << 5)
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#define AST2700_WDT_RESET2_SM3 (1 << 6)
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#define AST2700_WDT_RESET2_SM4 (1 << 7)
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#define AST2700_WDT_RESET2_SHA3 (1 << 8)
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#define AST2700_WDT_RESET2_RSA (1 << 9)
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#define AST2700_WDT_RESET2_DEFAULT 0x000003f6
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#define AST2700_WDT_RESET3_LPC0 (1 << 0)
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#define AST2700_WDT_RESET3_LPC1 (1 << 1)
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#define AST2700_WDT_RESET3_MDIO (1 << 2)
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#define AST2700_WDT_RESET3_PECI (1 << 3)
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#define AST2700_WDT_RESET3_PWM (1 << 4)
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#define AST2700_WDT_RESET3_MAC0 (1 << 5)
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#define AST2700_WDT_RESET3_MAC1 (1 << 6)
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#define AST2700_WDT_RESET3_MAC2 (1 << 7)
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#define AST2700_WDT_RESET3_ADC (1 << 8)
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#define AST2700_WDT_RESET3_SDC (1 << 9)
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#define AST2700_WDT_RESET3_ESPI0 (1 << 10)
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#define AST2700_WDT_RESET3_ESPI1 (1 << 11)
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#define AST2700_WDT_RESET3_JTAG1 (1 << 12)
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#define AST2700_WDT_RESET3_SPI0 (1 << 13)
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#define AST2700_WDT_RESET3_SPI1 (1 << 14)
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#define AST2700_WDT_RESET3_SPI2 (1 << 15)
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#define AST2700_WDT_RESET3_I3C0 (1 << 16)
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#define AST2700_WDT_RESET3_I3C1 (1 << 17)
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#define AST2700_WDT_RESET3_I3C2 (1 << 18)
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#define AST2700_WDT_RESET3_I3C3 (1 << 19)
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#define AST2700_WDT_RESET3_I3C4 (1 << 20)
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#define AST2700_WDT_RESET3_I3C5 (1 << 21)
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#define AST2700_WDT_RESET3_I3C6 (1 << 22)
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#define AST2700_WDT_RESET3_I3C7 (1 << 23)
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#define AST2700_WDT_RESET3_I3C8 (1 << 24)
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#define AST2700_WDT_RESET3_I3C9 (1 << 25)
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#define AST2700_WDT_RESET3_I3C10 (1 << 26)
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#define AST2700_WDT_RESET3_I3C11 (1 << 27)
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#define AST2700_WDT_RESET3_I3C12 (1 << 28)
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#define AST2700_WDT_RESET3_I3C13 (1 << 29)
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#define AST2700_WDT_RESET3_I3C14 (1 << 30)
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#define AST2700_WDT_RESET3_I3C15 (1 << 31)
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#define AST2700_WDT_RESET3_DEFAULT 0x000093ec
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#define AST2700_WDT_RESET4_FMC (1 << 0)
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#define AST2700_WDT_RESET4_SOC_MISC1 (1 << 1)
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#define AST2700_WDT_RESET4_AHB (1 << 2)
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#define AST2700_WDT_RESET4_SLI1 (1 << 3)
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#define AST2700_WDT_RESET4_UART0 (1 << 4)
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#define AST2700_WDT_RESET4_UART1 (1 << 5)
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#define AST2700_WDT_RESET4_UART2 (1 << 6)
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#define AST2700_WDT_RESET4_UART3 (1 << 7)
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#define AST2700_WDT_RESET4_I2C_MONITOR (1 << 8)
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#define AST2700_WDT_RESET4_HOST_TO_SPI1 (1 << 9)
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#define AST2700_WDT_RESET4_HOST_TO_SPI2 (1 << 10)
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#define AST2700_WDT_RESET4_GPIO1 (1 << 11)
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#define AST2700_WDT_RESET4_FSI (1 << 12)
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#define AST2700_WDT_RESET4_CANBUS (1 << 13)
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#define AST2700_WDT_RESET4_MCTP (1 << 14)
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#define AST2700_WDT_RESET4_XDMA (1 << 15)
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#define AST2700_WDT_RESET4_UART5 (1 << 16)
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#define AST2700_WDT_RESET4_UART6 (1 << 17)
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#define AST2700_WDT_RESET4_UART7 (1 << 18)
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#define AST2700_WDT_RESET4_UART8 (1 << 19)
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#define AST2700_WDT_RESET4_BOOT_MCU (1 << 20)
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#define AST2700_WDT_RESET4_IO_MCU (1 << 21)
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#define AST2700_WDT_RESET4_LTPI0 (1 << 22)
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#define AST2700_WDT_RESET4_VGA_LINK (1 << 23)
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#define AST2700_WDT_RESET4_LTPI1 (1 << 24)
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#define AST2700_WDT_RESET4_LTPI_PHY (1 << 25)
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#define AST2700_WDT_RESET4_ACE (1 << 26)
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#define AST2700_WDT_RESET4_LTPI_GPIO0 (1 << 28)
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#define AST2700_WDT_RESET4_LTPI_GPIO1 (1 << 29)
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#define AST2700_WDT_RESET4_AHB_TO_PCIE1 (1 << 30)
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#define AST2700_WDT_RESET4_I3C_DMA (1 << 31)
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#define AST2700_WDT_RESET4_DEFAULT 0x40303803
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#define AST2700_WDT_RESET5_I2C_GLOBAL (1 << 0)
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#define AST2700_WDT_RESET5_I2C0 (1 << 1)
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#define AST2700_WDT_RESET5_I2C1 (1 << 2)
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#define AST2700_WDT_RESET5_I2C2 (1 << 3)
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#define AST2700_WDT_RESET5_I2C3 (1 << 4)
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#define AST2700_WDT_RESET5_I2C4 (1 << 5)
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#define AST2700_WDT_RESET5_I2C5 (1 << 6)
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#define AST2700_WDT_RESET5_I2C6 (1 << 7)
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#define AST2700_WDT_RESET5_I2C7 (1 << 8)
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#define AST2700_WDT_RESET5_I2C8 (1 << 9)
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#define AST2700_WDT_RESET5_I2C9 (1 << 10)
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#define AST2700_WDT_RESET5_I2C10 (1 << 11)
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#define AST2700_WDT_RESET5_I2C11 (1 << 12)
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#define AST2700_WDT_RESET5_I2C12 (1 << 13)
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#define AST2700_WDT_RESET5_I2C13 (1 << 14)
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#define AST2700_WDT_RESET5_I2C14 (1 << 15)
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#define AST2700_WDT_RESET5_I2C15 (1 << 16)
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#define AST2700_WDT_RESET5_UHCI (1 << 17)
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#define AST2700_WDT_RESET5_USB2_C_UART (1 << 18)
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#define AST2700_WDT_RESET5_USB2_C (1 << 19)
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#define AST2700_WDT_RESET5_USB2_D_UART (1 << 20)
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#define AST2700_WDT_RESET5_USB2_D (1 << 21)
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#define AST2700_WDT_RESET5_DEFAULT 0x00320000
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#endif