···27272828/*2929 * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.3030- * Since IRQ block starts from address 0x002 we need to substract that from3030+ * Since IRQ block starts from address 0x002 we need to subtract that from3131 * the actual IRQ status register address.3232 */3333#define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))