Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

staging:r8188eu: remove NumTotalRFPath member of hal_data_8188e structure

NumTotalRFPath is 1 for r8188eu chip.

Signed-off-by: Ivan Safonov <insafonov@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Ivan Safonov and committed by
Greg Kroah-Hartman
b39db0b1 76fe8b32

+49 -106
+4 -7
drivers/staging/rtl8188eu/hal/phy.c
··· 278 278 279 279 static void phy_sw_chnl_callback(struct adapter *adapt, u8 channel) 280 280 { 281 - u8 rf_path; 282 281 u32 param1, param2; 283 282 struct hal_data_8188e *hal_data = adapt->HalData; 284 283 ··· 285 286 286 287 param1 = RF_CHNLBW; 287 288 param2 = channel; 288 - for (rf_path = 0; rf_path < hal_data->NumTotalRFPath; rf_path++) { 289 - hal_data->RfRegChnlVal[rf_path] = (hal_data->RfRegChnlVal[rf_path] & 290 - 0xfffffc00) | param2; 291 - phy_set_rf_reg(adapt, (enum rf_radio_path)rf_path, param1, 292 - bRFRegOffsetMask, hal_data->RfRegChnlVal[rf_path]); 293 - } 289 + hal_data->RfRegChnlVal[0] = (hal_data->RfRegChnlVal[0] & 290 + 0xfffffc00) | param2; 291 + phy_set_rf_reg(adapt, 0, param1, 292 + bRFRegOffsetMask, hal_data->RfRegChnlVal[0]); 294 293 } 295 294 296 295 void rtw_hal_set_chan(struct adapter *adapt, u8 channel)
+9 -11
drivers/staging/rtl8188eu/hal/rf.c
··· 137 137 (powerbase0<<8) | powerbase0; 138 138 *(ofdmbase+i) = powerbase0; 139 139 } 140 - for (i = 0; i < adapt->HalData->NumTotalRFPath; i++) { 141 - /* Check HT20 to HT40 diff */ 142 - if (adapt->HalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) 143 - powerlevel[i] = pwr_level_bw20[i]; 144 - else 145 - powerlevel[i] = pwr_level_bw40[i]; 146 - powerbase1 = powerlevel[i]; 147 - powerbase1 = (powerbase1<<24) | (powerbase1<<16) | 148 - (powerbase1<<8) | powerbase1; 149 - *(mcs_base+i) = powerbase1; 150 - } 140 + /* Check HT20 to HT40 diff */ 141 + if (adapt->HalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) 142 + powerlevel[0] = pwr_level_bw20[0]; 143 + else 144 + powerlevel[0] = pwr_level_bw40[0]; 145 + powerbase1 = powerlevel[0]; 146 + powerbase1 = (powerbase1<<24) | (powerbase1<<16) | 147 + (powerbase1<<8) | powerbase1; 148 + *mcs_base = powerbase1; 151 149 } 152 150 static void get_rx_power_val_by_reg(struct adapter *adapt, u8 channel, 153 151 u8 index, u32 *powerbase0, u32 *powerbase1,
+12 -58
drivers/staging/rtl8188eu/hal/rf_cfg.c
··· 230 230 { 231 231 struct hal_data_8188e *hal_data = adapt->HalData; 232 232 u32 u4val = 0; 233 - u8 rfpath; 234 233 bool rtstatus = true; 235 234 struct bb_reg_def *pphyreg; 236 235 237 - for (rfpath = 0; rfpath < hal_data->NumTotalRFPath; rfpath++) { 238 - pphyreg = &hal_data->PHYRegDef[rfpath]; 236 + pphyreg = &hal_data->PHYRegDef[RF90_PATH_A]; 237 + u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs, BRFSI_RFENV); 239 238 240 - switch (rfpath) { 241 - case RF90_PATH_A: 242 - case RF90_PATH_C: 243 - u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs, 244 - BRFSI_RFENV); 245 - break; 246 - case RF90_PATH_B: 247 - case RF90_PATH_D: 248 - u4val = phy_query_bb_reg(adapt, pphyreg->rfintfs, 249 - BRFSI_RFENV << 16); 250 - break; 251 - } 239 + phy_set_bb_reg(adapt, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); 240 + udelay(1); 252 241 253 - phy_set_bb_reg(adapt, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); 254 - udelay(1); 242 + phy_set_bb_reg(adapt, pphyreg->rfintfo, BRFSI_RFENV, 0x1); 243 + udelay(1); 255 244 256 - phy_set_bb_reg(adapt, pphyreg->rfintfo, BRFSI_RFENV, 0x1); 257 - udelay(1); 245 + phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREADDREAALENGTH, 0x0); 246 + udelay(1); 258 247 259 - phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, 260 - B3WIREADDREAALENGTH, 0x0); 261 - udelay(1); 248 + phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREDATALENGTH, 0x0); 249 + udelay(1); 262 250 263 - phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, 264 - B3WIREDATALENGTH, 0x0); 265 - udelay(1); 251 + rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt); 266 252 267 - switch (rfpath) { 268 - case RF90_PATH_A: 269 - rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt); 270 - break; 271 - case RF90_PATH_B: 272 - rtstatus = rtl88e_phy_config_rf_with_headerfile(adapt); 273 - break; 274 - case RF90_PATH_C: 275 - break; 276 - case RF90_PATH_D: 277 - break; 278 - } 279 - 280 - switch (rfpath) { 281 - case RF90_PATH_A: 282 - case RF90_PATH_C: 283 - phy_set_bb_reg(adapt, pphyreg->rfintfs, 284 - BRFSI_RFENV, u4val); 285 - break; 286 - case RF90_PATH_B: 287 - case RF90_PATH_D: 288 - phy_set_bb_reg(adapt, pphyreg->rfintfs, 289 - BRFSI_RFENV << 16, u4val); 290 - break; 291 - } 292 - 293 - if (!rtstatus) 294 - return false; 295 - } 253 + phy_set_bb_reg(adapt, pphyreg->rfintfs, BRFSI_RFENV, u4val); 296 254 297 255 return rtstatus; 298 256 } 299 257 300 258 static bool rtl88e_phy_rf6052_config(struct adapter *adapt) 301 259 { 302 - struct hal_data_8188e *hal_data = adapt->HalData; 303 - 304 - hal_data->NumTotalRFPath = 1; 305 - 306 260 return rf6052_conf_para(adapt); 307 261 } 308 262
+24 -27
drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c
··· 135 135 dump_chip_info(ChipVersion); 136 136 137 137 pHalData->VersionID = ChipVersion; 138 - pHalData->NumTotalRFPath = 1; 139 138 } 140 139 141 140 void rtw_hal_set_odm_var(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet) ··· 469 470 { 470 471 struct hal_data_8188e *pHalData = padapter->HalData; 471 472 struct txpowerinfo24g pwrInfo24G; 472 - u8 rfPath, ch, group; 473 + u8 ch, group; 473 474 u8 bIn24G, TxCount; 474 475 475 476 Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail); ··· 477 478 if (!AutoLoadFail) 478 479 pHalData->bTXPowerDataReadFromEEPORM = true; 479 480 480 - for (rfPath = 0; rfPath < pHalData->NumTotalRFPath; rfPath++) { 481 - for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { 482 - bIn24G = Hal_GetChnlGroup88E(ch, &group); 483 - if (bIn24G) { 484 - pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group]; 485 - if (ch == 14) 486 - pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][4]; 487 - else 488 - pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group]; 489 - } 490 - if (bIn24G) { 491 - DBG_88E("======= Path %d, Channel %d =======\n", rfPath, ch); 492 - DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_CCK_Base[rfPath][ch]); 493 - DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_BW40_Base[rfPath][ch]); 494 - } 481 + for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { 482 + bIn24G = Hal_GetChnlGroup88E(ch, &group); 483 + if (bIn24G) { 484 + pHalData->Index24G_CCK_Base[0][ch] = pwrInfo24G.IndexCCK_Base[0][group]; 485 + if (ch == 14) 486 + pHalData->Index24G_BW40_Base[0][ch] = pwrInfo24G.IndexBW40_Base[0][4]; 487 + else 488 + pHalData->Index24G_BW40_Base[0][ch] = pwrInfo24G.IndexBW40_Base[0][group]; 495 489 } 496 - for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 497 - pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount]; 498 - pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount]; 499 - pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount]; 500 - pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount]; 501 - DBG_88E("======= TxCount %d =======\n", TxCount); 502 - DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]); 503 - DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]); 504 - DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]); 505 - DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]); 490 + if (bIn24G) { 491 + DBG_88E("======= Path %d, Channel %d =======\n", 0, ch); 492 + DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", 0, ch , pHalData->Index24G_CCK_Base[0][ch]); 493 + DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", 0, ch , pHalData->Index24G_BW40_Base[0][ch]); 506 494 } 495 + } 496 + for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 497 + pHalData->CCK_24G_Diff[0][TxCount] = pwrInfo24G.CCK_Diff[0][TxCount]; 498 + pHalData->OFDM_24G_Diff[0][TxCount] = pwrInfo24G.OFDM_Diff[0][TxCount]; 499 + pHalData->BW20_24G_Diff[0][TxCount] = pwrInfo24G.BW20_Diff[0][TxCount]; 500 + pHalData->BW40_24G_Diff[0][TxCount] = pwrInfo24G.BW40_Diff[0][TxCount]; 501 + DBG_88E("======= TxCount %d =======\n", TxCount); 502 + DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->CCK_24G_Diff[0][TxCount]); 503 + DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->OFDM_24G_Diff[0][TxCount]); 504 + DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->BW20_24G_Diff[0][TxCount]); 505 + DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->BW40_24G_Diff[0][TxCount]); 507 506 } 508 507 509 508 /* 2010/10/19 MH Add Regulator recognize for CU. */
-3
drivers/staging/rtl8188eu/include/rtl8188e_hal.h
··· 200 200 201 201 u16 BasicRateSet; 202 202 203 - /* rf_ctrl */ 204 - u8 NumTotalRFPath; 205 - 206 203 u8 BoardType; 207 204 208 205 /* EEPROM setting. */