Merge branch 'clk-amlogic' into clk-next

+119

drivers/clk/meson/g12a.c

··· 3981 3981 }, 3982 3982 }; 3983 3983 3984 + /* Neural Network Accelerator source clock */ 3985 + 3986 + static const struct clk_parent_data nna_clk_parent_data[] = { 3987 + { .fw_name = "xtal", }, 3988 + { .hw = &g12a_gp0_pll.hw, }, 3989 + { .hw = &g12a_hifi_pll.hw, }, 3990 + { .hw = &g12a_fclk_div2p5.hw, }, 3991 + { .hw = &g12a_fclk_div3.hw, }, 3992 + { .hw = &g12a_fclk_div4.hw, }, 3993 + { .hw = &g12a_fclk_div5.hw, }, 3994 + { .hw = &g12a_fclk_div7.hw }, 3995 + }; 3996 + 3997 + static struct clk_regmap sm1_nna_axi_clk_sel = { 3998 + .data = &(struct clk_regmap_mux_data){ 3999 + .offset = HHI_NNA_CLK_CNTL, 4000 + .mask = 7, 4001 + .shift = 9, 4002 + }, 4003 + .hw.init = &(struct clk_init_data){ 4004 + .name = "nna_axi_clk_sel", 4005 + .ops = &clk_regmap_mux_ops, 4006 + .parent_data = nna_clk_parent_data, 4007 + .num_parents = ARRAY_SIZE(nna_clk_parent_data), 4008 + }, 4009 + }; 4010 + 4011 + static struct clk_regmap sm1_nna_axi_clk_div = { 4012 + .data = &(struct clk_regmap_div_data){ 4013 + .offset = HHI_NNA_CLK_CNTL, 4014 + .shift = 0, 4015 + .width = 7, 4016 + }, 4017 + .hw.init = &(struct clk_init_data){ 4018 + .name = "nna_axi_clk_div", 4019 + .ops = &clk_regmap_divider_ops, 4020 + .parent_hws = (const struct clk_hw *[]) { 4021 + &sm1_nna_axi_clk_sel.hw 4022 + }, 4023 + .num_parents = 1, 4024 + .flags = CLK_SET_RATE_PARENT, 4025 + }, 4026 + }; 4027 + 4028 + static struct clk_regmap sm1_nna_axi_clk = { 4029 + .data = &(struct clk_regmap_gate_data){ 4030 + .offset = HHI_NNA_CLK_CNTL, 4031 + .bit_idx = 8, 4032 + }, 4033 + .hw.init = &(struct clk_init_data){ 4034 + .name = "nna_axi_clk", 4035 + .ops = &clk_regmap_gate_ops, 4036 + .parent_hws = (const struct clk_hw *[]) { 4037 + &sm1_nna_axi_clk_div.hw 4038 + }, 4039 + .num_parents = 1, 4040 + .flags = CLK_SET_RATE_PARENT, 4041 + }, 4042 + }; 4043 + 4044 + static struct clk_regmap sm1_nna_core_clk_sel = { 4045 + .data = &(struct clk_regmap_mux_data){ 4046 + .offset = HHI_NNA_CLK_CNTL, 4047 + .mask = 7, 4048 + .shift = 25, 4049 + }, 4050 + .hw.init = &(struct clk_init_data){ 4051 + .name = "nna_core_clk_sel", 4052 + .ops = &clk_regmap_mux_ops, 4053 + .parent_data = nna_clk_parent_data, 4054 + .num_parents = ARRAY_SIZE(nna_clk_parent_data), 4055 + }, 4056 + }; 4057 + 4058 + static struct clk_regmap sm1_nna_core_clk_div = { 4059 + .data = &(struct clk_regmap_div_data){ 4060 + .offset = HHI_NNA_CLK_CNTL, 4061 + .shift = 16, 4062 + .width = 7, 4063 + }, 4064 + .hw.init = &(struct clk_init_data){ 4065 + .name = "nna_core_clk_div", 4066 + .ops = &clk_regmap_divider_ops, 4067 + .parent_hws = (const struct clk_hw *[]) { 4068 + &sm1_nna_core_clk_sel.hw 4069 + }, 4070 + .num_parents = 1, 4071 + .flags = CLK_SET_RATE_PARENT, 4072 + }, 4073 + }; 4074 + 4075 + static struct clk_regmap sm1_nna_core_clk = { 4076 + .data = &(struct clk_regmap_gate_data){ 4077 + .offset = HHI_NNA_CLK_CNTL, 4078 + .bit_idx = 24, 4079 + }, 4080 + .hw.init = &(struct clk_init_data){ 4081 + .name = "nna_core_clk", 4082 + .ops = &clk_regmap_gate_ops, 4083 + .parent_hws = (const struct clk_hw *[]) { 4084 + &sm1_nna_core_clk_div.hw 4085 + }, 4086 + .num_parents = 1, 4087 + .flags = CLK_SET_RATE_PARENT, 4088 + }, 4089 + }; 4090 + 3984 4091 #define MESON_GATE(_name, _reg, _bit) \ 3985 4092 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) 3986 4093 ··· 4886 4779 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, 4887 4780 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, 4888 4781 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, 4782 + [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, 4783 + [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, 4784 + [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw, 4785 + [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, 4786 + [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, 4787 + [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw, 4889 4788 [NR_CLKS] = NULL, 4890 4789 }, 4891 4790 .num = NR_CLKS, ··· 5133 5020 &g12a_spicc1_sclk_sel, 5134 5021 &g12a_spicc1_sclk_div, 5135 5022 &g12a_spicc1_sclk, 5023 + &sm1_nna_axi_clk_sel, 5024 + &sm1_nna_axi_clk_div, 5025 + &sm1_nna_axi_clk, 5026 + &sm1_nna_core_clk_sel, 5027 + &sm1_nna_core_clk_div, 5028 + &sm1_nna_core_clk, 5136 5029 }; 5137 5030 5138 5031 static const struct reg_sequence g12a_init_regs[] = {

+6 -1

drivers/clk/meson/g12a.h

··· 70 70 #define HHI_MALI_CLK_CNTL 0x1b0 71 71 #define HHI_VPU_CLKC_CNTL 0x1b4 72 72 #define HHI_VPU_CLK_CNTL 0x1bC 73 + #define HHI_NNA_CLK_CNTL 0x1C8 73 74 #define HHI_HDMI_CLK_CNTL 0x1CC 74 75 #define HHI_VDEC_CLK_CNTL 0x1E0 75 76 #define HHI_VDEC2_CLK_CNTL 0x1E4 ··· 260 259 #define CLKID_SPICC0_SCLK_DIV 257 261 260 #define CLKID_SPICC1_SCLK_SEL 259 262 261 #define CLKID_SPICC1_SCLK_DIV 260 262 + #define CLKID_NNA_AXI_CLK_SEL 262 263 + #define CLKID_NNA_AXI_CLK_DIV 263 264 + #define CLKID_NNA_CORE_CLK_SEL 265 265 + #define CLKID_NNA_CORE_CLK_DIV 266 263 266 264 - #define NR_CLKS 262 267 + #define NR_CLKS 268 265 268 266 269 /* include the CLKIDs that have been made part of the DT binding */ 267 270 #include <dt-bindings/clock/g12a-clkc.h>

+50 -17

drivers/clk/meson/meson8b.c

··· 293 293 &meson8b_fclk_div2_div.hw 294 294 }, 295 295 .num_parents = 1, 296 - /* 297 - * FIXME: Ethernet with a RGMII PHYs is not working if 298 - * fclk_div2 is disabled. it is currently unclear why this 299 - * is. keep it enabled until the Ethernet driver knows how 300 - * to manage this clock. 301 - */ 302 - .flags = CLK_IS_CRITICAL, 303 296 }, 304 297 }; 305 298 ··· 1204 1211 }, 1205 1212 }; 1206 1213 1214 + static struct clk_regmap meson8b_vclk_en = { 1215 + .data = &(struct clk_regmap_gate_data){ 1216 + .offset = HHI_VID_CLK_CNTL, 1217 + .bit_idx = 19, 1218 + }, 1219 + .hw.init = &(struct clk_init_data){ 1220 + .name = "vclk_en", 1221 + .ops = &clk_regmap_gate_ro_ops, 1222 + .parent_hws = (const struct clk_hw *[]) { 1223 + &meson8b_vclk_in_en.hw 1224 + }, 1225 + .num_parents = 1, 1226 + .flags = CLK_SET_RATE_PARENT, 1227 + }, 1228 + }; 1229 + 1207 1230 static struct clk_regmap meson8b_vclk_div1_gate = { 1208 1231 .data = &(struct clk_regmap_gate_data){ 1209 1232 .offset = HHI_VID_CLK_CNTL, ··· 1229 1220 .name = "vclk_div1_en", 1230 1221 .ops = &clk_regmap_gate_ro_ops, 1231 1222 .parent_hws = (const struct clk_hw *[]) { 1232 - &meson8b_vclk_in_en.hw 1223 + &meson8b_vclk_en.hw 1233 1224 }, 1234 1225 .num_parents = 1, 1235 1226 .flags = CLK_SET_RATE_PARENT, ··· 1243 1234 .name = "vclk_div2", 1244 1235 .ops = &clk_fixed_factor_ops, 1245 1236 .parent_hws = (const struct clk_hw *[]) { 1246 - &meson8b_vclk_in_en.hw 1237 + &meson8b_vclk_en.hw 1247 1238 }, 1248 1239 .num_parents = 1, 1249 1240 .flags = CLK_SET_RATE_PARENT, ··· 1273 1264 .name = "vclk_div4", 1274 1265 .ops = &clk_fixed_factor_ops, 1275 1266 .parent_hws = (const struct clk_hw *[]) { 1276 - &meson8b_vclk_in_en.hw 1267 + &meson8b_vclk_en.hw 1277 1268 }, 1278 1269 .num_parents = 1, 1279 1270 .flags = CLK_SET_RATE_PARENT, ··· 1303 1294 .name = "vclk_div6", 1304 1295 .ops = &clk_fixed_factor_ops, 1305 1296 .parent_hws = (const struct clk_hw *[]) { 1306 - &meson8b_vclk_in_en.hw 1297 + &meson8b_vclk_en.hw 1307 1298 }, 1308 1299 .num_parents = 1, 1309 1300 .flags = CLK_SET_RATE_PARENT, ··· 1333 1324 .name = "vclk_div12", 1334 1325 .ops = &clk_fixed_factor_ops, 1335 1326 .parent_hws = (const struct clk_hw *[]) { 1336 - &meson8b_vclk_in_en.hw 1327 + &meson8b_vclk_en.hw 1337 1328 }, 1338 1329 .num_parents = 1, 1339 1330 .flags = CLK_SET_RATE_PARENT, ··· 1387 1378 }, 1388 1379 }; 1389 1380 1381 + static struct clk_regmap meson8b_vclk2_clk_en = { 1382 + .data = &(struct clk_regmap_gate_data){ 1383 + .offset = HHI_VIID_CLK_DIV, 1384 + .bit_idx = 19, 1385 + }, 1386 + .hw.init = &(struct clk_init_data){ 1387 + .name = "vclk2_en", 1388 + .ops = &clk_regmap_gate_ro_ops, 1389 + .parent_hws = (const struct clk_hw *[]) { 1390 + &meson8b_vclk2_clk_in_en.hw 1391 + }, 1392 + .num_parents = 1, 1393 + .flags = CLK_SET_RATE_PARENT, 1394 + }, 1395 + }; 1396 + 1390 1397 static struct clk_regmap meson8b_vclk2_div1_gate = { 1391 1398 .data = &(struct clk_regmap_gate_data){ 1392 1399 .offset = HHI_VIID_CLK_DIV, ··· 1412 1387 .name = "vclk2_div1_en", 1413 1388 .ops = &clk_regmap_gate_ro_ops, 1414 1389 .parent_hws = (const struct clk_hw *[]) { 1415 - &meson8b_vclk2_clk_in_en.hw 1390 + &meson8b_vclk2_clk_en.hw 1416 1391 }, 1417 1392 .num_parents = 1, 1418 1393 .flags = CLK_SET_RATE_PARENT, ··· 1426 1401 .name = "vclk2_div2", 1427 1402 .ops = &clk_fixed_factor_ops, 1428 1403 .parent_hws = (const struct clk_hw *[]) { 1429 - &meson8b_vclk2_clk_in_en.hw 1404 + &meson8b_vclk2_clk_en.hw 1430 1405 }, 1431 1406 .num_parents = 1, 1432 1407 .flags = CLK_SET_RATE_PARENT, ··· 1456 1431 .name = "vclk2_div4", 1457 1432 .ops = &clk_fixed_factor_ops, 1458 1433 .parent_hws = (const struct clk_hw *[]) { 1459 - &meson8b_vclk2_clk_in_en.hw 1434 + &meson8b_vclk2_clk_en.hw 1460 1435 }, 1461 1436 .num_parents = 1, 1462 1437 .flags = CLK_SET_RATE_PARENT, ··· 1486 1461 .name = "vclk2_div6", 1487 1462 .ops = &clk_fixed_factor_ops, 1488 1463 .parent_hws = (const struct clk_hw *[]) { 1489 - &meson8b_vclk2_clk_in_en.hw 1464 + &meson8b_vclk2_clk_en.hw 1490 1465 }, 1491 1466 .num_parents = 1, 1492 1467 .flags = CLK_SET_RATE_PARENT, ··· 1516 1491 .name = "vclk2_div12", 1517 1492 .ops = &clk_fixed_factor_ops, 1518 1493 .parent_hws = (const struct clk_hw *[]) { 1519 - &meson8b_vclk2_clk_in_en.hw 1494 + &meson8b_vclk2_clk_en.hw 1520 1495 }, 1521 1496 .num_parents = 1, 1522 1497 .flags = CLK_SET_RATE_PARENT, ··· 2852 2827 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 2853 2828 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 2854 2829 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 2830 + [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 2855 2831 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, 2856 2832 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 2857 2833 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, ··· 2864 2838 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, 2865 2839 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 2866 2840 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, 2841 + [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, 2867 2842 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, 2868 2843 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 2869 2844 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, ··· 3059 3032 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 3060 3033 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 3061 3034 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 3035 + [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 3062 3036 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, 3063 3037 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 3064 3038 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, ··· 3071 3043 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, 3072 3044 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 3073 3045 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, 3046 + [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, 3074 3047 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, 3075 3048 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 3076 3049 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, ··· 3277 3248 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, 3278 3249 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, 3279 3250 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, 3251 + [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, 3280 3252 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, 3281 3253 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, 3282 3254 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, ··· 3289 3259 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, 3290 3260 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, 3291 3261 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, 3262 + [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, 3292 3263 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, 3293 3264 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, 3294 3265 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, ··· 3481 3450 &meson8b_vid_pll_final_div, 3482 3451 &meson8b_vclk_in_sel, 3483 3452 &meson8b_vclk_in_en, 3453 + &meson8b_vclk_en, 3484 3454 &meson8b_vclk_div1_gate, 3485 3455 &meson8b_vclk_div2_div_gate, 3486 3456 &meson8b_vclk_div4_div_gate, ··· 3489 3457 &meson8b_vclk_div12_div_gate, 3490 3458 &meson8b_vclk2_in_sel, 3491 3459 &meson8b_vclk2_clk_in_en, 3460 + &meson8b_vclk2_clk_en, 3492 3461 &meson8b_vclk2_div1_gate, 3493 3462 &meson8b_vclk2_div2_div_gate, 3494 3463 &meson8b_vclk2_div4_div_gate,

+3 -1

drivers/clk/meson/meson8b.h

··· 180 180 #define CLKID_CTS_AMCLK_DIV 208 181 181 #define CLKID_CTS_MCLK_I958_SEL 210 182 182 #define CLKID_CTS_MCLK_I958_DIV 211 183 + #define CLKID_VCLK_EN 214 184 + #define CLKID_VCLK2_EN 215 183 185 184 - #define CLK_NR_CLKS 214 186 + #define CLK_NR_CLKS 216 185 187 186 188 /* 187 189 * include the CLKID and RESETID that have

+2

include/dt-bindings/clock/g12a-clkc.h

··· 145 145 #define CLKID_CPU3_CLK 255 146 146 #define CLKID_SPICC0_SCLK 258 147 147 #define CLKID_SPICC1_SCLK 261 148 + #define CLKID_NNA_AXI_CLK 264 149 + #define CLKID_NNA_CORE_CLK 267 148 150 149 151 #endif /* __G12A_CLKC_H */