tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'for-2.6.25' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc into for-2.6.25

Paul Mackerras b370b082 75e89b02

+190 -174
+1
arch/powerpc/boot/dts/adder875-redboot.dts
··· 151 151 compatible = "fsl,mpc875-brg", 152 152 "fsl,cpm1-brg", 153 153 "fsl,cpm-brg"; 154 + clock-frequency = <50000000>; 154 155 reg = <0x9f0 0x10>; 155 156 }; 156 157
+1
arch/powerpc/boot/dts/adder875-uboot.dts
··· 150 150 compatible = "fsl,mpc875-brg", 151 151 "fsl,cpm1-brg", 152 152 "fsl,cpm-brg"; 153 + clock-frequency = <50000000>; 153 154 reg = <0x9f0 0x10>; 154 155 }; 155 156
+4
arch/powerpc/boot/dts/mpc8313erdb.dts
··· 118 118 interrupts = <14 0x8>; 119 119 interrupt-parent = <&ipic>; 120 120 dfsrr; 121 + rtc@68 { 122 + compatible = "dallas,ds1339"; 123 + reg = <0x68>; 124 + }; 121 125 }; 122 126 123 127 i2c@3100 {
+1 -1
arch/powerpc/boot/dts/mpc8315erdb.dts
··· 96 96 #address-cells = <1>; 97 97 #size-cells = <1>; 98 98 device_type = "soc"; 99 - compatible = "simple-bus"; 99 + compatible = "fsl,mpc8315-immr", "simple-bus"; 100 100 ranges = <0 0xe0000000 0x00100000>; 101 101 reg = <0xe0000000 0x00000200>; 102 102 bus-frequency = <0>;
+1 -1
arch/powerpc/boot/dts/mpc834x_mds.dts
··· 332 332 0xc000 0x0 0x0 0x3 &ipic 23 0x8 333 333 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; 334 334 interrupt-parent = <&ipic>; 335 - interrupts = <66 0x8>; 335 + interrupts = <67 0x8>; 336 336 bus-range = <0 0>; 337 337 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 338 338 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+12
arch/powerpc/boot/dts/mpc8572ds.dts
··· 42 42 bus-frequency = <0>; 43 43 clock-frequency = <0>; 44 44 }; 45 + 46 + PowerPC,8572@1 { 47 + device_type = "cpu"; 48 + reg = <1>; 49 + d-cache-line-size = <20>; // 32 bytes 50 + i-cache-line-size = <20>; // 32 bytes 51 + d-cache-size = <8000>; // L1, 32K 52 + i-cache-size = <8000>; // L1, 32K 53 + timebase-frequency = <0>; 54 + bus-frequency = <0>; 55 + clock-frequency = <0>; 56 + }; 45 57 }; 46 58 47 59 memory {
+1
arch/powerpc/boot/dts/mpc885ads.dts
··· 166 166 compatible = "fsl,mpc885-brg", 167 167 "fsl,cpm1-brg", 168 168 "fsl,cpm-brg"; 169 + clock-frequency = <0>; 169 170 reg = <9f0 10>; 170 171 }; 171 172
+6 -6
arch/powerpc/boot/dts/storcenter.dts
··· 15 15 16 16 / { 17 17 model = "StorCenter"; 18 - compatible = "storcenter"; 18 + compatible = "iomega,storcenter"; 19 19 #address-cells = <1>; 20 20 #size-cells = <1>; 21 21 ··· 62 62 #size-cells = <0>; 63 63 compatible = "fsl-i2c"; 64 64 reg = <0x3000 0x100>; 65 - interrupts = <5 2>; 65 + interrupts = <17 2>; 66 66 interrupt-parent = <&mpic>; 67 67 68 68 rtc@68 { 69 69 compatible = "dallas,ds1337"; 70 - reg = <68>; 70 + reg = <0x68>; 71 71 }; 72 72 }; 73 73 ··· 78 78 reg = <0x4500 0x20>; 79 79 clock-frequency = <97553800>; /* Hz */ 80 80 current-speed = <115200>; 81 - interrupts = <9 2>; 81 + interrupts = <25 2>; 82 82 interrupt-parent = <&mpic>; 83 83 }; 84 84 ··· 89 89 reg = <0x4600 0x20>; 90 90 clock-frequency = <97553800>; /* Hz */ 91 91 current-speed = <9600>; 92 - interrupts = <10 2>; 92 + interrupts = <26 2>; 93 93 interrupt-parent = <&mpic>; 94 94 }; 95 95 ··· 136 136 }; 137 137 138 138 chosen { 139 - linux,stdout-path = "/soc/serial@4500"; 139 + linux,stdout-path = &serial0; 140 140 }; 141 141 };
+5 -5
arch/powerpc/configs/mpc83xx_defconfig
··· 186 186 # CONFIG_PREEMPT is not set 187 187 CONFIG_BINFMT_ELF=y 188 188 # CONFIG_BINFMT_MISC is not set 189 - # CONFIG_MATH_EMULATION is not set 189 + CONFIG_MATH_EMULATION=y 190 190 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 191 191 CONFIG_ARCH_FLATMEM_ENABLE=y 192 192 CONFIG_ARCH_POPULATES_NODE_MAP=y ··· 416 416 # MII PHY device drivers 417 417 # 418 418 CONFIG_MARVELL_PHY=y 419 - # CONFIG_DAVICOM_PHY is not set 419 + CONFIG_DAVICOM_PHY=y 420 420 # CONFIG_QSEMI_PHY is not set 421 421 # CONFIG_LXT_PHY is not set 422 422 # CONFIG_CICADA_PHY is not set 423 - # CONFIG_VITESSE_PHY is not set 423 + CONFIG_VITESSE_PHY=y 424 424 # CONFIG_SMSC_PHY is not set 425 425 # CONFIG_BROADCOM_PHY is not set 426 - # CONFIG_ICPLUS_PHY is not set 426 + CONFIG_ICPLUS_PHY=y 427 427 # CONFIG_FIXED_PHY is not set 428 428 # CONFIG_MDIO_BITBANG is not set 429 429 CONFIG_NET_ETHERNET=y ··· 436 436 CONFIG_NETDEV_1000=y 437 437 CONFIG_GIANFAR=y 438 438 # CONFIG_GFAR_NAPI is not set 439 - # CONFIG_UCC_GETH is not set 439 + CONFIG_UCC_GETH=y 440 440 CONFIG_NETDEV_10000=y 441 441 442 442 #
+8 -2
arch/powerpc/kernel/cputable.c
··· 959 959 .icache_bsize = 32, 960 960 .dcache_bsize = 32, 961 961 .cpu_setup = __setup_cpu_603, 962 + .num_pmcs = 4, 963 + .oprofile_cpu_type = "ppc/e300", 964 + .oprofile_type = PPC_OPROFILE_FSL_EMB, 962 965 .platform = "ppc603", 963 966 }, 964 967 { /* e300c4 (e300c1, plus one IU) */ ··· 974 971 .dcache_bsize = 32, 975 972 .cpu_setup = __setup_cpu_603, 976 973 .machine_check = machine_check_generic, 974 + .num_pmcs = 4, 975 + .oprofile_cpu_type = "ppc/e300", 976 + .oprofile_type = PPC_OPROFILE_FSL_EMB, 977 977 .platform = "ppc603", 978 978 }, 979 979 { /* default match, we assume split I/D cache & TB (non-601)... */ ··· 1441 1435 .dcache_bsize = 32, 1442 1436 .num_pmcs = 4, 1443 1437 .oprofile_cpu_type = "ppc/e500", 1444 - .oprofile_type = PPC_OPROFILE_BOOKE, 1438 + .oprofile_type = PPC_OPROFILE_FSL_EMB, 1445 1439 .machine_check = machine_check_e500, 1446 1440 .platform = "ppc8540", 1447 1441 }, ··· 1459 1453 .dcache_bsize = 32, 1460 1454 .num_pmcs = 4, 1461 1455 .oprofile_cpu_type = "ppc/e500", 1462 - .oprofile_type = PPC_OPROFILE_BOOKE, 1456 + .oprofile_type = PPC_OPROFILE_FSL_EMB, 1463 1457 .machine_check = machine_check_e500, 1464 1458 .platform = "ppc8548", 1465 1459 },
+1 -1
arch/powerpc/kernel/pmc.c
··· 26 26 27 27 static void dummy_perf(struct pt_regs *regs) 28 28 { 29 - #if defined(CONFIG_FSL_BOOKE) && !defined(CONFIG_E200) 29 + #if defined(CONFIG_FSL_EMB_PERFMON) 30 30 mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE); 31 31 #elif defined(CONFIG_PPC64) || defined(CONFIG_6xx) 32 32 if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
+1 -1
arch/powerpc/oprofile/Makefile
··· 15 15 cell/spu_profiler.o cell/vma_map.o \ 16 16 cell/spu_task_sync.o 17 17 oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o 18 - oprofile-$(CONFIG_FSL_BOOKE) += op_model_fsl_booke.o 18 + oprofile-$(CONFIG_FSL_EMB_PERFMON) += op_model_fsl_emb.o 19 19 oprofile-$(CONFIG_6xx) += op_model_7450.o
+3 -3
arch/powerpc/oprofile/common.c
··· 202 202 model = &op_model_7450; 203 203 break; 204 204 #endif 205 - #ifdef CONFIG_FSL_BOOKE 206 - case PPC_OPROFILE_BOOKE: 207 - model = &op_model_fsl_booke; 205 + #if defined(CONFIG_FSL_EMB_PERFMON) 206 + case PPC_OPROFILE_FSL_EMB: 207 + model = &op_model_fsl_emb; 208 208 break; 209 209 #endif 210 210 default:
+13 -15
arch/powerpc/oprofile/op_model_fsl_booke.c arch/powerpc/oprofile/op_model_fsl_emb.c
··· 1 1 /* 2 - * arch/powerpc/oprofile/op_model_fsl_booke.c 3 - * 4 - * Freescale Book-E oprofile support, based on ppc64 oprofile support 2 + * Freescale Embedded oprofile support, based on ppc64 oprofile support 5 3 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM 6 4 * 7 5 * Copyright (c) 2004 Freescale Semiconductor, Inc ··· 20 22 #include <asm/system.h> 21 23 #include <asm/processor.h> 22 24 #include <asm/cputable.h> 23 - #include <asm/reg_booke.h> 25 + #include <asm/reg_fsl_emb.h> 24 26 #include <asm/page.h> 25 27 #include <asm/pmc.h> 26 28 #include <asm/oprofile_impl.h> ··· 242 244 mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3)); 243 245 } 244 246 245 - static int fsl_booke_cpu_setup(struct op_counter_config *ctr) 247 + static int fsl_emb_cpu_setup(struct op_counter_config *ctr) 246 248 { 247 249 int i; 248 250 ··· 260 262 return 0; 261 263 } 262 264 263 - static int fsl_booke_reg_setup(struct op_counter_config *ctr, 265 + static int fsl_emb_reg_setup(struct op_counter_config *ctr, 264 266 struct op_system_config *sys, 265 267 int num_ctrs) 266 268 { ··· 279 281 return 0; 280 282 } 281 283 282 - static int fsl_booke_start(struct op_counter_config *ctr) 284 + static int fsl_emb_start(struct op_counter_config *ctr) 283 285 { 284 286 int i; 285 287 ··· 313 315 return 0; 314 316 } 315 317 316 - static void fsl_booke_stop(void) 318 + static void fsl_emb_stop(void) 317 319 { 318 320 /* freeze counters */ 319 321 pmc_stop_ctrs(); ··· 327 329 } 328 330 329 331 330 - static void fsl_booke_handle_interrupt(struct pt_regs *regs, 332 + static void fsl_emb_handle_interrupt(struct pt_regs *regs, 331 333 struct op_counter_config *ctr) 332 334 { 333 335 unsigned long pc; ··· 360 362 pmc_start_ctrs(1); 361 363 } 362 364 363 - struct op_powerpc_model op_model_fsl_booke = { 364 - .reg_setup = fsl_booke_reg_setup, 365 - .cpu_setup = fsl_booke_cpu_setup, 366 - .start = fsl_booke_start, 367 - .stop = fsl_booke_stop, 368 - .handle_interrupt = fsl_booke_handle_interrupt, 365 + struct op_powerpc_model op_model_fsl_emb = { 366 + .reg_setup = fsl_emb_reg_setup, 367 + .cpu_setup = fsl_emb_cpu_setup, 368 + .start = fsl_emb_start, 369 + .stop = fsl_emb_stop, 370 + .handle_interrupt = fsl_emb_handle_interrupt, 369 371 };
+1 -1
arch/powerpc/platforms/83xx/mpc832x_rdb.c
··· 101 101 #ifdef CONFIG_QUICC_ENGINE 102 102 qe_reset(); 103 103 104 - if ((np = of_find_node_by_name(np, "par_io")) != NULL) { 104 + if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { 105 105 par_io_init(np); 106 106 of_node_put(np); 107 107
+2
arch/powerpc/platforms/83xx/mpc83xx.h
··· 14 14 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000 15 15 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 16 16 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 17 + #define MPC8315_SCCR_USB_MASK 0x00c00000 18 + #define MPC8315_SCCR_USB_DRCM_11 0x00c00000 17 19 #define MPC837X_SCCR_USB_DRCM_11 0x00c00000 18 20 19 21 /* system i/o configuration register low */
+13 -4
arch/powerpc/platforms/83xx/usb.c
··· 104 104 u32 temp; 105 105 void __iomem *immap, *usb_regs; 106 106 struct device_node *np = NULL; 107 + struct device_node *immr_node = NULL; 107 108 const void *prop; 108 109 struct resource res; 109 110 int ret = 0; ··· 125 124 } 126 125 127 126 /* Configure clock */ 128 - temp = in_be32(immap + MPC83XX_SCCR_OFFS); 129 - temp &= ~MPC83XX_SCCR_USB_MASK; 130 - temp |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */ 131 - out_be32(immap + MPC83XX_SCCR_OFFS, temp); 127 + immr_node = of_get_parent(np); 128 + if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) 129 + clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, 130 + MPC8315_SCCR_USB_MASK, 131 + MPC8315_SCCR_USB_DRCM_11); 132 + else 133 + clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, 134 + MPC83XX_SCCR_USB_MASK, 135 + MPC83XX_SCCR_USB_DRCM_11); 132 136 133 137 /* Configure pin mux for ULPI. There is no pin mux for UTMI */ 134 138 if (prop && !strcmp(prop, "ulpi")) { ··· 149 143 } 150 144 151 145 iounmap(immap); 146 + 147 + if (immr_node) 148 + of_node_put(immr_node); 152 149 153 150 /* Map USB SOC space */ 154 151 ret = of_address_to_resource(np, 0, &res);
+3 -3
arch/powerpc/platforms/8xx/adder875.c
··· 15 15 16 16 #include <asm/time.h> 17 17 #include <asm/machdep.h> 18 - #include <asm/commproc.h> 18 + #include <asm/cpm1.h> 19 19 #include <asm/fs_pd.h> 20 20 #include <asm/udbg.h> 21 21 #include <asm/prom.h> 22 22 23 - #include <sysdev/commproc.h> 23 + #include "mpc8xx.h" 24 24 25 25 struct cpm_pin { 26 26 int port, pin, flags; ··· 108 108 .name = "Adder MPC875", 109 109 .probe = adder875_probe, 110 110 .setup_arch = adder875_setup, 111 - .init_IRQ = m8xx_pic_init, 111 + .init_IRQ = mpc8xx_pics_init, 112 112 .get_irq = mpc8xx_get_irq, 113 113 .restart = mpc8xx_restart, 114 114 .calibrate_decr = generic_calibrate_decr,
-1
arch/powerpc/platforms/8xx/ep88xc.c
··· 15 15 #include <asm/machdep.h> 16 16 #include <asm/io.h> 17 17 #include <asm/udbg.h> 18 - #include <asm/commproc.h> 19 18 #include <asm/cpm1.h> 20 19 21 20 #include "mpc8xx.h"
+1
arch/powerpc/platforms/Kconfig
··· 24 24 select MPC83xx 25 25 select IPIC 26 26 select WANT_DEVICE_TREE 27 + select FSL_EMB_PERFMON 27 28 28 29 config PPC_86xx 29 30 bool "Freescale 86xx"
+4
arch/powerpc/platforms/Kconfig.cputype
··· 94 94 bool 95 95 96 96 config E500 97 + select FSL_EMB_PERFMON 97 98 bool 98 99 99 100 config PPC_FPU ··· 115 114 bool 116 115 depends on E200 || E500 117 116 default y 117 + 118 + config FSL_EMB_PERFMON 119 + bool 118 120 119 121 config PTE_64BIT 120 122 bool
+5 -20
arch/powerpc/platforms/embedded6xx/storcenter.c
··· 132 132 133 133 paddr = (phys_addr_t)of_translate_address(dnp, prop); 134 134 mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET, 135 - 4, 32, " EPIC "); 135 + 16, 32, " OpenPIC "); 136 136 137 137 of_node_put(dnp); 138 138 139 139 BUG_ON(mpic == NULL); 140 140 141 - /* PCI IRQs */ 142 141 /* 143 - * 2.6.12 patch: 144 - * openpic_set_sources(0, 5, OpenPIC_Addr + 0x10200); 145 - * openpic_set_sources(5, 2, OpenPIC_Addr + 0x11120); 146 - * first_irq, num_irqs, __iomem first_ISR 147 - * o_ss: i, src: 0, fdf50200 148 - * o_ss: i, src: 1, fdf50220 149 - * o_ss: i, src: 2, fdf50240 150 - * o_ss: i, src: 3, fdf50260 151 - * o_ss: i, src: 4, fdf50280 152 - * o_ss: i, src: 5, fdf51120 153 - * o_ss: i, src: 6, fdf51140 142 + * 16 Serial Interrupts followed by 16 Internal Interrupts. 143 + * I2C is the second internal, so it is at 17, 0x11020. 154 144 */ 155 145 mpic_assign_isu(mpic, 0, paddr + 0x10200); 156 - mpic_assign_isu(mpic, 1, paddr + 0x10220); 157 - mpic_assign_isu(mpic, 2, paddr + 0x10240); 158 - mpic_assign_isu(mpic, 3, paddr + 0x10260); 159 - mpic_assign_isu(mpic, 4, paddr + 0x10280); 160 - mpic_assign_isu(mpic, 5, paddr + 0x11120); 161 - mpic_assign_isu(mpic, 6, paddr + 0x11140); 146 + mpic_assign_isu(mpic, 1, paddr + 0x11000); 162 147 163 148 mpic_init(mpic); 164 149 } ··· 163 178 { 164 179 unsigned long root = of_get_flat_dt_root(); 165 180 166 - return of_flat_dt_is_compatible(root, "storcenter"); 181 + return of_flat_dt_is_compatible(root, "iomega,storcenter"); 167 182 } 168 183 169 184 define_machine(storcenter){
+1 -1
arch/powerpc/sysdev/fsl_soc.c
··· 1342 1342 if (ret) 1343 1343 goto unreg; 1344 1344 1345 - ret = platform_device_register(pdev); 1345 + ret = platform_device_add(pdev); 1346 1346 if (ret) 1347 1347 goto unreg; 1348 1348
+5 -5
arch/powerpc/sysdev/qe_lib/qe.c
··· 66 66 { 67 67 struct device_node *qe; 68 68 unsigned int size; 69 - const void *prop; 69 + const u32 *prop; 70 70 71 71 if (qebase != -1) 72 72 return qebase; ··· 79 79 } 80 80 81 81 prop = of_get_property(qe, "reg", &size); 82 - qebase = of_translate_address(qe, prop); 82 + if (prop && size >= sizeof(*prop)) 83 + qebase = of_translate_address(qe, prop); 83 84 of_node_put(qe); 84 85 85 86 return qebase; ··· 173 172 } 174 173 175 174 prop = of_get_property(qe, "brg-frequency", &size); 176 - if (!prop || size != sizeof(*prop)) 177 - return brg_clk; 175 + if (prop && size == sizeof(*prop)) 176 + brg_clk = *prop; 178 177 179 - brg_clk = *prop; 180 178 of_node_put(qe); 181 179 182 180 return brg_clk;
+1 -3
drivers/net/Kconfig
··· 1737 1737 1738 1738 config CPMAC 1739 1739 tristate "TI AR7 CPMAC Ethernet support (EXPERIMENTAL)" 1740 - depends on NET_ETHERNET && EXPERIMENTAL && AR7 1740 + depends on NET_ETHERNET && EXPERIMENTAL && AR7 && BROKEN 1741 1741 select PHYLIB 1742 - select FIXED_PHY 1743 - select FIXED_MII_100_FDX 1744 1742 help 1745 1743 TI AR7 CPMAC Ethernet support 1746 1744
+18 -37
drivers/net/cpmac.c
··· 845 845 spin_unlock(&priv->lock); 846 846 } 847 847 848 - static int cpmac_link_update(struct net_device *dev, 849 - struct fixed_phy_status *status) 850 - { 851 - status->link = 1; 852 - status->speed = 100; 853 - status->duplex = 1; 854 - return 0; 855 - } 856 - 857 848 static int cpmac_open(struct net_device *dev) 858 849 { 859 850 int i, size, res; ··· 987 996 static int __devinit cpmac_probe(struct platform_device *pdev) 988 997 { 989 998 int rc, phy_id, i; 999 + int mdio_bus_id = cpmac_mii.id; 990 1000 struct resource *mem; 991 1001 struct cpmac_priv *priv; 992 1002 struct net_device *dev; 993 1003 struct plat_cpmac_data *pdata; 994 - struct fixed_info *fixed_phy; 995 1004 DECLARE_MAC_BUF(mac); 996 1005 997 1006 pdata = pdev->dev.platform_data; ··· 1005 1014 } 1006 1015 1007 1016 if (phy_id == PHY_MAX_ADDR) { 1008 - if (external_switch || dumb_switch) 1017 + if (external_switch || dumb_switch) { 1018 + struct fixed_phy_status status = {}; 1019 + 1020 + mdio_bus_id = 0; 1021 + 1022 + /* 1023 + * FIXME: this should be in the platform code! 1024 + * Since there is not platform code at all (that is, 1025 + * no mainline users of that driver), place it here 1026 + * for now. 1027 + */ 1009 1028 phy_id = 0; 1010 - else { 1029 + status.link = 1; 1030 + status.duplex = 1; 1031 + status.speed = 100; 1032 + fixed_phy_add(PHY_POLL, phy_id, &status); 1033 + } else { 1011 1034 printk(KERN_ERR "cpmac: no PHY present\n"); 1012 1035 return -ENODEV; 1013 1036 } ··· 1065 1060 priv->msg_enable = netif_msg_init(debug_level, 0xff); 1066 1061 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr)); 1067 1062 1068 - if (phy_id == 31) { 1069 - snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, cpmac_mii.id, 1070 - phy_id); 1071 - } else { 1072 - /* Let's try to get a free fixed phy... */ 1073 - for (i = 0; i < MAX_PHY_AMNT; i++) { 1074 - fixed_phy = fixed_mdio_get_phydev(i); 1075 - if (!fixed_phy) 1076 - continue; 1077 - if (!fixed_phy->phydev->attached_dev) { 1078 - strncpy(priv->phy_name, 1079 - fixed_phy->phydev->dev.bus_id, 1080 - BUS_ID_SIZE); 1081 - fixed_mdio_set_link_update(fixed_phy->phydev, 1082 - &cpmac_link_update); 1083 - goto phy_found; 1084 - } 1085 - } 1086 - if (netif_msg_drv(priv)) 1087 - printk(KERN_ERR "%s: Could not find fixed PHY\n", 1088 - dev->name); 1089 - rc = -ENODEV; 1090 - goto fail; 1091 - } 1063 + snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); 1092 1064 1093 - phy_found: 1094 1065 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0, 1095 1066 PHY_INTERFACE_MODE_MII); 1096 1067 if (IS_ERR(priv->phy)) {
+1 -1
include/asm-powerpc/cputable.h
··· 46 46 PPC_OPROFILE_RS64 = 1, 47 47 PPC_OPROFILE_POWER4 = 2, 48 48 PPC_OPROFILE_G4 = 3, 49 - PPC_OPROFILE_BOOKE = 4, 49 + PPC_OPROFILE_FSL_EMB = 4, 50 50 PPC_OPROFILE_CELL = 5, 51 51 PPC_OPROFILE_PA6T = 6, 52 52 };
+1 -1
include/asm-powerpc/oprofile_impl.h
··· 54 54 int num_counters; 55 55 }; 56 56 57 - extern struct op_powerpc_model op_model_fsl_booke; 57 + extern struct op_powerpc_model op_model_fsl_emb; 58 58 extern struct op_powerpc_model op_model_rs64; 59 59 extern struct op_powerpc_model op_model_power4; 60 60 extern struct op_powerpc_model op_model_7450;
+4
include/asm-powerpc/reg.h
··· 18 18 #include <asm/reg_booke.h> 19 19 #endif /* CONFIG_BOOKE || CONFIG_40x */ 20 20 21 + #ifdef CONFIG_FSL_EMB_PERFMON 22 + #include <asm/reg_fsl_emb.h> 23 + #endif 24 + 21 25 #ifdef CONFIG_8xx 22 26 #include <asm/reg_8xx.h> 23 27 #endif /* CONFIG_8xx */
-62
include/asm-powerpc/reg_booke.h
··· 9 9 #ifndef __ASM_POWERPC_REG_BOOKE_H__ 10 10 #define __ASM_POWERPC_REG_BOOKE_H__ 11 11 12 - #ifndef __ASSEMBLY__ 13 - /* Performance Monitor Registers */ 14 - #define mfpmr(rn) ({unsigned int rval; \ 15 - asm volatile("mfpmr %0," __stringify(rn) \ 16 - : "=r" (rval)); rval;}) 17 - #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) 18 - #endif /* __ASSEMBLY__ */ 19 - 20 - /* Freescale Book E Performance Monitor APU Registers */ 21 - #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ 22 - #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ 23 - #define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ 24 - #define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ 25 - #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ 26 - #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ 27 - #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ 28 - #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ 29 - 30 - #define PMLCA_FC 0x80000000 /* Freeze Counter */ 31 - #define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ 32 - #define PMLCA_FCU 0x20000000 /* Freeze in User */ 33 - #define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ 34 - #define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ 35 - #define PMLCA_CE 0x04000000 /* Condition Enable */ 36 - 37 - #define PMLCA_EVENT_MASK 0x007f0000 /* Event field */ 38 - #define PMLCA_EVENT_SHIFT 16 39 - 40 - #define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ 41 - #define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ 42 - #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ 43 - #define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ 44 - 45 - #define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */ 46 - #define PMLCB_THRESHMUL_SHIFT 8 47 - 48 - #define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ 49 - #define PMLCB_THRESHOLD_SHIFT 0 50 - 51 - #define PMRN_PMGC0 0x190 /* PM Global Control 0 */ 52 - 53 - #define PMGC0_FAC 0x80000000 /* Freeze all Counters */ 54 - #define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ 55 - #define PMGC0_FCECE 0x20000000 /* Freeze countes on 56 - Enabled Condition or 57 - Event */ 58 - 59 - #define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ 60 - #define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ 61 - #define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ 62 - #define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ 63 - #define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ 64 - #define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ 65 - #define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ 66 - #define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ 67 - #define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ 68 - #define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ 69 - #define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ 70 - #define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ 71 - #define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ 72 - 73 - 74 12 /* Machine State Register (MSR) Fields */ 75 13 #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ 76 14 #define MSR_SPE (1<<25) /* Enable SPE */
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include/asm-powerpc/reg_fsl_emb.h
··· 1 + /* 2 + * Contains register definitions for the Freescale Embedded Performance 3 + * Monitor. 4 + */ 5 + #ifdef __KERNEL__ 6 + #ifndef __ASM_POWERPC_REG_FSL_EMB_H__ 7 + #define __ASM_POWERPC_REG_FSL_EMB_H__ 8 + 9 + #ifndef __ASSEMBLY__ 10 + /* Performance Monitor Registers */ 11 + #define mfpmr(rn) ({unsigned int rval; \ 12 + asm volatile("mfpmr %0," __stringify(rn) \ 13 + : "=r" (rval)); rval;}) 14 + #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) 15 + #endif /* __ASSEMBLY__ */ 16 + 17 + /* Freescale Book E Performance Monitor APU Registers */ 18 + #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ 19 + #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ 20 + #define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ 21 + #define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ 22 + #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ 23 + #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ 24 + #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ 25 + #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ 26 + 27 + #define PMLCA_FC 0x80000000 /* Freeze Counter */ 28 + #define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ 29 + #define PMLCA_FCU 0x20000000 /* Freeze in User */ 30 + #define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ 31 + #define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ 32 + #define PMLCA_CE 0x04000000 /* Condition Enable */ 33 + 34 + #define PMLCA_EVENT_MASK 0x007f0000 /* Event field */ 35 + #define PMLCA_EVENT_SHIFT 16 36 + 37 + #define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ 38 + #define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ 39 + #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ 40 + #define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ 41 + 42 + #define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */ 43 + #define PMLCB_THRESHMUL_SHIFT 8 44 + 45 + #define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ 46 + #define PMLCB_THRESHOLD_SHIFT 0 47 + 48 + #define PMRN_PMGC0 0x190 /* PM Global Control 0 */ 49 + 50 + #define PMGC0_FAC 0x80000000 /* Freeze all Counters */ 51 + #define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ 52 + #define PMGC0_FCECE 0x20000000 /* Freeze countes on 53 + Enabled Condition or 54 + Event */ 55 + 56 + #define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ 57 + #define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ 58 + #define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ 59 + #define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ 60 + #define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ 61 + #define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ 62 + #define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ 63 + #define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ 64 + #define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ 65 + #define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ 66 + #define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ 67 + #define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ 68 + #define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ 69 + 70 + 71 + #endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */ 72 + #endif /* __KERNEL__ */