Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
spi/mpc8xxx: refactor the common code for SPI/eSPI controller
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.
Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
authored by
Mingkai Hu
and committed by
Grant Likely
b36ece83
3272029f
+5
drivers/spi/Kconfig
+5
drivers/spi/Kconfig
···
182
This enables using the Freescale MPC5121 Programmable Serial
183
Controller in SPI master mode.
184
185
config SPI_FSL_SPI
186
tristate "Freescale SPI controller"
187
depends on FSL_SOC
188
help
189
This enables using the Freescale SPI controllers in master mode.
190
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
···
182
This enables using the Freescale MPC5121 Programmable Serial
183
Controller in SPI master mode.
184
185
+
config SPI_FSL_LIB
186
+
tristate
187
+
depends on FSL_SOC
188
+
189
config SPI_FSL_SPI
190
tristate "Freescale SPI controller"
191
depends on FSL_SOC
192
+
select SPI_FSL_LIB
193
help
194
This enables using the Freescale SPI controllers in master mode.
195
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
+1
drivers/spi/Makefile
+1
drivers/spi/Makefile
···
32
obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
33
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
34
obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
35
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
36
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
37
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
···
32
obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
33
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
34
obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
35
+
obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
36
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
37
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
38
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
+237
drivers/spi/spi_fsl_lib.c
+237
drivers/spi/spi_fsl_lib.c
···
···
1
+
/*
2
+
* Freescale SPI/eSPI controller driver library.
3
+
*
4
+
* Maintainer: Kumar Gala
5
+
*
6
+
* Copyright (C) 2006 Polycom, Inc.
7
+
*
8
+
* CPM SPI and QE buffer descriptors mode support:
9
+
* Copyright (c) 2009 MontaVista Software, Inc.
10
+
* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11
+
*
12
+
* Copyright 2010 Freescale Semiconductor, Inc.
13
+
*
14
+
* This program is free software; you can redistribute it and/or modify it
15
+
* under the terms of the GNU General Public License as published by the
16
+
* Free Software Foundation; either version 2 of the License, or (at your
17
+
* option) any later version.
18
+
*/
19
+
#include <linux/kernel.h>
20
+
#include <linux/interrupt.h>
21
+
#include <linux/fsl_devices.h>
22
+
#include <linux/dma-mapping.h>
23
+
#include <linux/mm.h>
24
+
#include <linux/of_platform.h>
25
+
#include <linux/of_spi.h>
26
+
#include <sysdev/fsl_soc.h>
27
+
28
+
#include "spi_fsl_lib.h"
29
+
30
+
#define MPC8XXX_SPI_RX_BUF(type) \
31
+
void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
32
+
{ \
33
+
type *rx = mpc8xxx_spi->rx; \
34
+
*rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
35
+
mpc8xxx_spi->rx = rx; \
36
+
}
37
+
38
+
#define MPC8XXX_SPI_TX_BUF(type) \
39
+
u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
40
+
{ \
41
+
u32 data; \
42
+
const type *tx = mpc8xxx_spi->tx; \
43
+
if (!tx) \
44
+
return 0; \
45
+
data = *tx++ << mpc8xxx_spi->tx_shift; \
46
+
mpc8xxx_spi->tx = tx; \
47
+
return data; \
48
+
}
49
+
50
+
MPC8XXX_SPI_RX_BUF(u8)
51
+
MPC8XXX_SPI_RX_BUF(u16)
52
+
MPC8XXX_SPI_RX_BUF(u32)
53
+
MPC8XXX_SPI_TX_BUF(u8)
54
+
MPC8XXX_SPI_TX_BUF(u16)
55
+
MPC8XXX_SPI_TX_BUF(u32)
56
+
57
+
struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
58
+
{
59
+
return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
60
+
}
61
+
62
+
void mpc8xxx_spi_work(struct work_struct *work)
63
+
{
64
+
struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
65
+
work);
66
+
67
+
spin_lock_irq(&mpc8xxx_spi->lock);
68
+
while (!list_empty(&mpc8xxx_spi->queue)) {
69
+
struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
70
+
struct spi_message, queue);
71
+
72
+
list_del_init(&m->queue);
73
+
spin_unlock_irq(&mpc8xxx_spi->lock);
74
+
75
+
if (mpc8xxx_spi->spi_do_one_msg)
76
+
mpc8xxx_spi->spi_do_one_msg(m);
77
+
78
+
spin_lock_irq(&mpc8xxx_spi->lock);
79
+
}
80
+
spin_unlock_irq(&mpc8xxx_spi->lock);
81
+
}
82
+
83
+
int mpc8xxx_spi_transfer(struct spi_device *spi,
84
+
struct spi_message *m)
85
+
{
86
+
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
87
+
unsigned long flags;
88
+
89
+
m->actual_length = 0;
90
+
m->status = -EINPROGRESS;
91
+
92
+
spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
93
+
list_add_tail(&m->queue, &mpc8xxx_spi->queue);
94
+
queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
95
+
spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
96
+
97
+
return 0;
98
+
}
99
+
100
+
void mpc8xxx_spi_cleanup(struct spi_device *spi)
101
+
{
102
+
kfree(spi->controller_state);
103
+
}
104
+
105
+
const char *mpc8xxx_spi_strmode(unsigned int flags)
106
+
{
107
+
if (flags & SPI_QE_CPU_MODE) {
108
+
return "QE CPU";
109
+
} else if (flags & SPI_CPM_MODE) {
110
+
if (flags & SPI_QE)
111
+
return "QE";
112
+
else if (flags & SPI_CPM2)
113
+
return "CPM2";
114
+
else
115
+
return "CPM1";
116
+
}
117
+
return "CPU";
118
+
}
119
+
120
+
int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
121
+
unsigned int irq)
122
+
{
123
+
struct fsl_spi_platform_data *pdata = dev->platform_data;
124
+
struct spi_master *master;
125
+
struct mpc8xxx_spi *mpc8xxx_spi;
126
+
int ret = 0;
127
+
128
+
master = dev_get_drvdata(dev);
129
+
130
+
/* the spi->mode bits understood by this driver: */
131
+
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
132
+
| SPI_LSB_FIRST | SPI_LOOP;
133
+
134
+
master->transfer = mpc8xxx_spi_transfer;
135
+
master->cleanup = mpc8xxx_spi_cleanup;
136
+
master->dev.of_node = dev->of_node;
137
+
138
+
mpc8xxx_spi = spi_master_get_devdata(master);
139
+
mpc8xxx_spi->dev = dev;
140
+
mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
141
+
mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
142
+
mpc8xxx_spi->flags = pdata->flags;
143
+
mpc8xxx_spi->spibrg = pdata->sysclk;
144
+
mpc8xxx_spi->irq = irq;
145
+
146
+
mpc8xxx_spi->rx_shift = 0;
147
+
mpc8xxx_spi->tx_shift = 0;
148
+
149
+
init_completion(&mpc8xxx_spi->done);
150
+
151
+
master->bus_num = pdata->bus_num;
152
+
master->num_chipselect = pdata->max_chipselect;
153
+
154
+
spin_lock_init(&mpc8xxx_spi->lock);
155
+
init_completion(&mpc8xxx_spi->done);
156
+
INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
157
+
INIT_LIST_HEAD(&mpc8xxx_spi->queue);
158
+
159
+
mpc8xxx_spi->workqueue = create_singlethread_workqueue(
160
+
dev_name(master->dev.parent));
161
+
if (mpc8xxx_spi->workqueue == NULL) {
162
+
ret = -EBUSY;
163
+
goto err;
164
+
}
165
+
166
+
return 0;
167
+
168
+
err:
169
+
return ret;
170
+
}
171
+
172
+
int __devexit mpc8xxx_spi_remove(struct device *dev)
173
+
{
174
+
struct mpc8xxx_spi *mpc8xxx_spi;
175
+
struct spi_master *master;
176
+
177
+
master = dev_get_drvdata(dev);
178
+
mpc8xxx_spi = spi_master_get_devdata(master);
179
+
180
+
flush_workqueue(mpc8xxx_spi->workqueue);
181
+
destroy_workqueue(mpc8xxx_spi->workqueue);
182
+
spi_unregister_master(master);
183
+
184
+
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
185
+
186
+
if (mpc8xxx_spi->spi_remove)
187
+
mpc8xxx_spi->spi_remove(mpc8xxx_spi);
188
+
189
+
return 0;
190
+
}
191
+
192
+
int __devinit of_mpc8xxx_spi_probe(struct platform_device *ofdev,
193
+
const struct of_device_id *ofid)
194
+
{
195
+
struct device *dev = &ofdev->dev;
196
+
struct device_node *np = ofdev->dev.of_node;
197
+
struct mpc8xxx_spi_probe_info *pinfo;
198
+
struct fsl_spi_platform_data *pdata;
199
+
const void *prop;
200
+
int ret = -ENOMEM;
201
+
202
+
pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
203
+
if (!pinfo)
204
+
return -ENOMEM;
205
+
206
+
pdata = &pinfo->pdata;
207
+
dev->platform_data = pdata;
208
+
209
+
/* Allocate bus num dynamically. */
210
+
pdata->bus_num = -1;
211
+
212
+
/* SPI controller is either clocked from QE or SoC clock. */
213
+
pdata->sysclk = get_brgfreq();
214
+
if (pdata->sysclk == -1) {
215
+
pdata->sysclk = fsl_get_sys_freq();
216
+
if (pdata->sysclk == -1) {
217
+
ret = -ENODEV;
218
+
goto err;
219
+
}
220
+
}
221
+
222
+
prop = of_get_property(np, "mode", NULL);
223
+
if (prop && !strcmp(prop, "cpu-qe"))
224
+
pdata->flags = SPI_QE_CPU_MODE;
225
+
else if (prop && !strcmp(prop, "qe"))
226
+
pdata->flags = SPI_CPM_MODE | SPI_QE;
227
+
else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
228
+
pdata->flags = SPI_CPM_MODE | SPI_CPM2;
229
+
else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
230
+
pdata->flags = SPI_CPM_MODE | SPI_CPM1;
231
+
232
+
return 0;
233
+
234
+
err:
235
+
kfree(pinfo);
236
+
return ret;
237
+
}
+119
drivers/spi/spi_fsl_lib.h
+119
drivers/spi/spi_fsl_lib.h
···
···
1
+
/*
2
+
* Freescale SPI/eSPI controller driver library.
3
+
*
4
+
* Maintainer: Kumar Gala
5
+
*
6
+
* Copyright 2010 Freescale Semiconductor, Inc.
7
+
* Copyright (C) 2006 Polycom, Inc.
8
+
*
9
+
* CPM SPI and QE buffer descriptors mode support:
10
+
* Copyright (c) 2009 MontaVista Software, Inc.
11
+
* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
12
+
*
13
+
* This program is free software; you can redistribute it and/or modify it
14
+
* under the terms of the GNU General Public License as published by the
15
+
* Free Software Foundation; either version 2 of the License, or (at your
16
+
* option) any later version.
17
+
*/
18
+
#ifndef __SPI_FSL_LIB_H__
19
+
#define __SPI_FSL_LIB_H__
20
+
21
+
/* SPI/eSPI Controller driver's private data. */
22
+
struct mpc8xxx_spi {
23
+
struct device *dev;
24
+
void *reg_base;
25
+
26
+
/* rx & tx bufs from the spi_transfer */
27
+
const void *tx;
28
+
void *rx;
29
+
30
+
int subblock;
31
+
struct spi_pram __iomem *pram;
32
+
struct cpm_buf_desc __iomem *tx_bd;
33
+
struct cpm_buf_desc __iomem *rx_bd;
34
+
35
+
struct spi_transfer *xfer_in_progress;
36
+
37
+
/* dma addresses for CPM transfers */
38
+
dma_addr_t tx_dma;
39
+
dma_addr_t rx_dma;
40
+
bool map_tx_dma;
41
+
bool map_rx_dma;
42
+
43
+
dma_addr_t dma_dummy_tx;
44
+
dma_addr_t dma_dummy_rx;
45
+
46
+
/* functions to deal with different sized buffers */
47
+
void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
48
+
u32(*get_tx) (struct mpc8xxx_spi *);
49
+
50
+
/* hooks for different controller driver */
51
+
void (*spi_do_one_msg) (struct spi_message *m);
52
+
void (*spi_remove) (struct mpc8xxx_spi *mspi);
53
+
54
+
unsigned int count;
55
+
unsigned int irq;
56
+
57
+
unsigned nsecs; /* (clock cycle time)/2 */
58
+
59
+
u32 spibrg; /* SPIBRG input clock */
60
+
u32 rx_shift; /* RX data reg shift when in qe mode */
61
+
u32 tx_shift; /* TX data reg shift when in qe mode */
62
+
63
+
unsigned int flags;
64
+
65
+
struct workqueue_struct *workqueue;
66
+
struct work_struct work;
67
+
68
+
struct list_head queue;
69
+
spinlock_t lock;
70
+
71
+
struct completion done;
72
+
};
73
+
74
+
struct spi_mpc8xxx_cs {
75
+
/* functions to deal with different sized buffers */
76
+
void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
77
+
u32 (*get_tx) (struct mpc8xxx_spi *);
78
+
u32 rx_shift; /* RX data reg shift when in qe mode */
79
+
u32 tx_shift; /* TX data reg shift when in qe mode */
80
+
u32 hw_mode; /* Holds HW mode register settings */
81
+
};
82
+
83
+
static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
84
+
{
85
+
out_be32(reg, val);
86
+
}
87
+
88
+
static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
89
+
{
90
+
return in_be32(reg);
91
+
}
92
+
93
+
struct mpc8xxx_spi_probe_info {
94
+
struct fsl_spi_platform_data pdata;
95
+
int *gpios;
96
+
bool *alow_flags;
97
+
};
98
+
99
+
extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
100
+
extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
101
+
extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
102
+
extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
103
+
extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
104
+
extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
105
+
106
+
extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
107
+
struct fsl_spi_platform_data *pdata);
108
+
extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
109
+
struct spi_transfer *t, unsigned int len);
110
+
extern int mpc8xxx_spi_transfer(struct spi_device *spi, struct spi_message *m);
111
+
extern void mpc8xxx_spi_cleanup(struct spi_device *spi);
112
+
extern const char *mpc8xxx_spi_strmode(unsigned int flags);
113
+
extern int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
114
+
unsigned int irq);
115
+
extern int mpc8xxx_spi_remove(struct device *dev);
116
+
extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev,
117
+
const struct of_device_id *ofid);
118
+
119
+
#endif /* __SPI_FSL_LIB_H__ */
+160
-392
drivers/spi/spi_fsl_spi.c
+160
-392
drivers/spi/spi_fsl_spi.c
···
1
/*
2
-
* MPC8xxx SPI controller driver.
3
*
4
* Maintainer: Kumar Gala
5
*
6
* Copyright (C) 2006 Polycom, Inc.
7
*
8
* CPM SPI and QE buffer descriptors mode support:
9
* Copyright (c) 2009 MontaVista Software, Inc.
···
16
* option) any later version.
17
*/
18
#include <linux/module.h>
19
-
#include <linux/init.h>
20
#include <linux/types.h>
21
#include <linux/kernel.h>
22
-
#include <linux/bug.h>
23
-
#include <linux/errno.h>
24
-
#include <linux/err.h>
25
-
#include <linux/io.h>
26
-
#include <linux/completion.h>
27
#include <linux/interrupt.h>
28
#include <linux/delay.h>
29
#include <linux/irq.h>
30
-
#include <linux/device.h>
31
#include <linux/spi/spi.h>
32
#include <linux/spi/spi_bitbang.h>
33
#include <linux/platform_device.h>
···
32
#include <linux/of_platform.h>
33
#include <linux/gpio.h>
34
#include <linux/of_gpio.h>
35
-
#include <linux/slab.h>
36
37
#include <sysdev/fsl_soc.h>
38
#include <asm/cpm.h>
39
#include <asm/qe.h>
40
-
#include <asm/irq.h>
41
42
/* CPM1 and CPM2 are mutually exclusive. */
43
#ifdef CONFIG_CPM1
···
49
#endif
50
51
/* SPI Controller registers */
52
-
struct mpc8xxx_spi_reg {
53
u8 res1[0x20];
54
__be32 mode;
55
__be32 event;
···
74
75
/*
76
* Default for SPI Mode:
77
-
* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
78
*/
79
#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
80
SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
···
96
#define SPI_PRAM_SIZE 0x100
97
#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
98
99
-
/* SPI Controller driver's private data. */
100
-
struct mpc8xxx_spi {
101
-
struct device *dev;
102
-
struct mpc8xxx_spi_reg __iomem *base;
103
104
-
/* rx & tx bufs from the spi_transfer */
105
-
const void *tx;
106
-
void *rx;
107
-
108
-
int subblock;
109
-
struct spi_pram __iomem *pram;
110
-
struct cpm_buf_desc __iomem *tx_bd;
111
-
struct cpm_buf_desc __iomem *rx_bd;
112
-
113
-
struct spi_transfer *xfer_in_progress;
114
-
115
-
/* dma addresses for CPM transfers */
116
-
dma_addr_t tx_dma;
117
-
dma_addr_t rx_dma;
118
-
bool map_tx_dma;
119
-
bool map_rx_dma;
120
-
121
-
dma_addr_t dma_dummy_tx;
122
-
dma_addr_t dma_dummy_rx;
123
-
124
-
/* functions to deal with different sized buffers */
125
-
void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
126
-
u32(*get_tx) (struct mpc8xxx_spi *);
127
-
128
-
unsigned int count;
129
-
unsigned int irq;
130
-
131
-
unsigned nsecs; /* (clock cycle time)/2 */
132
-
133
-
u32 spibrg; /* SPIBRG input clock */
134
-
u32 rx_shift; /* RX data reg shift when in qe mode */
135
-
u32 tx_shift; /* TX data reg shift when in qe mode */
136
-
137
-
unsigned int flags;
138
-
139
-
struct workqueue_struct *workqueue;
140
-
struct work_struct work;
141
-
142
-
struct list_head queue;
143
-
spinlock_t lock;
144
-
145
-
struct completion done;
146
-
};
147
-
148
-
static void *mpc8xxx_dummy_rx;
149
-
static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
150
-
static int mpc8xxx_dummy_rx_refcnt;
151
-
152
-
struct spi_mpc8xxx_cs {
153
-
/* functions to deal with different sized buffers */
154
-
void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
155
-
u32 (*get_tx) (struct mpc8xxx_spi *);
156
-
u32 rx_shift; /* RX data reg shift when in qe mode */
157
-
u32 tx_shift; /* TX data reg shift when in qe mode */
158
-
u32 hw_mode; /* Holds HW mode register settings */
159
-
};
160
-
161
-
static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
162
-
{
163
-
out_be32(reg, val);
164
-
}
165
-
166
-
static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
167
-
{
168
-
return in_be32(reg);
169
-
}
170
-
171
-
#define MPC83XX_SPI_RX_BUF(type) \
172
-
static \
173
-
void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
174
-
{ \
175
-
type *rx = mpc8xxx_spi->rx; \
176
-
*rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
177
-
mpc8xxx_spi->rx = rx; \
178
-
}
179
-
180
-
#define MPC83XX_SPI_TX_BUF(type) \
181
-
static \
182
-
u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
183
-
{ \
184
-
u32 data; \
185
-
const type *tx = mpc8xxx_spi->tx; \
186
-
if (!tx) \
187
-
return 0; \
188
-
data = *tx++ << mpc8xxx_spi->tx_shift; \
189
-
mpc8xxx_spi->tx = tx; \
190
-
return data; \
191
-
}
192
-
193
-
MPC83XX_SPI_RX_BUF(u8)
194
-
MPC83XX_SPI_RX_BUF(u16)
195
-
MPC83XX_SPI_RX_BUF(u32)
196
-
MPC83XX_SPI_TX_BUF(u8)
197
-
MPC83XX_SPI_TX_BUF(u16)
198
-
MPC83XX_SPI_TX_BUF(u32)
199
-
200
-
static void mpc8xxx_spi_change_mode(struct spi_device *spi)
201
{
202
struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
203
struct spi_mpc8xxx_cs *cs = spi->controller_state;
204
-
__be32 __iomem *mode = &mspi->base->mode;
205
unsigned long flags;
206
207
if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
···
136
local_irq_restore(flags);
137
}
138
139
-
static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
140
{
141
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
142
struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
···
154
mpc8xxx_spi->get_rx = cs->get_rx;
155
mpc8xxx_spi->get_tx = cs->get_tx;
156
157
-
mpc8xxx_spi_change_mode(spi);
158
159
if (pdata->cs_control)
160
pdata->cs_control(spi, pol);
161
}
162
}
163
164
-
static int
165
-
mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
166
-
struct spi_device *spi,
167
-
struct mpc8xxx_spi *mpc8xxx_spi,
168
-
int bits_per_word)
169
{
170
cs->rx_shift = 0;
171
cs->tx_shift = 0;
···
204
return bits_per_word;
205
}
206
207
-
static int
208
-
mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
209
-
struct spi_device *spi,
210
-
int bits_per_word)
211
{
212
/* QE uses Little Endian for words > 8
213
* so transform all words > 8 into 8 bits
···
222
return bits_per_word;
223
}
224
225
-
static
226
-
int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
227
{
228
struct mpc8xxx_spi *mpc8xxx_spi;
229
-
int bits_per_word;
230
u8 pm;
231
-
u32 hz;
232
struct spi_mpc8xxx_cs *cs = spi->controller_state;
233
234
mpc8xxx_spi = spi_master_get_devdata(spi->master);
···
236
if (t) {
237
bits_per_word = t->bits_per_word;
238
hz = t->speed_hz;
239
-
} else {
240
-
bits_per_word = 0;
241
-
hz = 0;
242
}
243
244
/* spi_transfer level calls that work per-word */
···
281
hz, mpc8xxx_spi->spibrg / 1024);
282
if (pm > 16)
283
pm = 16;
284
-
} else
285
pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
286
if (pm)
287
pm--;
288
289
cs->hw_mode |= SPMODE_PM(pm);
290
291
-
mpc8xxx_spi_change_mode(spi);
292
return 0;
293
}
294
295
-
static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
296
{
297
struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
298
struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
299
unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
300
unsigned int xfer_ofs;
301
302
xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
303
···
319
BD_SC_LAST);
320
321
/* start transfer */
322
-
mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
323
}
324
325
-
static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
326
struct spi_transfer *t, bool is_dma_mapped)
327
{
328
struct device *dev = mspi->dev;
329
330
if (is_dma_mapped) {
331
mspi->map_tx_dma = 0;
···
371
}
372
373
/* enable rx ints */
374
-
mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
375
376
mspi->xfer_in_progress = t;
377
mspi->count = t->len;
378
379
/* start CPM transfers */
380
-
mpc8xxx_spi_cpm_bufs_start(mspi);
381
382
return 0;
383
···
387
return -ENOMEM;
388
}
389
390
-
static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
391
{
392
struct device *dev = mspi->dev;
393
struct spi_transfer *t = mspi->xfer_in_progress;
···
399
mspi->xfer_in_progress = NULL;
400
}
401
402
-
static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
403
struct spi_transfer *t, unsigned int len)
404
{
405
u32 word;
406
407
mspi->count = len;
408
409
/* enable rx ints */
410
-
mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
411
412
/* transmit word */
413
word = mspi->get_tx(mspi);
414
-
mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
415
416
return 0;
417
}
418
419
-
static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
420
bool is_dma_mapped)
421
{
422
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
423
unsigned int len = t->len;
424
u8 bits_per_word;
425
int ret;
426
427
bits_per_word = spi->bits_per_word;
428
if (t->bits_per_word)
429
bits_per_word = t->bits_per_word;
···
450
INIT_COMPLETION(mpc8xxx_spi->done);
451
452
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
453
-
ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
454
else
455
-
ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
456
if (ret)
457
return ret;
458
459
wait_for_completion(&mpc8xxx_spi->done);
460
461
/* disable rx ints */
462
-
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
463
464
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
465
-
mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
466
467
return mpc8xxx_spi->count;
468
}
469
470
-
static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
471
{
472
struct spi_device *spi = m->spi;
473
struct spi_transfer *t;
···
483
status = -EINVAL;
484
485
if (cs_change)
486
-
status = mpc8xxx_spi_setup_transfer(spi, t);
487
if (status < 0)
488
break;
489
}
490
491
if (cs_change) {
492
-
mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
493
ndelay(nsecs);
494
}
495
cs_change = t->cs_change;
496
if (t->len)
497
-
status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
498
if (status) {
499
status = -EMSGSIZE;
500
break;
···
506
507
if (cs_change) {
508
ndelay(nsecs);
509
-
mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
510
ndelay(nsecs);
511
}
512
}
···
516
517
if (status || !cs_change) {
518
ndelay(nsecs);
519
-
mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
520
}
521
522
-
mpc8xxx_spi_setup_transfer(spi, NULL);
523
}
524
525
-
static void mpc8xxx_spi_work(struct work_struct *work)
526
-
{
527
-
struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
528
-
work);
529
-
530
-
spin_lock_irq(&mpc8xxx_spi->lock);
531
-
while (!list_empty(&mpc8xxx_spi->queue)) {
532
-
struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
533
-
struct spi_message, queue);
534
-
535
-
list_del_init(&m->queue);
536
-
spin_unlock_irq(&mpc8xxx_spi->lock);
537
-
538
-
mpc8xxx_spi_do_one_msg(m);
539
-
540
-
spin_lock_irq(&mpc8xxx_spi->lock);
541
-
}
542
-
spin_unlock_irq(&mpc8xxx_spi->lock);
543
-
}
544
-
545
-
static int mpc8xxx_spi_setup(struct spi_device *spi)
546
{
547
struct mpc8xxx_spi *mpc8xxx_spi;
548
int retval;
549
u32 hw_mode;
550
struct spi_mpc8xxx_cs *cs = spi->controller_state;
···
541
}
542
mpc8xxx_spi = spi_master_get_devdata(spi->master);
543
544
hw_mode = cs->hw_mode; /* Save original settings */
545
-
cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
546
/* mask out bits we are going to set */
547
cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
548
| SPMODE_REV | SPMODE_LOOP);
···
558
if (spi->mode & SPI_LOOP)
559
cs->hw_mode |= SPMODE_LOOP;
560
561
-
retval = mpc8xxx_spi_setup_transfer(spi, NULL);
562
if (retval < 0) {
563
cs->hw_mode = hw_mode; /* Restore settings */
564
return retval;
···
566
return 0;
567
}
568
569
-
static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
570
{
571
u16 len;
572
573
dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
574
in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
···
581
}
582
583
/* Clear the events */
584
-
mpc8xxx_spi_write_reg(&mspi->base->event, events);
585
586
mspi->count -= len;
587
if (mspi->count)
588
-
mpc8xxx_spi_cpm_bufs_start(mspi);
589
else
590
complete(&mspi->done);
591
}
592
593
-
static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
594
{
595
/* We need handle RX first */
596
if (events & SPIE_NE) {
597
-
u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
598
599
if (mspi->rx)
600
mspi->get_rx(rx_data, mspi);
···
605
if ((events & SPIE_NF) == 0)
606
/* spin until TX is done */
607
while (((events =
608
-
mpc8xxx_spi_read_reg(&mspi->base->event)) &
609
SPIE_NF) == 0)
610
cpu_relax();
611
612
/* Clear the events */
613
-
mpc8xxx_spi_write_reg(&mspi->base->event, events);
614
615
mspi->count -= 1;
616
if (mspi->count) {
617
u32 word = mspi->get_tx(mspi);
618
619
-
mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
620
} else {
621
complete(&mspi->done);
622
}
623
}
624
625
-
static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
626
{
627
struct mpc8xxx_spi *mspi = context_data;
628
irqreturn_t ret = IRQ_NONE;
629
u32 events;
630
631
/* Get interrupt events(tx/rx) */
632
-
events = mpc8xxx_spi_read_reg(&mspi->base->event);
633
if (events)
634
ret = IRQ_HANDLED;
635
636
dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
637
638
if (mspi->flags & SPI_CPM_MODE)
639
-
mpc8xxx_spi_cpm_irq(mspi, events);
640
else
641
-
mpc8xxx_spi_cpu_irq(mspi, events);
642
643
return ret;
644
}
645
646
-
static int mpc8xxx_spi_transfer(struct spi_device *spi,
647
-
struct spi_message *m)
648
{
649
-
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
650
-
unsigned long flags;
651
652
-
m->actual_length = 0;
653
-
m->status = -EINPROGRESS;
654
655
-
spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
656
-
list_add_tail(&m->queue, &mpc8xxx_spi->queue);
657
-
queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
658
-
spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
659
660
-
return 0;
661
}
662
663
-
664
-
static void mpc8xxx_spi_cleanup(struct spi_device *spi)
665
{
666
-
kfree(spi->controller_state);
667
-
}
668
669
-
static void *mpc8xxx_spi_alloc_dummy_rx(void)
670
-
{
671
-
mutex_lock(&mpc8xxx_dummy_rx_lock);
672
-
673
-
if (!mpc8xxx_dummy_rx)
674
-
mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
675
-
if (mpc8xxx_dummy_rx)
676
-
mpc8xxx_dummy_rx_refcnt++;
677
-
678
-
mutex_unlock(&mpc8xxx_dummy_rx_lock);
679
-
680
-
return mpc8xxx_dummy_rx;
681
-
}
682
-
683
-
static void mpc8xxx_spi_free_dummy_rx(void)
684
-
{
685
-
mutex_lock(&mpc8xxx_dummy_rx_lock);
686
-
687
-
switch (mpc8xxx_dummy_rx_refcnt) {
688
case 0:
689
WARN_ON(1);
690
break;
691
case 1:
692
-
kfree(mpc8xxx_dummy_rx);
693
-
mpc8xxx_dummy_rx = NULL;
694
/* fall through */
695
default:
696
-
mpc8xxx_dummy_rx_refcnt--;
697
break;
698
}
699
700
-
mutex_unlock(&mpc8xxx_dummy_rx_lock);
701
}
702
703
-
static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
704
{
705
struct device *dev = mspi->dev;
706
struct device_node *np = dev->of_node;
···
732
return pram_ofs;
733
}
734
735
-
static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
736
{
737
struct device *dev = mspi->dev;
738
struct device_node *np = dev->of_node;
···
744
if (!(mspi->flags & SPI_CPM_MODE))
745
return 0;
746
747
-
if (!mpc8xxx_spi_alloc_dummy_rx())
748
return -ENOMEM;
749
750
if (mspi->flags & SPI_QE) {
···
765
}
766
}
767
768
-
pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
769
if (IS_ERR_VALUE(pram_ofs)) {
770
dev_err(dev, "can't allocate spi parameter ram\n");
771
goto err_pram;
···
785
goto err_dummy_tx;
786
}
787
788
-
mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
789
DMA_FROM_DEVICE);
790
if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
791
dev_err(dev, "unable to map dummy rx buffer\n");
···
823
err_bds:
824
cpm_muram_free(pram_ofs);
825
err_pram:
826
-
mpc8xxx_spi_free_dummy_rx();
827
return -ENOMEM;
828
}
829
830
-
static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
831
{
832
struct device *dev = mspi->dev;
833
···
835
dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
836
cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
837
cpm_muram_free(cpm_muram_offset(mspi->pram));
838
-
mpc8xxx_spi_free_dummy_rx();
839
}
840
841
-
static const char *mpc8xxx_spi_strmode(unsigned int flags)
842
{
843
-
if (flags & SPI_QE_CPU_MODE) {
844
-
return "QE CPU";
845
-
} else if (flags & SPI_CPM_MODE) {
846
-
if (flags & SPI_QE)
847
-
return "QE";
848
-
else if (flags & SPI_CPM2)
849
-
return "CPM2";
850
-
else
851
-
return "CPM1";
852
-
}
853
-
return "CPU";
854
}
855
856
-
static struct spi_master * __devinit
857
-
mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
858
{
859
struct fsl_spi_platform_data *pdata = dev->platform_data;
860
struct spi_master *master;
861
struct mpc8xxx_spi *mpc8xxx_spi;
862
u32 regval;
863
int ret = 0;
864
···
862
863
dev_set_drvdata(dev, master);
864
865
-
/* the spi->mode bits understood by this driver: */
866
-
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
867
-
| SPI_LSB_FIRST | SPI_LOOP;
868
869
-
master->setup = mpc8xxx_spi_setup;
870
-
master->transfer = mpc8xxx_spi_transfer;
871
-
master->cleanup = mpc8xxx_spi_cleanup;
872
-
master->dev.of_node = dev->of_node;
873
874
mpc8xxx_spi = spi_master_get_devdata(master);
875
-
mpc8xxx_spi->dev = dev;
876
-
mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
877
-
mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
878
-
mpc8xxx_spi->flags = pdata->flags;
879
-
mpc8xxx_spi->spibrg = pdata->sysclk;
880
881
-
ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
882
if (ret)
883
goto err_cpm_init;
884
885
-
mpc8xxx_spi->rx_shift = 0;
886
-
mpc8xxx_spi->tx_shift = 0;
887
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
888
mpc8xxx_spi->rx_shift = 16;
889
mpc8xxx_spi->tx_shift = 24;
890
}
891
892
-
init_completion(&mpc8xxx_spi->done);
893
-
894
-
mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
895
-
if (mpc8xxx_spi->base == NULL) {
896
ret = -ENOMEM;
897
goto err_ioremap;
898
}
899
900
-
mpc8xxx_spi->irq = irq;
901
-
902
/* Register for SPI Interrupt */
903
-
ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
904
-
0, "mpc8xxx_spi", mpc8xxx_spi);
905
906
if (ret != 0)
907
-
goto unmap_io;
908
909
-
master->bus_num = pdata->bus_num;
910
-
master->num_chipselect = pdata->max_chipselect;
911
912
/* SPI controller initializations */
913
-
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
914
-
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
915
-
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
916
-
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
917
918
/* Enable SPI interface */
919
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
920
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
921
regval |= SPMODE_OP;
922
923
-
mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
924
-
spin_lock_init(&mpc8xxx_spi->lock);
925
-
init_completion(&mpc8xxx_spi->done);
926
-
INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
927
-
INIT_LIST_HEAD(&mpc8xxx_spi->queue);
928
-
929
-
mpc8xxx_spi->workqueue = create_singlethread_workqueue(
930
-
dev_name(master->dev.parent));
931
-
if (mpc8xxx_spi->workqueue == NULL) {
932
-
ret = -EBUSY;
933
-
goto free_irq;
934
-
}
935
936
ret = spi_register_master(master);
937
if (ret < 0)
938
goto unreg_master;
939
940
-
dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
941
mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
942
943
return master;
944
945
unreg_master:
946
-
destroy_workqueue(mpc8xxx_spi->workqueue);
947
-
free_irq:
948
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
949
-
unmap_io:
950
-
iounmap(mpc8xxx_spi->base);
951
err_ioremap:
952
-
mpc8xxx_spi_cpm_free(mpc8xxx_spi);
953
err_cpm_init:
954
spi_master_put(master);
955
err:
956
return ERR_PTR(ret);
957
}
958
959
-
static int __devexit mpc8xxx_spi_remove(struct device *dev)
960
-
{
961
-
struct mpc8xxx_spi *mpc8xxx_spi;
962
-
struct spi_master *master;
963
-
964
-
master = dev_get_drvdata(dev);
965
-
mpc8xxx_spi = spi_master_get_devdata(master);
966
-
967
-
flush_workqueue(mpc8xxx_spi->workqueue);
968
-
destroy_workqueue(mpc8xxx_spi->workqueue);
969
-
spi_unregister_master(master);
970
-
971
-
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
972
-
iounmap(mpc8xxx_spi->base);
973
-
mpc8xxx_spi_cpm_free(mpc8xxx_spi);
974
-
975
-
return 0;
976
-
}
977
-
978
-
struct mpc8xxx_spi_probe_info {
979
-
struct fsl_spi_platform_data pdata;
980
-
int *gpios;
981
-
bool *alow_flags;
982
-
};
983
-
984
-
static struct mpc8xxx_spi_probe_info *
985
-
to_of_pinfo(struct fsl_spi_platform_data *pdata)
986
-
{
987
-
return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
988
-
}
989
-
990
-
static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
991
{
992
struct device *dev = spi->dev.parent;
993
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
···
943
gpio_set_value(gpio, on ^ alow);
944
}
945
946
-
static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
947
{
948
struct device_node *np = dev->of_node;
949
struct fsl_spi_platform_data *pdata = dev->platform_data;
···
1004
}
1005
1006
pdata->max_chipselect = ngpios;
1007
-
pdata->cs_control = mpc8xxx_spi_cs_control;
1008
1009
return 0;
1010
···
1023
return ret;
1024
}
1025
1026
-
static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1027
{
1028
struct fsl_spi_platform_data *pdata = dev->platform_data;
1029
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
···
1042
return 0;
1043
}
1044
1045
-
static int __devinit of_mpc8xxx_spi_probe(struct platform_device *ofdev,
1046
-
const struct of_device_id *ofid)
1047
{
1048
struct device *dev = &ofdev->dev;
1049
struct device_node *np = ofdev->dev.of_node;
1050
-
struct mpc8xxx_spi_probe_info *pinfo;
1051
-
struct fsl_spi_platform_data *pdata;
1052
struct spi_master *master;
1053
struct resource mem;
1054
struct resource irq;
1055
-
const void *prop;
1056
int ret = -ENOMEM;
1057
1058
-
pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1059
-
if (!pinfo)
1060
-
return -ENOMEM;
1061
1062
-
pdata = &pinfo->pdata;
1063
-
dev->platform_data = pdata;
1064
-
1065
-
/* Allocate bus num dynamically. */
1066
-
pdata->bus_num = -1;
1067
-
1068
-
/* SPI controller is either clocked from QE or SoC clock. */
1069
-
pdata->sysclk = get_brgfreq();
1070
-
if (pdata->sysclk == -1) {
1071
-
pdata->sysclk = fsl_get_sys_freq();
1072
-
if (pdata->sysclk == -1) {
1073
-
ret = -ENODEV;
1074
-
goto err_clk;
1075
-
}
1076
-
}
1077
-
1078
-
prop = of_get_property(np, "mode", NULL);
1079
-
if (prop && !strcmp(prop, "cpu-qe"))
1080
-
pdata->flags = SPI_QE_CPU_MODE;
1081
-
else if (prop && !strcmp(prop, "qe"))
1082
-
pdata->flags = SPI_CPM_MODE | SPI_QE;
1083
-
else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1084
-
pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1085
-
else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1086
-
pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1087
-
1088
-
ret = of_mpc8xxx_spi_get_chipselects(dev);
1089
if (ret)
1090
goto err;
1091
···
1070
goto err;
1071
}
1072
1073
-
master = mpc8xxx_spi_probe(dev, &mem, irq.start);
1074
if (IS_ERR(master)) {
1075
ret = PTR_ERR(master);
1076
goto err;
···
1079
return 0;
1080
1081
err:
1082
-
of_mpc8xxx_spi_free_chipselects(dev);
1083
-
err_clk:
1084
-
kfree(pinfo);
1085
return ret;
1086
}
1087
1088
-
static int __devexit of_mpc8xxx_spi_remove(struct platform_device *ofdev)
1089
{
1090
int ret;
1091
1092
ret = mpc8xxx_spi_remove(&ofdev->dev);
1093
if (ret)
1094
return ret;
1095
-
of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
1096
return 0;
1097
}
1098
1099
-
static const struct of_device_id of_mpc8xxx_spi_match[] = {
1100
{ .compatible = "fsl,spi" },
1101
-
{},
1102
};
1103
-
MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
1104
1105
-
static struct of_platform_driver of_mpc8xxx_spi_driver = {
1106
.driver = {
1107
-
.name = "mpc8xxx_spi",
1108
.owner = THIS_MODULE,
1109
-
.of_match_table = of_mpc8xxx_spi_match,
1110
},
1111
-
.probe = of_mpc8xxx_spi_probe,
1112
-
.remove = __devexit_p(of_mpc8xxx_spi_remove),
1113
};
1114
1115
#ifdef CONFIG_MPC832x_RDB
1116
/*
1117
-
* XXX XXX XXX
1118
* This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1119
* only. The driver should go away soon, since newer MPC8323E-RDB's device
1120
* tree can work with OpenFirmware driver. But for now we support old trees
···
1135
if (irq <= 0)
1136
return -EINVAL;
1137
1138
-
master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
1139
if (IS_ERR(master))
1140
return PTR_ERR(master);
1141
return 0;
···
1174
static void __exit legacy_driver_unregister(void) {}
1175
#endif /* CONFIG_MPC832x_RDB */
1176
1177
-
static int __init mpc8xxx_spi_init(void)
1178
{
1179
legacy_driver_register();
1180
-
return of_register_platform_driver(&of_mpc8xxx_spi_driver);
1181
}
1182
1183
-
static void __exit mpc8xxx_spi_exit(void)
1184
{
1185
-
of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
1186
legacy_driver_unregister();
1187
}
1188
-
1189
-
module_init(mpc8xxx_spi_init);
1190
-
module_exit(mpc8xxx_spi_exit);
1191
1192
MODULE_AUTHOR("Kumar Gala");
1193
-
MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
1194
MODULE_LICENSE("GPL");
···
1
/*
2
+
* Freescale SPI controller driver.
3
*
4
* Maintainer: Kumar Gala
5
*
6
* Copyright (C) 2006 Polycom, Inc.
7
+
* Copyright 2010 Freescale Semiconductor, Inc.
8
*
9
* CPM SPI and QE buffer descriptors mode support:
10
* Copyright (c) 2009 MontaVista Software, Inc.
···
15
* option) any later version.
16
*/
17
#include <linux/module.h>
18
#include <linux/types.h>
19
#include <linux/kernel.h>
20
#include <linux/interrupt.h>
21
#include <linux/delay.h>
22
#include <linux/irq.h>
23
#include <linux/spi/spi.h>
24
#include <linux/spi/spi_bitbang.h>
25
#include <linux/platform_device.h>
···
38
#include <linux/of_platform.h>
39
#include <linux/gpio.h>
40
#include <linux/of_gpio.h>
41
42
#include <sysdev/fsl_soc.h>
43
#include <asm/cpm.h>
44
#include <asm/qe.h>
45
+
46
+
#include "spi_fsl_lib.h"
47
48
/* CPM1 and CPM2 are mutually exclusive. */
49
#ifdef CONFIG_CPM1
···
55
#endif
56
57
/* SPI Controller registers */
58
+
struct fsl_spi_reg {
59
u8 res1[0x20];
60
__be32 mode;
61
__be32 event;
···
80
81
/*
82
* Default for SPI Mode:
83
+
* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
84
*/
85
#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
86
SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
···
102
#define SPI_PRAM_SIZE 0x100
103
#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
104
105
+
static void *fsl_dummy_rx;
106
+
static DEFINE_MUTEX(fsl_dummy_rx_lock);
107
+
static int fsl_dummy_rx_refcnt;
108
109
+
static void fsl_spi_change_mode(struct spi_device *spi)
110
{
111
struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
112
struct spi_mpc8xxx_cs *cs = spi->controller_state;
113
+
struct fsl_spi_reg *reg_base = mspi->reg_base;
114
+
__be32 __iomem *mode = ®_base->mode;
115
unsigned long flags;
116
117
if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
···
238
local_irq_restore(flags);
239
}
240
241
+
static void fsl_spi_chipselect(struct spi_device *spi, int value)
242
{
243
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
244
struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
···
256
mpc8xxx_spi->get_rx = cs->get_rx;
257
mpc8xxx_spi->get_tx = cs->get_tx;
258
259
+
fsl_spi_change_mode(spi);
260
261
if (pdata->cs_control)
262
pdata->cs_control(spi, pol);
263
}
264
}
265
266
+
static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
267
+
struct spi_device *spi,
268
+
struct mpc8xxx_spi *mpc8xxx_spi,
269
+
int bits_per_word)
270
{
271
cs->rx_shift = 0;
272
cs->tx_shift = 0;
···
307
return bits_per_word;
308
}
309
310
+
static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
311
+
struct spi_device *spi,
312
+
int bits_per_word)
313
{
314
/* QE uses Little Endian for words > 8
315
* so transform all words > 8 into 8 bits
···
326
return bits_per_word;
327
}
328
329
+
static int fsl_spi_setup_transfer(struct spi_device *spi,
330
+
struct spi_transfer *t)
331
{
332
struct mpc8xxx_spi *mpc8xxx_spi;
333
+
int bits_per_word = 0;
334
u8 pm;
335
+
u32 hz = 0;
336
struct spi_mpc8xxx_cs *cs = spi->controller_state;
337
338
mpc8xxx_spi = spi_master_get_devdata(spi->master);
···
340
if (t) {
341
bits_per_word = t->bits_per_word;
342
hz = t->speed_hz;
343
}
344
345
/* spi_transfer level calls that work per-word */
···
388
hz, mpc8xxx_spi->spibrg / 1024);
389
if (pm > 16)
390
pm = 16;
391
+
} else {
392
pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
393
+
}
394
if (pm)
395
pm--;
396
397
cs->hw_mode |= SPMODE_PM(pm);
398
399
+
fsl_spi_change_mode(spi);
400
return 0;
401
}
402
403
+
static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
404
{
405
struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
406
struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
407
unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
408
unsigned int xfer_ofs;
409
+
struct fsl_spi_reg *reg_base = mspi->reg_base;
410
411
xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
412
···
424
BD_SC_LAST);
425
426
/* start transfer */
427
+
mpc8xxx_spi_write_reg(®_base->command, SPCOM_STR);
428
}
429
430
+
static int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
431
struct spi_transfer *t, bool is_dma_mapped)
432
{
433
struct device *dev = mspi->dev;
434
+
struct fsl_spi_reg *reg_base = mspi->reg_base;
435
436
if (is_dma_mapped) {
437
mspi->map_tx_dma = 0;
···
475
}
476
477
/* enable rx ints */
478
+
mpc8xxx_spi_write_reg(®_base->mask, SPIE_RXB);
479
480
mspi->xfer_in_progress = t;
481
mspi->count = t->len;
482
483
/* start CPM transfers */
484
+
fsl_spi_cpm_bufs_start(mspi);
485
486
return 0;
487
···
491
return -ENOMEM;
492
}
493
494
+
static void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
495
{
496
struct device *dev = mspi->dev;
497
struct spi_transfer *t = mspi->xfer_in_progress;
···
503
mspi->xfer_in_progress = NULL;
504
}
505
506
+
static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
507
struct spi_transfer *t, unsigned int len)
508
{
509
u32 word;
510
+
struct fsl_spi_reg *reg_base = mspi->reg_base;
511
512
mspi->count = len;
513
514
/* enable rx ints */
515
+
mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
516
517
/* transmit word */
518
word = mspi->get_tx(mspi);
519
+
mpc8xxx_spi_write_reg(®_base->transmit, word);
520
521
return 0;
522
}
523
524
+
static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
525
bool is_dma_mapped)
526
{
527
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
528
+
struct fsl_spi_reg *reg_base;
529
unsigned int len = t->len;
530
u8 bits_per_word;
531
int ret;
532
533
+
reg_base = mpc8xxx_spi->reg_base;
534
bits_per_word = spi->bits_per_word;
535
if (t->bits_per_word)
536
bits_per_word = t->bits_per_word;
···
551
INIT_COMPLETION(mpc8xxx_spi->done);
552
553
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
554
+
ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
555
else
556
+
ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
557
if (ret)
558
return ret;
559
560
wait_for_completion(&mpc8xxx_spi->done);
561
562
/* disable rx ints */
563
+
mpc8xxx_spi_write_reg(®_base->mask, 0);
564
565
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
566
+
fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
567
568
return mpc8xxx_spi->count;
569
}
570
571
+
static void fsl_spi_do_one_msg(struct spi_message *m)
572
{
573
struct spi_device *spi = m->spi;
574
struct spi_transfer *t;
···
584
status = -EINVAL;
585
586
if (cs_change)
587
+
status = fsl_spi_setup_transfer(spi, t);
588
if (status < 0)
589
break;
590
}
591
592
if (cs_change) {
593
+
fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
594
ndelay(nsecs);
595
}
596
cs_change = t->cs_change;
597
if (t->len)
598
+
status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
599
if (status) {
600
status = -EMSGSIZE;
601
break;
···
607
608
if (cs_change) {
609
ndelay(nsecs);
610
+
fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
611
ndelay(nsecs);
612
}
613
}
···
617
618
if (status || !cs_change) {
619
ndelay(nsecs);
620
+
fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
621
}
622
623
+
fsl_spi_setup_transfer(spi, NULL);
624
}
625
626
+
static int fsl_spi_setup(struct spi_device *spi)
627
{
628
struct mpc8xxx_spi *mpc8xxx_spi;
629
+
struct fsl_spi_reg *reg_base;
630
int retval;
631
u32 hw_mode;
632
struct spi_mpc8xxx_cs *cs = spi->controller_state;
···
661
}
662
mpc8xxx_spi = spi_master_get_devdata(spi->master);
663
664
+
reg_base = mpc8xxx_spi->reg_base;
665
+
666
hw_mode = cs->hw_mode; /* Save original settings */
667
+
cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
668
/* mask out bits we are going to set */
669
cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
670
| SPMODE_REV | SPMODE_LOOP);
···
676
if (spi->mode & SPI_LOOP)
677
cs->hw_mode |= SPMODE_LOOP;
678
679
+
retval = fsl_spi_setup_transfer(spi, NULL);
680
if (retval < 0) {
681
cs->hw_mode = hw_mode; /* Restore settings */
682
return retval;
···
684
return 0;
685
}
686
687
+
static void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
688
{
689
u16 len;
690
+
struct fsl_spi_reg *reg_base = mspi->reg_base;
691
692
dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
693
in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
···
698
}
699
700
/* Clear the events */
701
+
mpc8xxx_spi_write_reg(®_base->event, events);
702
703
mspi->count -= len;
704
if (mspi->count)
705
+
fsl_spi_cpm_bufs_start(mspi);
706
else
707
complete(&mspi->done);
708
}
709
710
+
static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
711
{
712
+
struct fsl_spi_reg *reg_base = mspi->reg_base;
713
+
714
/* We need handle RX first */
715
if (events & SPIE_NE) {
716
+
u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
717
718
if (mspi->rx)
719
mspi->get_rx(rx_data, mspi);
···
720
if ((events & SPIE_NF) == 0)
721
/* spin until TX is done */
722
while (((events =
723
+
mpc8xxx_spi_read_reg(®_base->event)) &
724
SPIE_NF) == 0)
725
cpu_relax();
726
727
/* Clear the events */
728
+
mpc8xxx_spi_write_reg(®_base->event, events);
729
730
mspi->count -= 1;
731
if (mspi->count) {
732
u32 word = mspi->get_tx(mspi);
733
734
+
mpc8xxx_spi_write_reg(®_base->transmit, word);
735
} else {
736
complete(&mspi->done);
737
}
738
}
739
740
+
static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
741
{
742
struct mpc8xxx_spi *mspi = context_data;
743
irqreturn_t ret = IRQ_NONE;
744
u32 events;
745
+
struct fsl_spi_reg *reg_base = mspi->reg_base;
746
747
/* Get interrupt events(tx/rx) */
748
+
events = mpc8xxx_spi_read_reg(®_base->event);
749
if (events)
750
ret = IRQ_HANDLED;
751
752
dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
753
754
if (mspi->flags & SPI_CPM_MODE)
755
+
fsl_spi_cpm_irq(mspi, events);
756
else
757
+
fsl_spi_cpu_irq(mspi, events);
758
759
return ret;
760
}
761
762
+
static void *fsl_spi_alloc_dummy_rx(void)
763
{
764
+
mutex_lock(&fsl_dummy_rx_lock);
765
766
+
if (!fsl_dummy_rx)
767
+
fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
768
+
if (fsl_dummy_rx)
769
+
fsl_dummy_rx_refcnt++;
770
771
+
mutex_unlock(&fsl_dummy_rx_lock);
772
773
+
return fsl_dummy_rx;
774
}
775
776
+
static void fsl_spi_free_dummy_rx(void)
777
{
778
+
mutex_lock(&fsl_dummy_rx_lock);
779
780
+
switch (fsl_dummy_rx_refcnt) {
781
case 0:
782
WARN_ON(1);
783
break;
784
case 1:
785
+
kfree(fsl_dummy_rx);
786
+
fsl_dummy_rx = NULL;
787
/* fall through */
788
default:
789
+
fsl_dummy_rx_refcnt--;
790
break;
791
}
792
793
+
mutex_unlock(&fsl_dummy_rx_lock);
794
}
795
796
+
static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
797
{
798
struct device *dev = mspi->dev;
799
struct device_node *np = dev->of_node;
···
869
return pram_ofs;
870
}
871
872
+
static int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
873
{
874
struct device *dev = mspi->dev;
875
struct device_node *np = dev->of_node;
···
881
if (!(mspi->flags & SPI_CPM_MODE))
882
return 0;
883
884
+
if (!fsl_spi_alloc_dummy_rx())
885
return -ENOMEM;
886
887
if (mspi->flags & SPI_QE) {
···
902
}
903
}
904
905
+
pram_ofs = fsl_spi_cpm_get_pram(mspi);
906
if (IS_ERR_VALUE(pram_ofs)) {
907
dev_err(dev, "can't allocate spi parameter ram\n");
908
goto err_pram;
···
922
goto err_dummy_tx;
923
}
924
925
+
mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR,
926
DMA_FROM_DEVICE);
927
if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
928
dev_err(dev, "unable to map dummy rx buffer\n");
···
960
err_bds:
961
cpm_muram_free(pram_ofs);
962
err_pram:
963
+
fsl_spi_free_dummy_rx();
964
return -ENOMEM;
965
}
966
967
+
static void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
968
{
969
struct device *dev = mspi->dev;
970
···
972
dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
973
cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
974
cpm_muram_free(cpm_muram_offset(mspi->pram));
975
+
fsl_spi_free_dummy_rx();
976
}
977
978
+
static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
979
{
980
+
iounmap(mspi->reg_base);
981
+
fsl_spi_cpm_free(mspi);
982
}
983
984
+
static struct spi_master * __devinit fsl_spi_probe(struct device *dev,
985
+
struct resource *mem, unsigned int irq)
986
{
987
struct fsl_spi_platform_data *pdata = dev->platform_data;
988
struct spi_master *master;
989
struct mpc8xxx_spi *mpc8xxx_spi;
990
+
struct fsl_spi_reg *reg_base;
991
u32 regval;
992
int ret = 0;
993
···
1007
1008
dev_set_drvdata(dev, master);
1009
1010
+
ret = mpc8xxx_spi_probe(dev, mem, irq);
1011
+
if (ret)
1012
+
goto err_probe;
1013
1014
+
master->setup = fsl_spi_setup;
1015
1016
mpc8xxx_spi = spi_master_get_devdata(master);
1017
+
mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
1018
+
mpc8xxx_spi->spi_remove = fsl_spi_remove;
1019
1020
+
1021
+
ret = fsl_spi_cpm_init(mpc8xxx_spi);
1022
if (ret)
1023
goto err_cpm_init;
1024
1025
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
1026
mpc8xxx_spi->rx_shift = 16;
1027
mpc8xxx_spi->tx_shift = 24;
1028
}
1029
1030
+
mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
1031
+
if (mpc8xxx_spi->reg_base == NULL) {
1032
ret = -ENOMEM;
1033
goto err_ioremap;
1034
}
1035
1036
/* Register for SPI Interrupt */
1037
+
ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
1038
+
0, "fsl_spi", mpc8xxx_spi);
1039
1040
if (ret != 0)
1041
+
goto free_irq;
1042
1043
+
reg_base = mpc8xxx_spi->reg_base;
1044
1045
/* SPI controller initializations */
1046
+
mpc8xxx_spi_write_reg(®_base->mode, 0);
1047
+
mpc8xxx_spi_write_reg(®_base->mask, 0);
1048
+
mpc8xxx_spi_write_reg(®_base->command, 0);
1049
+
mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
1050
1051
/* Enable SPI interface */
1052
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1053
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1054
regval |= SPMODE_OP;
1055
1056
+
mpc8xxx_spi_write_reg(®_base->mode, regval);
1057
1058
ret = spi_register_master(master);
1059
if (ret < 0)
1060
goto unreg_master;
1061
1062
+
dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
1063
mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1064
1065
return master;
1066
1067
unreg_master:
1068
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1069
+
free_irq:
1070
+
iounmap(mpc8xxx_spi->reg_base);
1071
err_ioremap:
1072
+
fsl_spi_cpm_free(mpc8xxx_spi);
1073
err_cpm_init:
1074
+
err_probe:
1075
spi_master_put(master);
1076
err:
1077
return ERR_PTR(ret);
1078
}
1079
1080
+
static void fsl_spi_cs_control(struct spi_device *spi, bool on)
1081
{
1082
struct device *dev = spi->dev.parent;
1083
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
···
1143
gpio_set_value(gpio, on ^ alow);
1144
}
1145
1146
+
static int of_fsl_spi_get_chipselects(struct device *dev)
1147
{
1148
struct device_node *np = dev->of_node;
1149
struct fsl_spi_platform_data *pdata = dev->platform_data;
···
1204
}
1205
1206
pdata->max_chipselect = ngpios;
1207
+
pdata->cs_control = fsl_spi_cs_control;
1208
1209
return 0;
1210
···
1223
return ret;
1224
}
1225
1226
+
static int of_fsl_spi_free_chipselects(struct device *dev)
1227
{
1228
struct fsl_spi_platform_data *pdata = dev->platform_data;
1229
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
···
1242
return 0;
1243
}
1244
1245
+
static int __devinit of_fsl_spi_probe(struct platform_device *ofdev,
1246
+
const struct of_device_id *ofid)
1247
{
1248
struct device *dev = &ofdev->dev;
1249
struct device_node *np = ofdev->dev.of_node;
1250
struct spi_master *master;
1251
struct resource mem;
1252
struct resource irq;
1253
int ret = -ENOMEM;
1254
1255
+
ret = of_mpc8xxx_spi_probe(ofdev, ofid);
1256
+
if (ret)
1257
+
return ret;
1258
1259
+
ret = of_fsl_spi_get_chipselects(dev);
1260
if (ret)
1261
goto err;
1262
···
1299
goto err;
1300
}
1301
1302
+
master = fsl_spi_probe(dev, &mem, irq.start);
1303
if (IS_ERR(master)) {
1304
ret = PTR_ERR(master);
1305
goto err;
···
1308
return 0;
1309
1310
err:
1311
+
of_fsl_spi_free_chipselects(dev);
1312
return ret;
1313
}
1314
1315
+
static int __devexit of_fsl_spi_remove(struct platform_device *ofdev)
1316
{
1317
int ret;
1318
1319
ret = mpc8xxx_spi_remove(&ofdev->dev);
1320
if (ret)
1321
return ret;
1322
+
of_fsl_spi_free_chipselects(&ofdev->dev);
1323
return 0;
1324
}
1325
1326
+
static const struct of_device_id of_fsl_spi_match[] = {
1327
{ .compatible = "fsl,spi" },
1328
+
{}
1329
};
1330
+
MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
1331
1332
+
static struct of_platform_driver of_fsl_spi_driver = {
1333
.driver = {
1334
+
.name = "fsl_spi",
1335
.owner = THIS_MODULE,
1336
+
.of_match_table = of_fsl_spi_match,
1337
},
1338
+
.probe = of_fsl_spi_probe,
1339
+
.remove = __devexit_p(of_fsl_spi_remove),
1340
};
1341
1342
#ifdef CONFIG_MPC832x_RDB
1343
/*
1344
+
* XXX XXX XXX
1345
* This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1346
* only. The driver should go away soon, since newer MPC8323E-RDB's device
1347
* tree can work with OpenFirmware driver. But for now we support old trees
···
1366
if (irq <= 0)
1367
return -EINVAL;
1368
1369
+
master = fsl_spi_probe(&pdev->dev, mem, irq);
1370
if (IS_ERR(master))
1371
return PTR_ERR(master);
1372
return 0;
···
1405
static void __exit legacy_driver_unregister(void) {}
1406
#endif /* CONFIG_MPC832x_RDB */
1407
1408
+
static int __init fsl_spi_init(void)
1409
{
1410
legacy_driver_register();
1411
+
return of_register_platform_driver(&of_fsl_spi_driver);
1412
}
1413
+
module_init(fsl_spi_init);
1414
1415
+
static void __exit fsl_spi_exit(void)
1416
{
1417
+
of_unregister_platform_driver(&of_fsl_spi_driver);
1418
legacy_driver_unregister();
1419
}
1420
+
module_exit(fsl_spi_exit);
1421
1422
MODULE_AUTHOR("Kumar Gala");
1423
+
MODULE_DESCRIPTION("Simple Freescale SPI Driver");
1424
MODULE_LICENSE("GPL");